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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.80 98.25 93.97 97.02 91.86 96.37 99.77 93.37


Total test records in report: 1108
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T1004 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.1765349638 Sep 04 05:09:01 AM UTC 24 Sep 04 05:09:04 AM UTC 24 29089160 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1354970478 Sep 04 05:09:01 AM UTC 24 Sep 04 05:09:04 AM UTC 24 14963933 ps
T1005 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1012345741 Sep 04 05:09:01 AM UTC 24 Sep 04 05:09:04 AM UTC 24 22123127 ps
T1006 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1268930635 Sep 04 05:09:03 AM UTC 24 Sep 04 05:09:05 AM UTC 24 36476938 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.215645054 Sep 04 05:09:02 AM UTC 24 Sep 04 05:09:05 AM UTC 24 157767185 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2977634611 Sep 04 05:09:04 AM UTC 24 Sep 04 05:09:06 AM UTC 24 14666373 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3665743326 Sep 04 05:09:01 AM UTC 24 Sep 04 05:09:06 AM UTC 24 101481336 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.892322259 Sep 04 05:09:03 AM UTC 24 Sep 04 05:09:06 AM UTC 24 28500995 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2588896792 Sep 04 05:09:01 AM UTC 24 Sep 04 05:09:06 AM UTC 24 148691998 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.879876092 Sep 04 05:09:05 AM UTC 24 Sep 04 05:09:07 AM UTC 24 24730058 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2781851862 Sep 04 05:09:03 AM UTC 24 Sep 04 05:09:07 AM UTC 24 78464374 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.1072382454 Sep 04 05:09:05 AM UTC 24 Sep 04 05:09:08 AM UTC 24 102268972 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.2936070476 Sep 04 05:09:06 AM UTC 24 Sep 04 05:09:08 AM UTC 24 18694189 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1619680651 Sep 04 05:09:06 AM UTC 24 Sep 04 05:09:08 AM UTC 24 11248586 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1455595307 Sep 04 05:09:07 AM UTC 24 Sep 04 05:09:10 AM UTC 24 16021241 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3209346243 Sep 04 05:09:05 AM UTC 24 Sep 04 05:09:09 AM UTC 24 206211690 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3725124303 Sep 04 05:09:05 AM UTC 24 Sep 04 05:09:09 AM UTC 24 141349114 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2076644194 Sep 04 05:09:07 AM UTC 24 Sep 04 05:09:10 AM UTC 24 35582092 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.315668063 Sep 04 05:09:08 AM UTC 24 Sep 04 05:09:11 AM UTC 24 12518574 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.515449687 Sep 04 05:09:09 AM UTC 24 Sep 04 05:09:11 AM UTC 24 22961260 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.548934232 Sep 04 05:09:05 AM UTC 24 Sep 04 05:09:11 AM UTC 24 51902884 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3208401677 Sep 04 05:09:09 AM UTC 24 Sep 04 05:09:11 AM UTC 24 24250748 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.184231545 Sep 04 05:09:10 AM UTC 24 Sep 04 05:09:12 AM UTC 24 45798258 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.727791633 Sep 04 05:09:10 AM UTC 24 Sep 04 05:09:12 AM UTC 24 13361270 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1606546803 Sep 04 05:09:07 AM UTC 24 Sep 04 05:09:12 AM UTC 24 41221199 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1694802830 Sep 04 05:09:11 AM UTC 24 Sep 04 05:09:13 AM UTC 24 35257979 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.696978373 Sep 04 05:09:07 AM UTC 24 Sep 04 05:09:13 AM UTC 24 173401499 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1425751187 Sep 04 05:09:10 AM UTC 24 Sep 04 05:09:13 AM UTC 24 55850110 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.41517709 Sep 04 05:09:11 AM UTC 24 Sep 04 05:09:14 AM UTC 24 115863691 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.438967509 Sep 04 05:09:12 AM UTC 24 Sep 04 05:09:14 AM UTC 24 94864626 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2919436287 Sep 04 05:09:10 AM UTC 24 Sep 04 05:09:15 AM UTC 24 902752788 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3475641492 Sep 04 05:09:12 AM UTC 24 Sep 04 05:09:15 AM UTC 24 157799550 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2704621260 Sep 04 05:09:13 AM UTC 24 Sep 04 05:09:16 AM UTC 24 28301770 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.390815871 Sep 04 05:09:13 AM UTC 24 Sep 04 05:09:16 AM UTC 24 82589646 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.4136457003 Sep 04 05:09:12 AM UTC 24 Sep 04 05:09:16 AM UTC 24 391224804 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.605883224 Sep 04 05:09:12 AM UTC 24 Sep 04 05:09:17 AM UTC 24 254756967 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.887315637 Sep 04 05:09:15 AM UTC 24 Sep 04 05:09:17 AM UTC 24 12978624 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.3513432493 Sep 04 05:09:15 AM UTC 24 Sep 04 05:09:17 AM UTC 24 11056627 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.2534734656 Sep 04 05:09:14 AM UTC 24 Sep 04 05:09:18 AM UTC 24 734994100 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.3917691538 Sep 04 05:09:16 AM UTC 24 Sep 04 05:09:18 AM UTC 24 130496792 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3411348201 Sep 04 05:09:16 AM UTC 24 Sep 04 05:09:19 AM UTC 24 83176118 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.342932134 Sep 04 05:09:17 AM UTC 24 Sep 04 05:09:19 AM UTC 24 12069928 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.89846833 Sep 04 05:09:17 AM UTC 24 Sep 04 05:09:19 AM UTC 24 124058839 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3420712770 Sep 04 05:09:17 AM UTC 24 Sep 04 05:09:19 AM UTC 24 160765227 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.936342808 Sep 04 05:09:14 AM UTC 24 Sep 04 05:09:19 AM UTC 24 125410176 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2246361038 Sep 04 05:09:17 AM UTC 24 Sep 04 05:09:20 AM UTC 24 91991310 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1515503397 Sep 04 05:09:18 AM UTC 24 Sep 04 05:09:21 AM UTC 24 14053667 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3823077832 Sep 04 05:09:18 AM UTC 24 Sep 04 05:09:21 AM UTC 24 20965089 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.404892381 Sep 04 05:09:17 AM UTC 24 Sep 04 05:09:21 AM UTC 24 46205615 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3081495178 Sep 04 05:09:19 AM UTC 24 Sep 04 05:09:22 AM UTC 24 26367702 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.777206488 Sep 04 05:09:18 AM UTC 24 Sep 04 05:09:22 AM UTC 24 188102449 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2386563199 Sep 04 05:09:18 AM UTC 24 Sep 04 05:09:22 AM UTC 24 102637376 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2597392097 Sep 04 05:09:19 AM UTC 24 Sep 04 05:09:22 AM UTC 24 35612961 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4018255789 Sep 04 05:09:19 AM UTC 24 Sep 04 05:09:22 AM UTC 24 103696895 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.1240001428 Sep 04 05:09:21 AM UTC 24 Sep 04 05:09:23 AM UTC 24 24704628 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.270235429 Sep 04 05:09:21 AM UTC 24 Sep 04 05:09:23 AM UTC 24 43515729 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.757819754 Sep 04 05:09:21 AM UTC 24 Sep 04 05:09:24 AM UTC 24 92162447 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2114729399 Sep 04 05:09:21 AM UTC 24 Sep 04 05:09:24 AM UTC 24 255379141 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.41973179 Sep 04 05:09:22 AM UTC 24 Sep 04 05:09:25 AM UTC 24 90322743 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.490648187 Sep 04 05:09:22 AM UTC 24 Sep 04 05:09:25 AM UTC 24 25467283 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1321766887 Sep 04 05:09:23 AM UTC 24 Sep 04 05:09:25 AM UTC 24 23631514 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.3717437218 Sep 04 05:09:23 AM UTC 24 Sep 04 05:09:25 AM UTC 24 47889224 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.116004759 Sep 04 05:09:23 AM UTC 24 Sep 04 05:09:26 AM UTC 24 51250036 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1893261612 Sep 04 05:09:23 AM UTC 24 Sep 04 05:09:26 AM UTC 24 34519585 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3974428239 Sep 04 05:09:23 AM UTC 24 Sep 04 05:09:26 AM UTC 24 286876231 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.585622621 Sep 04 05:09:22 AM UTC 24 Sep 04 05:09:26 AM UTC 24 153176231 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.4219247418 Sep 04 05:09:23 AM UTC 24 Sep 04 05:09:27 AM UTC 24 103298715 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2856349152 Sep 04 05:09:24 AM UTC 24 Sep 04 05:09:27 AM UTC 24 13934370 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3986122760 Sep 04 05:09:24 AM UTC 24 Sep 04 05:09:27 AM UTC 24 20826464 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1541945834 Sep 04 05:09:26 AM UTC 24 Sep 04 05:09:28 AM UTC 24 32442706 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3629934874 Sep 04 05:09:26 AM UTC 24 Sep 04 05:09:28 AM UTC 24 60518116 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.2078842087 Sep 04 05:09:24 AM UTC 24 Sep 04 05:09:29 AM UTC 24 156293207 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3311020341 Sep 04 05:09:27 AM UTC 24 Sep 04 05:09:29 AM UTC 24 25599452 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.25278313 Sep 04 05:09:27 AM UTC 24 Sep 04 05:09:29 AM UTC 24 13777658 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3434925997 Sep 04 05:09:27 AM UTC 24 Sep 04 05:09:30 AM UTC 24 33616875 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.3429083385 Sep 04 05:09:27 AM UTC 24 Sep 04 05:09:30 AM UTC 24 31758905 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2933026790 Sep 04 05:09:27 AM UTC 24 Sep 04 05:09:30 AM UTC 24 142910353 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3574031094 Sep 04 05:09:28 AM UTC 24 Sep 04 05:09:30 AM UTC 24 22713775 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1055499869 Sep 04 05:09:28 AM UTC 24 Sep 04 05:09:30 AM UTC 24 43527658 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.728776775 Sep 04 05:09:27 AM UTC 24 Sep 04 05:09:30 AM UTC 24 69112857 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.2037600189 Sep 04 05:09:28 AM UTC 24 Sep 04 05:09:30 AM UTC 24 35675976 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3638780194 Sep 04 05:09:29 AM UTC 24 Sep 04 05:09:31 AM UTC 24 20656455 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.505993053 Sep 04 05:09:29 AM UTC 24 Sep 04 05:09:32 AM UTC 24 30351047 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3003274282 Sep 04 05:09:30 AM UTC 24 Sep 04 05:09:33 AM UTC 24 24716250 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1518215821 Sep 04 05:09:30 AM UTC 24 Sep 04 05:09:33 AM UTC 24 16263610 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.884203051 Sep 04 05:09:30 AM UTC 24 Sep 04 05:09:33 AM UTC 24 53889623 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.4196795072 Sep 04 05:09:31 AM UTC 24 Sep 04 05:09:33 AM UTC 24 82996734 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.4153171091 Sep 04 05:09:31 AM UTC 24 Sep 04 05:09:33 AM UTC 24 54095316 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.2284218396 Sep 04 05:09:30 AM UTC 24 Sep 04 05:09:33 AM UTC 24 13373564 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.982634380 Sep 04 05:09:32 AM UTC 24 Sep 04 05:09:35 AM UTC 24 18147834 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3217767802 Sep 04 05:09:32 AM UTC 24 Sep 04 05:09:35 AM UTC 24 83679560 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3158919373 Sep 04 05:09:32 AM UTC 24 Sep 04 05:09:35 AM UTC 24 57907252 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.3483558937 Sep 04 05:09:32 AM UTC 24 Sep 04 05:09:35 AM UTC 24 152688113 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.419820384 Sep 04 05:09:33 AM UTC 24 Sep 04 05:09:35 AM UTC 24 16292211 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.4094627200 Sep 04 05:09:33 AM UTC 24 Sep 04 05:09:35 AM UTC 24 14300008 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.1705411023 Sep 04 05:09:33 AM UTC 24 Sep 04 05:09:35 AM UTC 24 90301828 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3109271930 Sep 04 05:09:34 AM UTC 24 Sep 04 05:09:36 AM UTC 24 33295254 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.303572286 Sep 04 05:09:34 AM UTC 24 Sep 04 05:09:37 AM UTC 24 57311367 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2241940502 Sep 04 05:09:34 AM UTC 24 Sep 04 05:09:37 AM UTC 24 19506939 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2916622024 Sep 04 05:09:34 AM UTC 24 Sep 04 05:09:37 AM UTC 24 37676617 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.876742171 Sep 04 05:09:34 AM UTC 24 Sep 04 05:09:37 AM UTC 24 21141911 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1623685030 Sep 04 05:09:34 AM UTC 24 Sep 04 05:09:37 AM UTC 24 34590277 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2499964684 Sep 04 05:09:35 AM UTC 24 Sep 04 05:09:38 AM UTC 24 90698607 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.2475403065 Sep 04 05:09:36 AM UTC 24 Sep 04 05:09:38 AM UTC 24 12885577 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1207688389 Sep 04 05:09:36 AM UTC 24 Sep 04 05:09:38 AM UTC 24 12740740 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3800314512 Sep 04 05:09:36 AM UTC 24 Sep 04 05:09:38 AM UTC 24 39538583 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.372645256 Sep 04 05:09:36 AM UTC 24 Sep 04 05:09:38 AM UTC 24 75964450 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.3902444597 Sep 04 05:09:37 AM UTC 24 Sep 04 05:09:39 AM UTC 24 13645157 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_alert.3942416577
Short name T10
Test name
Test status
Simulation time 47791801 ps
CPU time 1.9 seconds
Started Sep 04 04:59:33 AM UTC 24
Finished Sep 04 04:59:36 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942416577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.3942416577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_sec_cm.3725239097
Short name T16
Test name
Test status
Simulation time 1105966749 ps
CPU time 7.27 seconds
Started Sep 04 04:59:37 AM UTC 24
Finished Sep 04 04:59:45 AM UTC 24
Peak memory 260368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725239097 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3725239097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_genbits.52491273
Short name T26
Test name
Test status
Simulation time 77891991 ps
CPU time 1.67 seconds
Started Sep 04 04:59:40 AM UTC 24
Finished Sep 04 04:59:43 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52491273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.edn_genbits.52491273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.670624143
Short name T34
Test name
Test status
Simulation time 4976776545 ps
CPU time 32.51 seconds
Started Sep 04 04:59:31 AM UTC 24
Finished Sep 04 05:00:05 AM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=670624143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_w
ith_rand_reset.670624143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_genbits.1912320496
Short name T43
Test name
Test status
Simulation time 74384785 ps
CPU time 3.1 seconds
Started Sep 04 04:59:54 AM UTC 24
Finished Sep 04 04:59:58 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912320496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1912320496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_stress_all.3999504624
Short name T5
Test name
Test status
Simulation time 467669132 ps
CPU time 4.66 seconds
Started Sep 04 04:59:31 AM UTC 24
Finished Sep 04 04:59:36 AM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999504624 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3999504624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_stress_all.2819763833
Short name T102
Test name
Test status
Simulation time 870862498 ps
CPU time 7.6 seconds
Started Sep 04 04:59:54 AM UTC 24
Finished Sep 04 05:00:03 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819763833 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2819763833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2688163244
Short name T22
Test name
Test status
Simulation time 42586322 ps
CPU time 1.74 seconds
Started Sep 04 05:00:15 AM UTC 24
Finished Sep 04 05:00:18 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688163244 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2688163244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_alert.495740599
Short name T46
Test name
Test status
Simulation time 43128610 ps
CPU time 1.5 seconds
Started Sep 04 05:00:14 AM UTC 24
Finished Sep 04 05:00:16 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495740599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.edn_alert.495740599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_alert.2094035743
Short name T56
Test name
Test status
Simulation time 99973613 ps
CPU time 1.53 seconds
Started Sep 04 05:00:02 AM UTC 24
Finished Sep 04 05:00:07 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094035743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.2094035743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.1924030083
Short name T152
Test name
Test status
Simulation time 24746243 ps
CPU time 1.51 seconds
Started Sep 04 05:01:19 AM UTC 24
Finished Sep 04 05:01:21 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924030083 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.1924030083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3665743326
Short name T299
Test name
Test status
Simulation time 101481336 ps
CPU time 3.85 seconds
Started Sep 04 05:09:01 AM UTC 24
Finished Sep 04 05:09:06 AM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665743326 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3665743326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_alert.3206154961
Short name T55
Test name
Test status
Simulation time 88619420 ps
CPU time 1.62 seconds
Started Sep 04 04:59:56 AM UTC 24
Finished Sep 04 04:59:59 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206154961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.3206154961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.2129937172
Short name T204
Test name
Test status
Simulation time 3440096941 ps
CPU time 105.04 seconds
Started Sep 04 05:00:14 AM UTC 24
Finished Sep 04 05:02:01 AM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2129937172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_
with_rand_reset.2129937172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.166856259
Short name T122
Test name
Test status
Simulation time 30284260 ps
CPU time 1.71 seconds
Started Sep 04 05:03:34 AM UTC 24
Finished Sep 04 05:03:37 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166856259 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.166856259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_err.1445107853
Short name T166
Test name
Test status
Simulation time 19637928 ps
CPU time 1.57 seconds
Started Sep 04 05:01:19 AM UTC 24
Finished Sep 04 05:01:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445107853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.1445107853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_disable.3249093719
Short name T50
Test name
Test status
Simulation time 14022950 ps
CPU time 1.28 seconds
Started Sep 04 05:02:19 AM UTC 24
Finished Sep 04 05:02:21 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249093719 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3249093719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_disable.731268144
Short name T72
Test name
Test status
Simulation time 23786654 ps
CPU time 1.34 seconds
Started Sep 04 05:00:43 AM UTC 24
Finished Sep 04 05:00:46 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731268144 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.731268144
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_disable.1454524548
Short name T76
Test name
Test status
Simulation time 17349486 ps
CPU time 1.26 seconds
Started Sep 04 05:01:04 AM UTC 24
Finished Sep 04 05:01:06 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454524548 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1454524548
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.4192604723
Short name T238
Test name
Test status
Simulation time 59187225 ps
CPU time 2.18 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:44 AM UTC 24
Peak memory 217436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192604723 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4192604723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_stress_all.3220231868
Short name T304
Test name
Test status
Simulation time 254823014 ps
CPU time 5.29 seconds
Started Sep 04 05:01:01 AM UTC 24
Finished Sep 04 05:01:07 AM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220231868 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3220231868
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_disable.3138463770
Short name T37
Test name
Test status
Simulation time 18510792 ps
CPU time 1.35 seconds
Started Sep 04 04:59:45 AM UTC 24
Finished Sep 04 04:59:47 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138463770 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3138463770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_alert.4184406438
Short name T115
Test name
Test status
Simulation time 168069953 ps
CPU time 1.98 seconds
Started Sep 04 05:00:50 AM UTC 24
Finished Sep 04 05:00:53 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184406438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.4184406438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/56.edn_alert.2814377099
Short name T302
Test name
Test status
Simulation time 63642760 ps
CPU time 1.89 seconds
Started Sep 04 05:06:07 AM UTC 24
Finished Sep 04 05:06:10 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814377099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.2814377099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_genbits.1104070619
Short name T254
Test name
Test status
Simulation time 60424628 ps
CPU time 3.42 seconds
Started Sep 04 05:05:08 AM UTC 24
Finished Sep 04 05:05:13 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104070619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1104070619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_alert.3392686456
Short name T147
Test name
Test status
Simulation time 159921008 ps
CPU time 1.5 seconds
Started Sep 04 05:01:39 AM UTC 24
Finished Sep 04 05:01:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392686456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.3392686456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.195634690
Short name T11
Test name
Test status
Simulation time 100285054 ps
CPU time 1.44 seconds
Started Sep 04 04:59:36 AM UTC 24
Finished Sep 04 04:59:39 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195634690 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.195634690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_intr.972672410
Short name T28
Test name
Test status
Simulation time 35673100 ps
CPU time 1.29 seconds
Started Sep 04 05:00:24 AM UTC 24
Finished Sep 04 05:00:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972672410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.972672410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/68.edn_genbits.3568580640
Short name T324
Test name
Test status
Simulation time 51522110 ps
CPU time 2.8 seconds
Started Sep 04 05:06:25 AM UTC 24
Finished Sep 04 05:06:28 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568580640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3568580640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/160.edn_alert.3286698504
Short name T808
Test name
Test status
Simulation time 307717068 ps
CPU time 2.05 seconds
Started Sep 04 05:07:42 AM UTC 24
Finished Sep 04 05:07:45 AM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286698504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.3286698504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/95.edn_alert.610008307
Short name T195
Test name
Test status
Simulation time 154154492 ps
CPU time 1.7 seconds
Started Sep 04 05:06:57 AM UTC 24
Finished Sep 04 05:07:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610008307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 95.edn_alert.610008307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_alert.3586954290
Short name T86
Test name
Test status
Simulation time 94201520 ps
CPU time 1.82 seconds
Started Sep 04 05:01:31 AM UTC 24
Finished Sep 04 05:01:34 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586954290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.3586954290
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_intr.354675660
Short name T32
Test name
Test status
Simulation time 19932605 ps
CPU time 1.63 seconds
Started Sep 04 05:01:15 AM UTC 24
Finished Sep 04 05:01:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354675660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.354675660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.2181564509
Short name T128
Test name
Test status
Simulation time 82992791 ps
CPU time 1.71 seconds
Started Sep 04 05:00:44 AM UTC 24
Finished Sep 04 05:00:47 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181564509 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.2181564509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/110.edn_alert.298004940
Short name T706
Test name
Test status
Simulation time 66958661 ps
CPU time 1.24 seconds
Started Sep 04 05:07:09 AM UTC 24
Finished Sep 04 05:07:12 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298004940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 110.edn_alert.298004940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/115.edn_alert.2701219909
Short name T137
Test name
Test status
Simulation time 108999152 ps
CPU time 1.95 seconds
Started Sep 04 05:07:13 AM UTC 24
Finished Sep 04 05:07:16 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701219909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.2701219909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/125.edn_alert.3890880454
Short name T132
Test name
Test status
Simulation time 68706373 ps
CPU time 1.71 seconds
Started Sep 04 05:07:19 AM UTC 24
Finished Sep 04 05:07:22 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890880454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.3890880454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_err.3748963130
Short name T201
Test name
Test status
Simulation time 23946870 ps
CPU time 1.57 seconds
Started Sep 04 05:00:57 AM UTC 24
Finished Sep 04 05:01:00 AM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748963130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.3748963130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/135.edn_alert.1249737326
Short name T760
Test name
Test status
Simulation time 55272967 ps
CPU time 1.5 seconds
Started Sep 04 05:07:26 AM UTC 24
Finished Sep 04 05:07:29 AM UTC 24
Peak memory 226284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249737326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.1249737326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_alert.4214790081
Short name T113
Test name
Test status
Simulation time 22401422 ps
CPU time 1.76 seconds
Started Sep 04 05:01:09 AM UTC 24
Finished Sep 04 05:01:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214790081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.4214790081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/157.edn_alert.2159679476
Short name T802
Test name
Test status
Simulation time 22701686 ps
CPU time 1.72 seconds
Started Sep 04 05:07:40 AM UTC 24
Finished Sep 04 05:07:43 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159679476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.2159679476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_disable.1227995395
Short name T181
Test name
Test status
Simulation time 10267373 ps
CPU time 1.25 seconds
Started Sep 04 05:01:43 AM UTC 24
Finished Sep 04 05:01:45 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227995395 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1227995395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/194.edn_alert.100660671
Short name T866
Test name
Test status
Simulation time 38727438 ps
CPU time 1.64 seconds
Started Sep 04 05:08:04 AM UTC 24
Finished Sep 04 05:08:06 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100660671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 194.edn_alert.100660671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.3613167194
Short name T38
Test name
Test status
Simulation time 124115016 ps
CPU time 1.6 seconds
Started Sep 04 04:59:51 AM UTC 24
Finished Sep 04 04:59:53 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613167194 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.3613167194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_disable.2023759612
Short name T91
Test name
Test status
Simulation time 11969666 ps
CPU time 1.39 seconds
Started Sep 04 05:02:05 AM UTC 24
Finished Sep 04 05:02:07 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023759612 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2023759612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_err.2557544352
Short name T186
Test name
Test status
Simulation time 33583965 ps
CPU time 1.51 seconds
Started Sep 04 05:03:16 AM UTC 24
Finished Sep 04 05:03:19 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557544352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.2557544352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.1444275019
Short name T497
Test name
Test status
Simulation time 45322265 ps
CPU time 1.65 seconds
Started Sep 04 05:04:00 AM UTC 24
Finished Sep 04 05:04:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444275019 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.1444275019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_disable.2235055499
Short name T212
Test name
Test status
Simulation time 12035201 ps
CPU time 1.37 seconds
Started Sep 04 05:05:53 AM UTC 24
Finished Sep 04 05:05:56 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235055499 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2235055499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_alert_test.2552521764
Short name T350
Test name
Test status
Simulation time 39025462 ps
CPU time 1.55 seconds
Started Sep 04 05:00:21 AM UTC 24
Finished Sep 04 05:00:23 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552521764 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2552521764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_genbits.3830654109
Short name T339
Test name
Test status
Simulation time 59258541 ps
CPU time 1.8 seconds
Started Sep 04 05:05:31 AM UTC 24
Finished Sep 04 05:05:34 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830654109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3830654109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_stress_all.304376079
Short name T310
Test name
Test status
Simulation time 258632448 ps
CPU time 4.7 seconds
Started Sep 04 05:01:28 AM UTC 24
Finished Sep 04 05:01:33 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304376079 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.304376079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/104.edn_genbits.1643121339
Short name T335
Test name
Test status
Simulation time 113312900 ps
CPU time 3.27 seconds
Started Sep 04 05:07:05 AM UTC 24
Finished Sep 04 05:07:09 AM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643121339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1643121339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.1444330530
Short name T278
Test name
Test status
Simulation time 22796502 ps
CPU time 1.53 seconds
Started Sep 04 05:01:25 AM UTC 24
Finished Sep 04 05:01:28 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444330530 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.1444330530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/198.edn_genbits.2970874093
Short name T322
Test name
Test status
Simulation time 90627188 ps
CPU time 1.42 seconds
Started Sep 04 05:08:06 AM UTC 24
Finished Sep 04 05:08:08 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970874093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2970874093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_genbits.87164221
Short name T65
Test name
Test status
Simulation time 65910923 ps
CPU time 1.65 seconds
Started Sep 04 04:59:47 AM UTC 24
Finished Sep 04 04:59:50 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87164221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.edn_genbits.87164221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/62.edn_err.1786608358
Short name T94
Test name
Test status
Simulation time 35012146 ps
CPU time 1.81 seconds
Started Sep 04 05:06:18 AM UTC 24
Finished Sep 04 05:06:20 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786608358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.1786608358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/151.edn_genbits.90105833
Short name T331
Test name
Test status
Simulation time 60717009 ps
CPU time 1.8 seconds
Started Sep 04 05:07:36 AM UTC 24
Finished Sep 04 05:07:39 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90105833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 151.edn_genbits.90105833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/163.edn_genbits.89136401
Short name T326
Test name
Test status
Simulation time 44753286 ps
CPU time 1.63 seconds
Started Sep 04 05:07:43 AM UTC 24
Finished Sep 04 05:07:46 AM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89136401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 163.edn_genbits.89136401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1199132022
Short name T272
Test name
Test status
Simulation time 23923344 ps
CPU time 1.33 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199132022 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1199132022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.2652505334
Short name T265
Test name
Test status
Simulation time 92688159 ps
CPU time 1.68 seconds
Started Sep 04 05:08:46 AM UTC 24
Finished Sep 04 05:08:48 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652505334 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2652505334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/109.edn_genbits.1540219132
Short name T707
Test name
Test status
Simulation time 103760885 ps
CPU time 2.71 seconds
Started Sep 04 05:07:08 AM UTC 24
Finished Sep 04 05:07:12 AM UTC 24
Peak memory 228824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540219132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1540219132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_stress_all.3126675124
Short name T101
Test name
Test status
Simulation time 487870357 ps
CPU time 6.86 seconds
Started Sep 04 05:00:40 AM UTC 24
Finished Sep 04 05:00:48 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126675124 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3126675124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_stress_all.1243540919
Short name T284
Test name
Test status
Simulation time 763186364 ps
CPU time 4.97 seconds
Started Sep 04 05:00:47 AM UTC 24
Finished Sep 04 05:00:54 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243540919 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1243540919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/143.edn_genbits.1950745490
Short name T774
Test name
Test status
Simulation time 65053753 ps
CPU time 1.7 seconds
Started Sep 04 05:07:31 AM UTC 24
Finished Sep 04 05:07:34 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950745490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1950745490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/144.edn_genbits.3129445657
Short name T333
Test name
Test status
Simulation time 54156976 ps
CPU time 1.87 seconds
Started Sep 04 05:07:31 AM UTC 24
Finished Sep 04 05:07:34 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129445657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3129445657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/155.edn_alert.959654164
Short name T286
Test name
Test status
Simulation time 94482087 ps
CPU time 1.71 seconds
Started Sep 04 05:07:38 AM UTC 24
Finished Sep 04 05:07:41 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959654164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 155.edn_alert.959654164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_genbits.3751199575
Short name T79
Test name
Test status
Simulation time 30423040 ps
CPU time 2.02 seconds
Started Sep 04 05:01:21 AM UTC 24
Finished Sep 04 05:01:24 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751199575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3751199575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/195.edn_genbits.3167310762
Short name T314
Test name
Test status
Simulation time 55852343 ps
CPU time 2.02 seconds
Started Sep 04 05:08:04 AM UTC 24
Finished Sep 04 05:08:07 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167310762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3167310762
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_intr.1862989969
Short name T33
Test name
Test status
Simulation time 32212707 ps
CPU time 1.3 seconds
Started Sep 04 05:01:38 AM UTC 24
Finished Sep 04 05:01:41 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862989969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.1862989969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_intr.797294683
Short name T30
Test name
Test status
Simulation time 28586226 ps
CPU time 1.26 seconds
Started Sep 04 05:01:22 AM UTC 24
Finished Sep 04 05:01:24 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797294683 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.797294683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_err.435795153
Short name T149
Test name
Test status
Simulation time 27377006 ps
CPU time 2.02 seconds
Started Sep 04 05:00:42 AM UTC 24
Finished Sep 04 05:00:45 AM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435795153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 11.edn_err.435795153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/193.edn_genbits.3142357016
Short name T861
Test name
Test status
Simulation time 112448650 ps
CPU time 2.11 seconds
Started Sep 04 05:08:01 AM UTC 24
Finished Sep 04 05:08:05 AM UTC 24
Peak memory 231788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142357016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3142357016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.2082048171
Short name T974
Test name
Test status
Simulation time 983017937 ps
CPU time 5.05 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:47 AM UTC 24
Peak memory 217452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082048171 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2082048171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.2723320385
Short name T262
Test name
Test status
Simulation time 20560102 ps
CPU time 1.4 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723320385 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2723320385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3473233385
Short name T971
Test name
Test status
Simulation time 82524289 ps
CPU time 2.17 seconds
Started Sep 04 05:08:42 AM UTC 24
Finished Sep 04 05:08:45 AM UTC 24
Peak memory 227352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3473233385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3473233385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.1382457181
Short name T969
Test name
Test status
Simulation time 27238919 ps
CPU time 1.24 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:43 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382457181 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1382457181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.3919136609
Short name T263
Test name
Test status
Simulation time 177839421 ps
CPU time 2.48 seconds
Started Sep 04 05:08:42 AM UTC 24
Finished Sep 04 05:08:46 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919136609 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.3919136609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.1054675934
Short name T970
Test name
Test status
Simulation time 34334578 ps
CPU time 3.15 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:45 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054675934 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1054675934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.812101390
Short name T249
Test name
Test status
Simulation time 294772999 ps
CPU time 2.27 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:44 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812101390 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.812101390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.3111492603
Short name T978
Test name
Test status
Simulation time 94977320 ps
CPU time 3.94 seconds
Started Sep 04 05:08:45 AM UTC 24
Finished Sep 04 05:08:49 AM UTC 24
Peak memory 217460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111492603 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3111492603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.779843968
Short name T973
Test name
Test status
Simulation time 63144611 ps
CPU time 1.29 seconds
Started Sep 04 05:08:44 AM UTC 24
Finished Sep 04 05:08:47 AM UTC 24
Peak memory 215444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779843968 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.779843968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4052671956
Short name T977
Test name
Test status
Simulation time 128138862 ps
CPU time 2.69 seconds
Started Sep 04 05:08:46 AM UTC 24
Finished Sep 04 05:08:49 AM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4052671956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4052671956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.321444542
Short name T273
Test name
Test status
Simulation time 14284463 ps
CPU time 1.39 seconds
Started Sep 04 05:08:45 AM UTC 24
Finished Sep 04 05:08:47 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321444542 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.321444542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1988847430
Short name T972
Test name
Test status
Simulation time 101012330 ps
CPU time 1.14 seconds
Started Sep 04 05:08:44 AM UTC 24
Finished Sep 04 05:08:47 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988847430 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1988847430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.3464750628
Short name T264
Test name
Test status
Simulation time 25489481 ps
CPU time 1.6 seconds
Started Sep 04 05:08:46 AM UTC 24
Finished Sep 04 05:08:48 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464750628 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.3464750628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.2010128846
Short name T979
Test name
Test status
Simulation time 1951391214 ps
CPU time 7.26 seconds
Started Sep 04 05:08:42 AM UTC 24
Finished Sep 04 05:08:51 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010128846 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2010128846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.4113595372
Short name T281
Test name
Test status
Simulation time 223992528 ps
CPU time 2.23 seconds
Started Sep 04 05:08:43 AM UTC 24
Finished Sep 04 05:08:47 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113595372 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4113595372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.184231545
Short name T1023
Test name
Test status
Simulation time 45798258 ps
CPU time 1.35 seconds
Started Sep 04 05:09:10 AM UTC 24
Finished Sep 04 05:09:12 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=184231545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.184231545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.515449687
Short name T1020
Test name
Test status
Simulation time 22961260 ps
CPU time 1.37 seconds
Started Sep 04 05:09:09 AM UTC 24
Finished Sep 04 05:09:11 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515449687 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.515449687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.315668063
Short name T1019
Test name
Test status
Simulation time 12518574 ps
CPU time 1.3 seconds
Started Sep 04 05:09:08 AM UTC 24
Finished Sep 04 05:09:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315668063 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.315668063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3208401677
Short name T1022
Test name
Test status
Simulation time 24250748 ps
CPU time 1.68 seconds
Started Sep 04 05:09:09 AM UTC 24
Finished Sep 04 05:09:11 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208401677 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.3208401677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1606546803
Short name T1025
Test name
Test status
Simulation time 41221199 ps
CPU time 3.95 seconds
Started Sep 04 05:09:07 AM UTC 24
Finished Sep 04 05:09:12 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606546803 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1606546803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.696978373
Short name T1027
Test name
Test status
Simulation time 173401499 ps
CPU time 4.64 seconds
Started Sep 04 05:09:07 AM UTC 24
Finished Sep 04 05:09:13 AM UTC 24
Peak memory 227736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696978373 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.696978373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3475641492
Short name T1032
Test name
Test status
Simulation time 157799550 ps
CPU time 2.3 seconds
Started Sep 04 05:09:12 AM UTC 24
Finished Sep 04 05:09:15 AM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3475641492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3475641492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1694802830
Short name T1026
Test name
Test status
Simulation time 35257979 ps
CPU time 1.18 seconds
Started Sep 04 05:09:11 AM UTC 24
Finished Sep 04 05:09:13 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694802830 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1694802830
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.727791633
Short name T1024
Test name
Test status
Simulation time 13361270 ps
CPU time 1.27 seconds
Started Sep 04 05:09:10 AM UTC 24
Finished Sep 04 05:09:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727791633 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.727791633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.41517709
Short name T1029
Test name
Test status
Simulation time 115863691 ps
CPU time 1.67 seconds
Started Sep 04 05:09:11 AM UTC 24
Finished Sep 04 05:09:14 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41517709 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.41517709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2919436287
Short name T1031
Test name
Test status
Simulation time 902752788 ps
CPU time 4.37 seconds
Started Sep 04 05:09:10 AM UTC 24
Finished Sep 04 05:09:15 AM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919436287 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2919436287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1425751187
Short name T1028
Test name
Test status
Simulation time 55850110 ps
CPU time 2.62 seconds
Started Sep 04 05:09:10 AM UTC 24
Finished Sep 04 05:09:13 AM UTC 24
Peak memory 217512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425751187 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1425751187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.390815871
Short name T1034
Test name
Test status
Simulation time 82589646 ps
CPU time 1.6 seconds
Started Sep 04 05:09:13 AM UTC 24
Finished Sep 04 05:09:16 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=390815871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.390815871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.701103093
Short name T1000
Test name
Test status
Simulation time 69513678 ps
CPU time 1.27 seconds
Started Sep 04 05:09:13 AM UTC 24
Finished Sep 04 05:09:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701103093 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.701103093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.438967509
Short name T1030
Test name
Test status
Simulation time 94864626 ps
CPU time 1.23 seconds
Started Sep 04 05:09:12 AM UTC 24
Finished Sep 04 05:09:14 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438967509 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.438967509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2704621260
Short name T1033
Test name
Test status
Simulation time 28301770 ps
CPU time 1.63 seconds
Started Sep 04 05:09:13 AM UTC 24
Finished Sep 04 05:09:16 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704621260 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.2704621260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.605883224
Short name T1036
Test name
Test status
Simulation time 254756967 ps
CPU time 3.65 seconds
Started Sep 04 05:09:12 AM UTC 24
Finished Sep 04 05:09:17 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605883224 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.605883224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.4136457003
Short name T1035
Test name
Test status
Simulation time 391224804 ps
CPU time 3.02 seconds
Started Sep 04 05:09:12 AM UTC 24
Finished Sep 04 05:09:16 AM UTC 24
Peak memory 217488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136457003 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4136457003
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3411348201
Short name T1041
Test name
Test status
Simulation time 83176118 ps
CPU time 2.09 seconds
Started Sep 04 05:09:16 AM UTC 24
Finished Sep 04 05:09:19 AM UTC 24
Peak memory 228056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3411348201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3411348201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.3513432493
Short name T1038
Test name
Test status
Simulation time 11056627 ps
CPU time 1.27 seconds
Started Sep 04 05:09:15 AM UTC 24
Finished Sep 04 05:09:17 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513432493 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3513432493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.887315637
Short name T1037
Test name
Test status
Simulation time 12978624 ps
CPU time 1.3 seconds
Started Sep 04 05:09:15 AM UTC 24
Finished Sep 04 05:09:17 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887315637 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.887315637
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.3917691538
Short name T1040
Test name
Test status
Simulation time 130496792 ps
CPU time 1.49 seconds
Started Sep 04 05:09:16 AM UTC 24
Finished Sep 04 05:09:18 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917691538 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.3917691538
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.936342808
Short name T1045
Test name
Test status
Simulation time 125410176 ps
CPU time 3.92 seconds
Started Sep 04 05:09:14 AM UTC 24
Finished Sep 04 05:09:19 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936342808 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.936342808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.2534734656
Short name T1039
Test name
Test status
Simulation time 734994100 ps
CPU time 2.29 seconds
Started Sep 04 05:09:14 AM UTC 24
Finished Sep 04 05:09:18 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534734656 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2534734656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3823077832
Short name T1048
Test name
Test status
Simulation time 20965089 ps
CPU time 1.61 seconds
Started Sep 04 05:09:18 AM UTC 24
Finished Sep 04 05:09:21 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3823077832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3823077832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.89846833
Short name T1043
Test name
Test status
Simulation time 124058839 ps
CPU time 1.23 seconds
Started Sep 04 05:09:17 AM UTC 24
Finished Sep 04 05:09:19 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89846833 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.89846833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.342932134
Short name T1042
Test name
Test status
Simulation time 12069928 ps
CPU time 1.24 seconds
Started Sep 04 05:09:17 AM UTC 24
Finished Sep 04 05:09:19 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342932134 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.342932134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3420712770
Short name T1044
Test name
Test status
Simulation time 160765227 ps
CPU time 1.38 seconds
Started Sep 04 05:09:17 AM UTC 24
Finished Sep 04 05:09:19 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420712770 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.3420712770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.404892381
Short name T1049
Test name
Test status
Simulation time 46205615 ps
CPU time 3.34 seconds
Started Sep 04 05:09:17 AM UTC 24
Finished Sep 04 05:09:21 AM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404892381 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.404892381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2246361038
Short name T1046
Test name
Test status
Simulation time 91991310 ps
CPU time 2.36 seconds
Started Sep 04 05:09:17 AM UTC 24
Finished Sep 04 05:09:20 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246361038 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2246361038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4018255789
Short name T1054
Test name
Test status
Simulation time 103696895 ps
CPU time 2 seconds
Started Sep 04 05:09:19 AM UTC 24
Finished Sep 04 05:09:22 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4018255789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4018255789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3081495178
Short name T1050
Test name
Test status
Simulation time 26367702 ps
CPU time 1.36 seconds
Started Sep 04 05:09:19 AM UTC 24
Finished Sep 04 05:09:22 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081495178 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3081495178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1515503397
Short name T1047
Test name
Test status
Simulation time 14053667 ps
CPU time 1.34 seconds
Started Sep 04 05:09:18 AM UTC 24
Finished Sep 04 05:09:21 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515503397 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1515503397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2597392097
Short name T1053
Test name
Test status
Simulation time 35612961 ps
CPU time 1.89 seconds
Started Sep 04 05:09:19 AM UTC 24
Finished Sep 04 05:09:22 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597392097 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.2597392097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2386563199
Short name T1052
Test name
Test status
Simulation time 102637376 ps
CPU time 2.7 seconds
Started Sep 04 05:09:18 AM UTC 24
Finished Sep 04 05:09:22 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386563199 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2386563199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.777206488
Short name T1051
Test name
Test status
Simulation time 188102449 ps
CPU time 2.55 seconds
Started Sep 04 05:09:18 AM UTC 24
Finished Sep 04 05:09:22 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777206488 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.777206488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.490648187
Short name T1060
Test name
Test status
Simulation time 25467283 ps
CPU time 1.87 seconds
Started Sep 04 05:09:22 AM UTC 24
Finished Sep 04 05:09:25 AM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=490648187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.490648187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.270235429
Short name T1056
Test name
Test status
Simulation time 43515729 ps
CPU time 1.3 seconds
Started Sep 04 05:09:21 AM UTC 24
Finished Sep 04 05:09:23 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270235429 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.270235429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.1240001428
Short name T1055
Test name
Test status
Simulation time 24704628 ps
CPU time 1.09 seconds
Started Sep 04 05:09:21 AM UTC 24
Finished Sep 04 05:09:23 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240001428 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1240001428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.41973179
Short name T1059
Test name
Test status
Simulation time 90322743 ps
CPU time 1.91 seconds
Started Sep 04 05:09:22 AM UTC 24
Finished Sep 04 05:09:25 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41973179 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.41973179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.757819754
Short name T1057
Test name
Test status
Simulation time 92162447 ps
CPU time 2.21 seconds
Started Sep 04 05:09:21 AM UTC 24
Finished Sep 04 05:09:24 AM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757819754 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.757819754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2114729399
Short name T1058
Test name
Test status
Simulation time 255379141 ps
CPU time 2.3 seconds
Started Sep 04 05:09:21 AM UTC 24
Finished Sep 04 05:09:24 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114729399 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2114729399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.116004759
Short name T1063
Test name
Test status
Simulation time 51250036 ps
CPU time 1.71 seconds
Started Sep 04 05:09:23 AM UTC 24
Finished Sep 04 05:09:26 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=116004759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.116004759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.3717437218
Short name T1062
Test name
Test status
Simulation time 47889224 ps
CPU time 1.27 seconds
Started Sep 04 05:09:23 AM UTC 24
Finished Sep 04 05:09:25 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717437218 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3717437218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1321766887
Short name T1061
Test name
Test status
Simulation time 23631514 ps
CPU time 1.29 seconds
Started Sep 04 05:09:23 AM UTC 24
Finished Sep 04 05:09:25 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321766887 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1321766887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1893261612
Short name T1064
Test name
Test status
Simulation time 34519585 ps
CPU time 1.83 seconds
Started Sep 04 05:09:23 AM UTC 24
Finished Sep 04 05:09:26 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893261612 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.1893261612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.585622621
Short name T1066
Test name
Test status
Simulation time 153176231 ps
CPU time 3.37 seconds
Started Sep 04 05:09:22 AM UTC 24
Finished Sep 04 05:09:26 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585622621 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.585622621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3974428239
Short name T1065
Test name
Test status
Simulation time 286876231 ps
CPU time 2.11 seconds
Started Sep 04 05:09:23 AM UTC 24
Finished Sep 04 05:09:26 AM UTC 24
Peak memory 217512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974428239 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3974428239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3629934874
Short name T1071
Test name
Test status
Simulation time 60518116 ps
CPU time 1.63 seconds
Started Sep 04 05:09:26 AM UTC 24
Finished Sep 04 05:09:28 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3629934874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3629934874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3986122760
Short name T1069
Test name
Test status
Simulation time 20826464 ps
CPU time 1.29 seconds
Started Sep 04 05:09:24 AM UTC 24
Finished Sep 04 05:09:27 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986122760 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3986122760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2856349152
Short name T1068
Test name
Test status
Simulation time 13934370 ps
CPU time 1.3 seconds
Started Sep 04 05:09:24 AM UTC 24
Finished Sep 04 05:09:27 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856349152 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2856349152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1541945834
Short name T1070
Test name
Test status
Simulation time 32442706 ps
CPU time 1.62 seconds
Started Sep 04 05:09:26 AM UTC 24
Finished Sep 04 05:09:28 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541945834 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1541945834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.4219247418
Short name T1067
Test name
Test status
Simulation time 103298715 ps
CPU time 2.33 seconds
Started Sep 04 05:09:23 AM UTC 24
Finished Sep 04 05:09:27 AM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219247418 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4219247418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.2078842087
Short name T1072
Test name
Test status
Simulation time 156293207 ps
CPU time 3.51 seconds
Started Sep 04 05:09:24 AM UTC 24
Finished Sep 04 05:09:29 AM UTC 24
Peak memory 228008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078842087 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2078842087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3434925997
Short name T1075
Test name
Test status
Simulation time 33616875 ps
CPU time 1.91 seconds
Started Sep 04 05:09:27 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3434925997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3434925997
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3311020341
Short name T1073
Test name
Test status
Simulation time 25599452 ps
CPU time 1.29 seconds
Started Sep 04 05:09:27 AM UTC 24
Finished Sep 04 05:09:29 AM UTC 24
Peak memory 215132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311020341 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3311020341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.25278313
Short name T1074
Test name
Test status
Simulation time 13777658 ps
CPU time 1.35 seconds
Started Sep 04 05:09:27 AM UTC 24
Finished Sep 04 05:09:29 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25278313 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.25278313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.3429083385
Short name T1076
Test name
Test status
Simulation time 31758905 ps
CPU time 1.93 seconds
Started Sep 04 05:09:27 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429083385 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.3429083385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2933026790
Short name T1077
Test name
Test status
Simulation time 142910353 ps
CPU time 2.29 seconds
Started Sep 04 05:09:27 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933026790 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2933026790
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.728776775
Short name T1080
Test name
Test status
Simulation time 69112857 ps
CPU time 2.68 seconds
Started Sep 04 05:09:27 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 217700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728776775 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.728776775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.2867453854
Short name T980
Test name
Test status
Simulation time 38124447 ps
CPU time 1.78 seconds
Started Sep 04 05:08:48 AM UTC 24
Finished Sep 04 05:08:51 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867453854 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2867453854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.708916267
Short name T991
Test name
Test status
Simulation time 706306785 ps
CPU time 7.17 seconds
Started Sep 04 05:08:48 AM UTC 24
Finished Sep 04 05:08:56 AM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708916267 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.708916267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.3865175165
Short name T266
Test name
Test status
Simulation time 32216657 ps
CPU time 1.25 seconds
Started Sep 04 05:08:47 AM UTC 24
Finished Sep 04 05:08:49 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865175165 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3865175165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1366020970
Short name T981
Test name
Test status
Simulation time 57239335 ps
CPU time 1.58 seconds
Started Sep 04 05:08:49 AM UTC 24
Finished Sep 04 05:08:52 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1366020970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1366020970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.2421112396
Short name T267
Test name
Test status
Simulation time 19544053 ps
CPU time 1.25 seconds
Started Sep 04 05:08:48 AM UTC 24
Finished Sep 04 05:08:50 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421112396 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2421112396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.391837626
Short name T976
Test name
Test status
Simulation time 17157714 ps
CPU time 1.43 seconds
Started Sep 04 05:08:47 AM UTC 24
Finished Sep 04 05:08:49 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391837626 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.391837626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.3921356181
Short name T274
Test name
Test status
Simulation time 28704770 ps
CPU time 1.92 seconds
Started Sep 04 05:08:49 AM UTC 24
Finished Sep 04 05:08:52 AM UTC 24
Peak memory 215300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921356181 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.3921356181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.2234044000
Short name T975
Test name
Test status
Simulation time 75190071 ps
CPU time 2.22 seconds
Started Sep 04 05:08:46 AM UTC 24
Finished Sep 04 05:08:49 AM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234044000 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2234044000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.68413634
Short name T282
Test name
Test status
Simulation time 70366274 ps
CPU time 2.48 seconds
Started Sep 04 05:08:47 AM UTC 24
Finished Sep 04 05:08:50 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68413634 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.68413634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1055499869
Short name T1079
Test name
Test status
Simulation time 43527658 ps
CPU time 1.29 seconds
Started Sep 04 05:09:28 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055499869 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1055499869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3574031094
Short name T1078
Test name
Test status
Simulation time 22713775 ps
CPU time 1.29 seconds
Started Sep 04 05:09:28 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574031094 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3574031094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.2037600189
Short name T1081
Test name
Test status
Simulation time 35675976 ps
CPU time 1.29 seconds
Started Sep 04 05:09:28 AM UTC 24
Finished Sep 04 05:09:30 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037600189 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2037600189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3638780194
Short name T1082
Test name
Test status
Simulation time 20656455 ps
CPU time 1.26 seconds
Started Sep 04 05:09:29 AM UTC 24
Finished Sep 04 05:09:31 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638780194 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3638780194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.505993053
Short name T1083
Test name
Test status
Simulation time 30351047 ps
CPU time 1.26 seconds
Started Sep 04 05:09:29 AM UTC 24
Finished Sep 04 05:09:32 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505993053 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.505993053
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1518215821
Short name T1085
Test name
Test status
Simulation time 16263610 ps
CPU time 1.18 seconds
Started Sep 04 05:09:30 AM UTC 24
Finished Sep 04 05:09:33 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518215821 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1518215821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.884203051
Short name T1086
Test name
Test status
Simulation time 53889623 ps
CPU time 1.21 seconds
Started Sep 04 05:09:30 AM UTC 24
Finished Sep 04 05:09:33 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884203051 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.884203051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3003274282
Short name T1084
Test name
Test status
Simulation time 24716250 ps
CPU time 1.06 seconds
Started Sep 04 05:09:30 AM UTC 24
Finished Sep 04 05:09:33 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003274282 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3003274282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.2284218396
Short name T1089
Test name
Test status
Simulation time 13373564 ps
CPU time 1.28 seconds
Started Sep 04 05:09:30 AM UTC 24
Finished Sep 04 05:09:33 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284218396 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2284218396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.4153171091
Short name T1088
Test name
Test status
Simulation time 54095316 ps
CPU time 1.19 seconds
Started Sep 04 05:09:31 AM UTC 24
Finished Sep 04 05:09:33 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153171091 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4153171091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.3995003401
Short name T986
Test name
Test status
Simulation time 231593255 ps
CPU time 1.78 seconds
Started Sep 04 05:08:52 AM UTC 24
Finished Sep 04 05:08:55 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995003401 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3995003401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.3801587691
Short name T269
Test name
Test status
Simulation time 1041488036 ps
CPU time 7.16 seconds
Started Sep 04 05:08:52 AM UTC 24
Finished Sep 04 05:09:00 AM UTC 24
Peak memory 217436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801587691 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3801587691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.2800058521
Short name T983
Test name
Test status
Simulation time 42381130 ps
CPU time 1.16 seconds
Started Sep 04 05:08:51 AM UTC 24
Finished Sep 04 05:08:53 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800058521 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2800058521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2234240377
Short name T987
Test name
Test status
Simulation time 42563848 ps
CPU time 2.11 seconds
Started Sep 04 05:08:52 AM UTC 24
Finished Sep 04 05:08:55 AM UTC 24
Peak memory 228048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2234240377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2234240377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2762464564
Short name T984
Test name
Test status
Simulation time 40597144 ps
CPU time 1.26 seconds
Started Sep 04 05:08:51 AM UTC 24
Finished Sep 04 05:08:53 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762464564 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2762464564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.3984987423
Short name T982
Test name
Test status
Simulation time 16161238 ps
CPU time 1.25 seconds
Started Sep 04 05:08:51 AM UTC 24
Finished Sep 04 05:08:53 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984987423 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3984987423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1911360980
Short name T275
Test name
Test status
Simulation time 24420367 ps
CPU time 1.68 seconds
Started Sep 04 05:08:52 AM UTC 24
Finished Sep 04 05:08:54 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911360980 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1911360980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.639313969
Short name T985
Test name
Test status
Simulation time 66780167 ps
CPU time 3.88 seconds
Started Sep 04 05:08:49 AM UTC 24
Finished Sep 04 05:08:54 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639313969 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.639313969
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2211205117
Short name T297
Test name
Test status
Simulation time 113858439 ps
CPU time 4.31 seconds
Started Sep 04 05:08:51 AM UTC 24
Finished Sep 04 05:08:56 AM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211205117 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2211205117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.4196795072
Short name T1087
Test name
Test status
Simulation time 82996734 ps
CPU time 1.19 seconds
Started Sep 04 05:09:31 AM UTC 24
Finished Sep 04 05:09:33 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196795072 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4196795072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.982634380
Short name T1090
Test name
Test status
Simulation time 18147834 ps
CPU time 1.29 seconds
Started Sep 04 05:09:32 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982634380 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.982634380
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3158919373
Short name T1092
Test name
Test status
Simulation time 57907252 ps
CPU time 1.33 seconds
Started Sep 04 05:09:32 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158919373 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3158919373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3217767802
Short name T1091
Test name
Test status
Simulation time 83679560 ps
CPU time 1.23 seconds
Started Sep 04 05:09:32 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217767802 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3217767802
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.3483558937
Short name T1093
Test name
Test status
Simulation time 152688113 ps
CPU time 1.29 seconds
Started Sep 04 05:09:32 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483558937 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3483558937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.4094627200
Short name T1095
Test name
Test status
Simulation time 14300008 ps
CPU time 1.31 seconds
Started Sep 04 05:09:33 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094627200 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.4094627200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.1705411023
Short name T1096
Test name
Test status
Simulation time 90301828 ps
CPU time 1.32 seconds
Started Sep 04 05:09:33 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705411023 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1705411023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.419820384
Short name T1094
Test name
Test status
Simulation time 16292211 ps
CPU time 1.03 seconds
Started Sep 04 05:09:33 AM UTC 24
Finished Sep 04 05:09:35 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419820384 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.419820384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2241940502
Short name T1099
Test name
Test status
Simulation time 19506939 ps
CPU time 1.35 seconds
Started Sep 04 05:09:34 AM UTC 24
Finished Sep 04 05:09:37 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241940502 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2241940502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3109271930
Short name T1097
Test name
Test status
Simulation time 33295254 ps
CPU time 1.18 seconds
Started Sep 04 05:09:34 AM UTC 24
Finished Sep 04 05:09:36 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109271930 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3109271930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.2942066342
Short name T268
Test name
Test status
Simulation time 39358161 ps
CPU time 2.29 seconds
Started Sep 04 05:08:55 AM UTC 24
Finished Sep 04 05:08:59 AM UTC 24
Peak memory 217444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942066342 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2942066342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.346652246
Short name T1003
Test name
Test status
Simulation time 523128874 ps
CPU time 7.28 seconds
Started Sep 04 05:08:55 AM UTC 24
Finished Sep 04 05:09:04 AM UTC 24
Peak memory 217436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346652246 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.346652246
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.3073203759
Short name T990
Test name
Test status
Simulation time 13704625 ps
CPU time 1.22 seconds
Started Sep 04 05:08:54 AM UTC 24
Finished Sep 04 05:08:56 AM UTC 24
Peak memory 215340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073203759 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3073203759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.482909579
Short name T993
Test name
Test status
Simulation time 12478945 ps
CPU time 1.25 seconds
Started Sep 04 05:08:56 AM UTC 24
Finished Sep 04 05:08:59 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=482909579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.482909579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.3519559959
Short name T992
Test name
Test status
Simulation time 161413134 ps
CPU time 1.31 seconds
Started Sep 04 05:08:54 AM UTC 24
Finished Sep 04 05:08:56 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519559959 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3519559959
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.2294335391
Short name T989
Test name
Test status
Simulation time 17423356 ps
CPU time 1.27 seconds
Started Sep 04 05:08:54 AM UTC 24
Finished Sep 04 05:08:56 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294335391 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2294335391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3737745417
Short name T276
Test name
Test status
Simulation time 30600952 ps
CPU time 1.88 seconds
Started Sep 04 05:08:55 AM UTC 24
Finished Sep 04 05:08:58 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737745417 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3737745417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.1076748079
Short name T988
Test name
Test status
Simulation time 41940289 ps
CPU time 2.31 seconds
Started Sep 04 05:08:53 AM UTC 24
Finished Sep 04 05:08:56 AM UTC 24
Peak memory 227296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076748079 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1076748079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.194606655
Short name T298
Test name
Test status
Simulation time 436657998 ps
CPU time 3.31 seconds
Started Sep 04 05:08:53 AM UTC 24
Finished Sep 04 05:08:57 AM UTC 24
Peak memory 227728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194606655 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.194606655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.303572286
Short name T1098
Test name
Test status
Simulation time 57311367 ps
CPU time 1.24 seconds
Started Sep 04 05:09:34 AM UTC 24
Finished Sep 04 05:09:37 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303572286 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.303572286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1623685030
Short name T1102
Test name
Test status
Simulation time 34590277 ps
CPU time 1.3 seconds
Started Sep 04 05:09:34 AM UTC 24
Finished Sep 04 05:09:37 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623685030 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1623685030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2916622024
Short name T1100
Test name
Test status
Simulation time 37676617 ps
CPU time 1.19 seconds
Started Sep 04 05:09:34 AM UTC 24
Finished Sep 04 05:09:37 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916622024 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2916622024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.876742171
Short name T1101
Test name
Test status
Simulation time 21141911 ps
CPU time 1.18 seconds
Started Sep 04 05:09:34 AM UTC 24
Finished Sep 04 05:09:37 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876742171 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.876742171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2499964684
Short name T1103
Test name
Test status
Simulation time 90698607 ps
CPU time 1.14 seconds
Started Sep 04 05:09:35 AM UTC 24
Finished Sep 04 05:09:38 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499964684 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2499964684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.2475403065
Short name T1104
Test name
Test status
Simulation time 12885577 ps
CPU time 1.3 seconds
Started Sep 04 05:09:36 AM UTC 24
Finished Sep 04 05:09:38 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475403065 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2475403065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1207688389
Short name T1105
Test name
Test status
Simulation time 12740740 ps
CPU time 1.3 seconds
Started Sep 04 05:09:36 AM UTC 24
Finished Sep 04 05:09:38 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207688389 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1207688389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3800314512
Short name T1106
Test name
Test status
Simulation time 39538583 ps
CPU time 1.27 seconds
Started Sep 04 05:09:36 AM UTC 24
Finished Sep 04 05:09:38 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800314512 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3800314512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.372645256
Short name T1107
Test name
Test status
Simulation time 75964450 ps
CPU time 1.28 seconds
Started Sep 04 05:09:36 AM UTC 24
Finished Sep 04 05:09:38 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372645256 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.372645256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.3902444597
Short name T1108
Test name
Test status
Simulation time 13645157 ps
CPU time 1.34 seconds
Started Sep 04 05:09:37 AM UTC 24
Finished Sep 04 05:09:39 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902444597 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3902444597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2509551222
Short name T995
Test name
Test status
Simulation time 187152790 ps
CPU time 1.56 seconds
Started Sep 04 05:08:58 AM UTC 24
Finished Sep 04 05:09:00 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2509551222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2509551222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.3255631796
Short name T270
Test name
Test status
Simulation time 75886909 ps
CPU time 1.32 seconds
Started Sep 04 05:08:58 AM UTC 24
Finished Sep 04 05:09:00 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255631796 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3255631796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.2906218858
Short name T994
Test name
Test status
Simulation time 46768030 ps
CPU time 1.27 seconds
Started Sep 04 05:08:58 AM UTC 24
Finished Sep 04 05:09:00 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906218858 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2906218858
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.3915309871
Short name T277
Test name
Test status
Simulation time 85802878 ps
CPU time 1.61 seconds
Started Sep 04 05:08:58 AM UTC 24
Finished Sep 04 05:09:00 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915309871 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.3915309871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.999551315
Short name T996
Test name
Test status
Simulation time 241000244 ps
CPU time 3.34 seconds
Started Sep 04 05:08:57 AM UTC 24
Finished Sep 04 05:09:01 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999551315 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.999551315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.4196404441
Short name T301
Test name
Test status
Simulation time 261507512 ps
CPU time 2.5 seconds
Started Sep 04 05:08:58 AM UTC 24
Finished Sep 04 05:09:01 AM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196404441 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4196404441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1012345741
Short name T1005
Test name
Test status
Simulation time 22123127 ps
CPU time 1.77 seconds
Started Sep 04 05:09:01 AM UTC 24
Finished Sep 04 05:09:04 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1012345741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1012345741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.1909235194
Short name T999
Test name
Test status
Simulation time 24196230 ps
CPU time 1.32 seconds
Started Sep 04 05:08:59 AM UTC 24
Finished Sep 04 05:09:01 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909235194 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1909235194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.602984579
Short name T998
Test name
Test status
Simulation time 14224380 ps
CPU time 1.33 seconds
Started Sep 04 05:08:59 AM UTC 24
Finished Sep 04 05:09:01 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602984579 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.602984579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.1765349638
Short name T1004
Test name
Test status
Simulation time 29089160 ps
CPU time 1.56 seconds
Started Sep 04 05:09:01 AM UTC 24
Finished Sep 04 05:09:04 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765349638 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.1765349638
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2909600627
Short name T997
Test name
Test status
Simulation time 29404339 ps
CPU time 2.15 seconds
Started Sep 04 05:08:58 AM UTC 24
Finished Sep 04 05:09:01 AM UTC 24
Peak memory 228052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909600627 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2909600627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.3498598647
Short name T1001
Test name
Test status
Simulation time 303726508 ps
CPU time 3.08 seconds
Started Sep 04 05:08:59 AM UTC 24
Finished Sep 04 05:09:03 AM UTC 24
Peak memory 217564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498598647 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3498598647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1268930635
Short name T1006
Test name
Test status
Simulation time 36476938 ps
CPU time 1.76 seconds
Started Sep 04 05:09:03 AM UTC 24
Finished Sep 04 05:09:05 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1268930635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1268930635
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1354970478
Short name T271
Test name
Test status
Simulation time 14963933 ps
CPU time 1.39 seconds
Started Sep 04 05:09:01 AM UTC 24
Finished Sep 04 05:09:04 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354970478 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1354970478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1132108061
Short name T1002
Test name
Test status
Simulation time 31163783 ps
CPU time 1.14 seconds
Started Sep 04 05:09:01 AM UTC 24
Finished Sep 04 05:09:03 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132108061 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1132108061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.215645054
Short name T1007
Test name
Test status
Simulation time 157767185 ps
CPU time 1.72 seconds
Started Sep 04 05:09:02 AM UTC 24
Finished Sep 04 05:09:05 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215645054 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.215645054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2588896792
Short name T1010
Test name
Test status
Simulation time 148691998 ps
CPU time 3.97 seconds
Started Sep 04 05:09:01 AM UTC 24
Finished Sep 04 05:09:06 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588896792 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2588896792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3209346243
Short name T1017
Test name
Test status
Simulation time 206211690 ps
CPU time 2.99 seconds
Started Sep 04 05:09:05 AM UTC 24
Finished Sep 04 05:09:09 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3209346243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3209346243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.879876092
Short name T1011
Test name
Test status
Simulation time 24730058 ps
CPU time 1.32 seconds
Started Sep 04 05:09:05 AM UTC 24
Finished Sep 04 05:09:07 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879876092 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.879876092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2977634611
Short name T1008
Test name
Test status
Simulation time 14666373 ps
CPU time 1.35 seconds
Started Sep 04 05:09:04 AM UTC 24
Finished Sep 04 05:09:06 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977634611 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2977634611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.1072382454
Short name T1013
Test name
Test status
Simulation time 102268972 ps
CPU time 2.05 seconds
Started Sep 04 05:09:05 AM UTC 24
Finished Sep 04 05:09:08 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072382454 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.1072382454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.892322259
Short name T1009
Test name
Test status
Simulation time 28500995 ps
CPU time 2.65 seconds
Started Sep 04 05:09:03 AM UTC 24
Finished Sep 04 05:09:06 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892322259 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.892322259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2781851862
Short name T1012
Test name
Test status
Simulation time 78464374 ps
CPU time 3.46 seconds
Started Sep 04 05:09:03 AM UTC 24
Finished Sep 04 05:09:07 AM UTC 24
Peak memory 227676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781851862 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2781851862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2076644194
Short name T1018
Test name
Test status
Simulation time 35582092 ps
CPU time 2.13 seconds
Started Sep 04 05:09:07 AM UTC 24
Finished Sep 04 05:09:10 AM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2076644194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2076644194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1619680651
Short name T1015
Test name
Test status
Simulation time 11248586 ps
CPU time 1.3 seconds
Started Sep 04 05:09:06 AM UTC 24
Finished Sep 04 05:09:08 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619680651 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1619680651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.2936070476
Short name T1014
Test name
Test status
Simulation time 18694189 ps
CPU time 1.25 seconds
Started Sep 04 05:09:06 AM UTC 24
Finished Sep 04 05:09:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936070476 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2936070476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1455595307
Short name T1016
Test name
Test status
Simulation time 16021241 ps
CPU time 1.37 seconds
Started Sep 04 05:09:07 AM UTC 24
Finished Sep 04 05:09:10 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455595307 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.1455595307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.548934232
Short name T1021
Test name
Test status
Simulation time 51902884 ps
CPU time 5.07 seconds
Started Sep 04 05:09:05 AM UTC 24
Finished Sep 04 05:09:11 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548934232 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.548934232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3725124303
Short name T300
Test name
Test status
Simulation time 141349114 ps
CPU time 3.18 seconds
Started Sep 04 05:09:05 AM UTC 24
Finished Sep 04 05:09:09 AM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725124303 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3725124303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_alert_test.893686210
Short name T57
Test name
Test status
Simulation time 15501231 ps
CPU time 1.4 seconds
Started Sep 04 04:59:37 AM UTC 24
Finished Sep 04 04:59:40 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893686210 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.893686210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_disable.1571000647
Short name T23
Test name
Test status
Simulation time 29482305 ps
CPU time 1.4 seconds
Started Sep 04 04:59:34 AM UTC 24
Finished Sep 04 04:59:36 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571000647 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1571000647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_err.1087229230
Short name T6
Test name
Test status
Simulation time 74423925 ps
CPU time 1.66 seconds
Started Sep 04 04:59:34 AM UTC 24
Finished Sep 04 04:59:37 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087229230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.1087229230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_genbits.1008163333
Short name T3
Test name
Test status
Simulation time 40480986 ps
CPU time 1.7 seconds
Started Sep 04 04:59:29 AM UTC 24
Finished Sep 04 04:59:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008163333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1008163333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_intr.665880058
Short name T4
Test name
Test status
Simulation time 67272158 ps
CPU time 1.31 seconds
Started Sep 04 04:59:31 AM UTC 24
Finished Sep 04 04:59:33 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665880058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.665880058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_regwen.3141792827
Short name T2
Test name
Test status
Simulation time 14513020 ps
CPU time 1.44 seconds
Started Sep 04 04:59:27 AM UTC 24
Finished Sep 04 04:59:30 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141792827 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.3141792827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/0.edn_smoke.1711348197
Short name T1
Test name
Test status
Simulation time 50845998 ps
CPU time 1.38 seconds
Started Sep 04 04:59:27 AM UTC 24
Finished Sep 04 04:59:30 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711348197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_smoke.1711348197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_alert.360760291
Short name T12
Test name
Test status
Simulation time 32906571 ps
CPU time 1.93 seconds
Started Sep 04 04:59:44 AM UTC 24
Finished Sep 04 04:59:47 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360760291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.edn_alert.360760291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_alert_test.334046240
Short name T66
Test name
Test status
Simulation time 97757331 ps
CPU time 2.04 seconds
Started Sep 04 04:59:47 AM UTC 24
Finished Sep 04 04:59:50 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334046240 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.334046240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.1911191831
Short name T18
Test name
Test status
Simulation time 43323109 ps
CPU time 1.96 seconds
Started Sep 04 04:59:46 AM UTC 24
Finished Sep 04 04:59:49 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911191831 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1911191831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_err.1872864846
Short name T62
Test name
Test status
Simulation time 66947630 ps
CPU time 1.27 seconds
Started Sep 04 04:59:45 AM UTC 24
Finished Sep 04 04:59:47 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872864846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.1872864846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_intr.3828397560
Short name T27
Test name
Test status
Simulation time 33915545 ps
CPU time 1.19 seconds
Started Sep 04 04:59:43 AM UTC 24
Finished Sep 04 04:59:45 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828397560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.3828397560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_regwen.2762132266
Short name T69
Test name
Test status
Simulation time 24779380 ps
CPU time 1.43 seconds
Started Sep 04 04:59:39 AM UTC 24
Finished Sep 04 04:59:42 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762132266 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.2762132266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_sec_cm.2806742544
Short name T17
Test name
Test status
Simulation time 524633787 ps
CPU time 11.03 seconds
Started Sep 04 04:59:46 AM UTC 24
Finished Sep 04 04:59:58 AM UTC 24
Peak memory 259920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806742544 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2806742544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_smoke.2974698672
Short name T24
Test name
Test status
Simulation time 50023019 ps
CPU time 1.33 seconds
Started Sep 04 04:59:37 AM UTC 24
Finished Sep 04 04:59:39 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974698672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.2974698672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_stress_all.3610953534
Short name T40
Test name
Test status
Simulation time 651222409 ps
CPU time 5.39 seconds
Started Sep 04 04:59:40 AM UTC 24
Finished Sep 04 04:59:47 AM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610953534 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3610953534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.1481073501
Short name T224
Test name
Test status
Simulation time 19193796005 ps
CPU time 150.53 seconds
Started Sep 04 04:59:41 AM UTC 24
Finished Sep 04 05:02:15 AM UTC 24
Peak memory 229748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1481073501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_
with_rand_reset.1481073501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_alert.2665329639
Short name T172
Test name
Test status
Simulation time 41877290 ps
CPU time 1.73 seconds
Started Sep 04 05:00:35 AM UTC 24
Finished Sep 04 05:00:39 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665329639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.2665329639
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_alert_test.1890134074
Short name T360
Test name
Test status
Simulation time 26307054 ps
CPU time 1.69 seconds
Started Sep 04 05:00:39 AM UTC 24
Finished Sep 04 05:00:41 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890134074 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1890134074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_disable.1654260085
Short name T161
Test name
Test status
Simulation time 10919830 ps
CPU time 1.39 seconds
Started Sep 04 05:00:36 AM UTC 24
Finished Sep 04 05:00:38 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654260085 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1654260085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.210929616
Short name T140
Test name
Test status
Simulation time 92492842 ps
CPU time 1.64 seconds
Started Sep 04 05:00:37 AM UTC 24
Finished Sep 04 05:00:40 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210929616 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.210929616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_err.2195336845
Short name T357
Test name
Test status
Simulation time 36975449 ps
CPU time 1.35 seconds
Started Sep 04 05:00:35 AM UTC 24
Finished Sep 04 05:00:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195336845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.2195336845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_genbits.1850075429
Short name T283
Test name
Test status
Simulation time 277161795 ps
CPU time 1.56 seconds
Started Sep 04 05:00:33 AM UTC 24
Finished Sep 04 05:00:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850075429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1850075429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_intr.647736597
Short name T358
Test name
Test status
Simulation time 38153541 ps
CPU time 1.57 seconds
Started Sep 04 05:00:35 AM UTC 24
Finished Sep 04 05:00:38 AM UTC 24
Peak memory 237880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647736597 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.647736597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_smoke.1202507718
Short name T355
Test name
Test status
Simulation time 31154890 ps
CPU time 1.22 seconds
Started Sep 04 05:00:32 AM UTC 24
Finished Sep 04 05:00:35 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202507718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.1202507718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_stress_all.1885099018
Short name T241
Test name
Test status
Simulation time 77499770 ps
CPU time 2.67 seconds
Started Sep 04 05:00:33 AM UTC 24
Finished Sep 04 05:00:37 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885099018 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1885099018
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.3799874466
Short name T36
Test name
Test status
Simulation time 4868267118 ps
CPU time 81.81 seconds
Started Sep 04 05:00:33 AM UTC 24
Finished Sep 04 05:01:58 AM UTC 24
Peak memory 233968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3799874466 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all
_with_rand_reset.3799874466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/100.edn_alert.1520253382
Short name T260
Test name
Test status
Simulation time 278921799 ps
CPU time 1.78 seconds
Started Sep 04 05:07:02 AM UTC 24
Finished Sep 04 05:07:05 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520253382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 100.edn_alert.1520253382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/100.edn_genbits.541277593
Short name T694
Test name
Test status
Simulation time 49304729 ps
CPU time 2.44 seconds
Started Sep 04 05:07:02 AM UTC 24
Finished Sep 04 05:07:06 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541277593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 100.edn_genbits.541277593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/101.edn_alert.4215040726
Short name T695
Test name
Test status
Simulation time 43154640 ps
CPU time 1.65 seconds
Started Sep 04 05:07:03 AM UTC 24
Finished Sep 04 05:07:06 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215040726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 101.edn_alert.4215040726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/101.edn_genbits.1612920501
Short name T325
Test name
Test status
Simulation time 34301516 ps
CPU time 1.89 seconds
Started Sep 04 05:07:02 AM UTC 24
Finished Sep 04 05:07:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612920501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1612920501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/102.edn_alert.631176724
Short name T696
Test name
Test status
Simulation time 20466811 ps
CPU time 1.67 seconds
Started Sep 04 05:07:03 AM UTC 24
Finished Sep 04 05:07:06 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631176724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 102.edn_alert.631176724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/102.edn_genbits.3424141150
Short name T697
Test name
Test status
Simulation time 91509872 ps
CPU time 1.73 seconds
Started Sep 04 05:07:03 AM UTC 24
Finished Sep 04 05:07:06 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424141150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3424141150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/103.edn_alert.2343522210
Short name T699
Test name
Test status
Simulation time 41283173 ps
CPU time 1.7 seconds
Started Sep 04 05:07:05 AM UTC 24
Finished Sep 04 05:07:07 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343522210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.2343522210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/103.edn_genbits.3607346696
Short name T698
Test name
Test status
Simulation time 21340037 ps
CPU time 1.56 seconds
Started Sep 04 05:07:05 AM UTC 24
Finished Sep 04 05:07:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607346696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3607346696
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/104.edn_alert.4228433306
Short name T701
Test name
Test status
Simulation time 45792280 ps
CPU time 1.77 seconds
Started Sep 04 05:07:06 AM UTC 24
Finished Sep 04 05:07:09 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228433306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 104.edn_alert.4228433306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/105.edn_alert.3024802085
Short name T196
Test name
Test status
Simulation time 111922784 ps
CPU time 1.88 seconds
Started Sep 04 05:07:06 AM UTC 24
Finished Sep 04 05:07:09 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024802085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 105.edn_alert.3024802085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/105.edn_genbits.2323382709
Short name T700
Test name
Test status
Simulation time 55714093 ps
CPU time 1.76 seconds
Started Sep 04 05:07:06 AM UTC 24
Finished Sep 04 05:07:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323382709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2323382709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/106.edn_alert.3430431994
Short name T702
Test name
Test status
Simulation time 52167774 ps
CPU time 1.42 seconds
Started Sep 04 05:07:07 AM UTC 24
Finished Sep 04 05:07:09 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430431994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.3430431994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/106.edn_genbits.82714335
Short name T336
Test name
Test status
Simulation time 71767641 ps
CPU time 3.24 seconds
Started Sep 04 05:07:06 AM UTC 24
Finished Sep 04 05:07:10 AM UTC 24
Peak memory 231488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82714335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 106.edn_genbits.82714335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/107.edn_alert.1379570797
Short name T703
Test name
Test status
Simulation time 26940142 ps
CPU time 1.8 seconds
Started Sep 04 05:07:07 AM UTC 24
Finished Sep 04 05:07:10 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379570797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.1379570797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/107.edn_genbits.3659987330
Short name T330
Test name
Test status
Simulation time 92925131 ps
CPU time 2.48 seconds
Started Sep 04 05:07:07 AM UTC 24
Finished Sep 04 05:07:11 AM UTC 24
Peak memory 231484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659987330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3659987330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/108.edn_alert.1832006308
Short name T705
Test name
Test status
Simulation time 53876568 ps
CPU time 1.92 seconds
Started Sep 04 05:07:08 AM UTC 24
Finished Sep 04 05:07:11 AM UTC 24
Peak memory 231456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832006308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.edn_alert.1832006308
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/108.edn_genbits.3254585326
Short name T704
Test name
Test status
Simulation time 92123926 ps
CPU time 1.67 seconds
Started Sep 04 05:07:07 AM UTC 24
Finished Sep 04 05:07:10 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254585326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3254585326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/109.edn_alert.114030841
Short name T708
Test name
Test status
Simulation time 28456212 ps
CPU time 1.77 seconds
Started Sep 04 05:07:09 AM UTC 24
Finished Sep 04 05:07:12 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114030841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 109.edn_alert.114030841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_alert.4049665371
Short name T146
Test name
Test status
Simulation time 48430607 ps
CPU time 1.83 seconds
Started Sep 04 05:00:42 AM UTC 24
Finished Sep 04 05:00:45 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049665371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.4049665371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_alert_test.2181101917
Short name T361
Test name
Test status
Simulation time 59455279 ps
CPU time 1.42 seconds
Started Sep 04 05:00:46 AM UTC 24
Finished Sep 04 05:00:49 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181101917 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2181101917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_genbits.836592559
Short name T49
Test name
Test status
Simulation time 105206169 ps
CPU time 2.38 seconds
Started Sep 04 05:00:39 AM UTC 24
Finished Sep 04 05:00:42 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836592559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_genbits.836592559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_intr.1923044148
Short name T242
Test name
Test status
Simulation time 25630082 ps
CPU time 1.82 seconds
Started Sep 04 05:00:41 AM UTC 24
Finished Sep 04 05:00:44 AM UTC 24
Peak memory 237404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923044148 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.1923044148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/11.edn_smoke.4058717093
Short name T359
Test name
Test status
Simulation time 51880177 ps
CPU time 1.47 seconds
Started Sep 04 05:00:39 AM UTC 24
Finished Sep 04 05:00:41 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058717093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.4058717093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/110.edn_genbits.745928170
Short name T709
Test name
Test status
Simulation time 36402904 ps
CPU time 1.95 seconds
Started Sep 04 05:07:09 AM UTC 24
Finished Sep 04 05:07:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745928170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 110.edn_genbits.745928170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/111.edn_alert.3732585072
Short name T711
Test name
Test status
Simulation time 98373892 ps
CPU time 1.64 seconds
Started Sep 04 05:07:11 AM UTC 24
Finished Sep 04 05:07:13 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732585072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.3732585072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/111.edn_genbits.246659661
Short name T710
Test name
Test status
Simulation time 93748314 ps
CPU time 1.96 seconds
Started Sep 04 05:07:09 AM UTC 24
Finished Sep 04 05:07:12 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246659661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 111.edn_genbits.246659661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/112.edn_alert.2455390621
Short name T713
Test name
Test status
Simulation time 38840831 ps
CPU time 1.63 seconds
Started Sep 04 05:07:11 AM UTC 24
Finished Sep 04 05:07:13 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455390621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.2455390621
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/112.edn_genbits.1788585914
Short name T714
Test name
Test status
Simulation time 51423735 ps
CPU time 2.1 seconds
Started Sep 04 05:07:11 AM UTC 24
Finished Sep 04 05:07:14 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788585914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1788585914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/113.edn_alert.2114366798
Short name T715
Test name
Test status
Simulation time 35495051 ps
CPU time 1.62 seconds
Started Sep 04 05:07:12 AM UTC 24
Finished Sep 04 05:07:14 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114366798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.2114366798
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/113.edn_genbits.1010689096
Short name T712
Test name
Test status
Simulation time 78300558 ps
CPU time 1.48 seconds
Started Sep 04 05:07:11 AM UTC 24
Finished Sep 04 05:07:13 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010689096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1010689096
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/114.edn_alert.3254040938
Short name T717
Test name
Test status
Simulation time 89394921 ps
CPU time 1.69 seconds
Started Sep 04 05:07:13 AM UTC 24
Finished Sep 04 05:07:16 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254040938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.3254040938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/114.edn_genbits.1511571357
Short name T319
Test name
Test status
Simulation time 62920888 ps
CPU time 1.42 seconds
Started Sep 04 05:07:12 AM UTC 24
Finished Sep 04 05:07:14 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511571357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1511571357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/115.edn_genbits.2186903934
Short name T719
Test name
Test status
Simulation time 251298168 ps
CPU time 1.83 seconds
Started Sep 04 05:07:13 AM UTC 24
Finished Sep 04 05:07:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186903934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2186903934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/116.edn_alert.3516214335
Short name T716
Test name
Test status
Simulation time 28370580 ps
CPU time 1.11 seconds
Started Sep 04 05:07:13 AM UTC 24
Finished Sep 04 05:07:15 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516214335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.3516214335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/116.edn_genbits.1733488127
Short name T720
Test name
Test status
Simulation time 72662521 ps
CPU time 2.03 seconds
Started Sep 04 05:07:13 AM UTC 24
Finished Sep 04 05:07:16 AM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733488127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1733488127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/117.edn_alert.2036268135
Short name T721
Test name
Test status
Simulation time 46724207 ps
CPU time 1.75 seconds
Started Sep 04 05:07:14 AM UTC 24
Finished Sep 04 05:07:17 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036268135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.2036268135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/117.edn_genbits.2214682690
Short name T725
Test name
Test status
Simulation time 52813326 ps
CPU time 2.9 seconds
Started Sep 04 05:07:14 AM UTC 24
Finished Sep 04 05:07:18 AM UTC 24
Peak memory 229460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214682690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2214682690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/118.edn_alert.537256049
Short name T722
Test name
Test status
Simulation time 22179088 ps
CPU time 1.61 seconds
Started Sep 04 05:07:14 AM UTC 24
Finished Sep 04 05:07:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537256049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 118.edn_alert.537256049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/118.edn_genbits.3001632772
Short name T724
Test name
Test status
Simulation time 44428079 ps
CPU time 2.59 seconds
Started Sep 04 05:07:14 AM UTC 24
Finished Sep 04 05:07:18 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001632772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3001632772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/119.edn_alert.2294744937
Short name T726
Test name
Test status
Simulation time 131779004 ps
CPU time 1.68 seconds
Started Sep 04 05:07:15 AM UTC 24
Finished Sep 04 05:07:18 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294744937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.2294744937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/119.edn_genbits.1567004208
Short name T727
Test name
Test status
Simulation time 37093986 ps
CPU time 1.94 seconds
Started Sep 04 05:07:15 AM UTC 24
Finished Sep 04 05:07:18 AM UTC 24
Peak memory 228620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567004208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1567004208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_alert_test.2558236392
Short name T364
Test name
Test status
Simulation time 47467443 ps
CPU time 1.29 seconds
Started Sep 04 05:00:54 AM UTC 24
Finished Sep 04 05:00:56 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558236392 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2558236392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_disable.2478885884
Short name T85
Test name
Test status
Simulation time 32013621 ps
CPU time 1.19 seconds
Started Sep 04 05:00:53 AM UTC 24
Finished Sep 04 05:00:55 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478885884 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2478885884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.2039322597
Short name T363
Test name
Test status
Simulation time 56392728 ps
CPU time 1.84 seconds
Started Sep 04 05:00:53 AM UTC 24
Finished Sep 04 05:00:56 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039322597 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.2039322597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_err.1680578317
Short name T164
Test name
Test status
Simulation time 35559447 ps
CPU time 1.22 seconds
Started Sep 04 05:00:51 AM UTC 24
Finished Sep 04 05:00:53 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680578317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.1680578317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_genbits.2462664970
Short name T294
Test name
Test status
Simulation time 131413406 ps
CPU time 2.5 seconds
Started Sep 04 05:00:46 AM UTC 24
Finished Sep 04 05:00:50 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462664970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2462664970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_intr.3771177185
Short name T29
Test name
Test status
Simulation time 29603514 ps
CPU time 1.36 seconds
Started Sep 04 05:00:50 AM UTC 24
Finished Sep 04 05:00:52 AM UTC 24
Peak memory 228488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771177185 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.3771177185
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/12.edn_smoke.206115912
Short name T362
Test name
Test status
Simulation time 91169976 ps
CPU time 1.39 seconds
Started Sep 04 05:00:46 AM UTC 24
Finished Sep 04 05:00:49 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206115912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.edn_smoke.206115912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/120.edn_alert.4022196084
Short name T728
Test name
Test status
Simulation time 46231819 ps
CPU time 1.77 seconds
Started Sep 04 05:07:16 AM UTC 24
Finished Sep 04 05:07:19 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022196084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.4022196084
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/120.edn_genbits.458336583
Short name T742
Test name
Test status
Simulation time 281113169 ps
CPU time 6.05 seconds
Started Sep 04 05:07:16 AM UTC 24
Finished Sep 04 05:07:24 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458336583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 120.edn_genbits.458336583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/121.edn_alert.928949319
Short name T729
Test name
Test status
Simulation time 23836178 ps
CPU time 1.78 seconds
Started Sep 04 05:07:17 AM UTC 24
Finished Sep 04 05:07:19 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928949319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 121.edn_alert.928949319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/121.edn_genbits.1950865669
Short name T730
Test name
Test status
Simulation time 99759749 ps
CPU time 1.85 seconds
Started Sep 04 05:07:17 AM UTC 24
Finished Sep 04 05:07:19 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950865669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1950865669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/122.edn_alert.2364408141
Short name T733
Test name
Test status
Simulation time 88198456 ps
CPU time 1.65 seconds
Started Sep 04 05:07:18 AM UTC 24
Finished Sep 04 05:07:20 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364408141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 122.edn_alert.2364408141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/122.edn_genbits.52366295
Short name T731
Test name
Test status
Simulation time 103752713 ps
CPU time 2.03 seconds
Started Sep 04 05:07:17 AM UTC 24
Finished Sep 04 05:07:20 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52366295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 122.edn_genbits.52366295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/123.edn_alert.1942425231
Short name T735
Test name
Test status
Simulation time 28785895 ps
CPU time 1.89 seconds
Started Sep 04 05:07:19 AM UTC 24
Finished Sep 04 05:07:22 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942425231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.1942425231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/123.edn_genbits.2066936401
Short name T732
Test name
Test status
Simulation time 86392046 ps
CPU time 1.54 seconds
Started Sep 04 05:07:18 AM UTC 24
Finished Sep 04 05:07:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066936401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2066936401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/124.edn_alert.4012925346
Short name T734
Test name
Test status
Simulation time 78421282 ps
CPU time 1.59 seconds
Started Sep 04 05:07:19 AM UTC 24
Finished Sep 04 05:07:22 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012925346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.4012925346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/124.edn_genbits.2401100645
Short name T736
Test name
Test status
Simulation time 36986176 ps
CPU time 1.98 seconds
Started Sep 04 05:07:19 AM UTC 24
Finished Sep 04 05:07:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401100645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2401100645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/125.edn_genbits.1871354564
Short name T737
Test name
Test status
Simulation time 56252514 ps
CPU time 2.27 seconds
Started Sep 04 05:07:19 AM UTC 24
Finished Sep 04 05:07:22 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871354564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1871354564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/126.edn_alert.1135866590
Short name T739
Test name
Test status
Simulation time 169213753 ps
CPU time 1.83 seconds
Started Sep 04 05:07:20 AM UTC 24
Finished Sep 04 05:07:23 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135866590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.1135866590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/126.edn_genbits.1340618478
Short name T741
Test name
Test status
Simulation time 61061959 ps
CPU time 1.97 seconds
Started Sep 04 05:07:20 AM UTC 24
Finished Sep 04 05:07:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340618478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1340618478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/127.edn_alert.563990758
Short name T738
Test name
Test status
Simulation time 29253944 ps
CPU time 1.76 seconds
Started Sep 04 05:07:20 AM UTC 24
Finished Sep 04 05:07:23 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563990758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 127.edn_alert.563990758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/127.edn_genbits.1017876210
Short name T745
Test name
Test status
Simulation time 121562233 ps
CPU time 3.45 seconds
Started Sep 04 05:07:20 AM UTC 24
Finished Sep 04 05:07:25 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017876210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1017876210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/128.edn_alert.586474199
Short name T743
Test name
Test status
Simulation time 30513287 ps
CPU time 1.74 seconds
Started Sep 04 05:07:21 AM UTC 24
Finished Sep 04 05:07:24 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586474199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 128.edn_alert.586474199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/128.edn_genbits.2935009130
Short name T744
Test name
Test status
Simulation time 111140804 ps
CPU time 1.85 seconds
Started Sep 04 05:07:21 AM UTC 24
Finished Sep 04 05:07:24 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935009130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2935009130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/129.edn_alert.1630204846
Short name T746
Test name
Test status
Simulation time 95559842 ps
CPU time 1.25 seconds
Started Sep 04 05:07:23 AM UTC 24
Finished Sep 04 05:07:25 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630204846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 129.edn_alert.1630204846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/129.edn_genbits.1702810265
Short name T747
Test name
Test status
Simulation time 37423852 ps
CPU time 1.44 seconds
Started Sep 04 05:07:22 AM UTC 24
Finished Sep 04 05:07:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702810265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1702810265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_alert.3720877243
Short name T367
Test name
Test status
Simulation time 76209531 ps
CPU time 1.75 seconds
Started Sep 04 05:00:57 AM UTC 24
Finished Sep 04 05:01:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720877243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.3720877243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_alert_test.498134488
Short name T369
Test name
Test status
Simulation time 22843200 ps
CPU time 1.35 seconds
Started Sep 04 05:01:01 AM UTC 24
Finished Sep 04 05:01:03 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498134488 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.498134488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_disable.1806699971
Short name T368
Test name
Test status
Simulation time 13537705 ps
CPU time 1.35 seconds
Started Sep 04 05:00:59 AM UTC 24
Finished Sep 04 05:01:01 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806699971 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1806699971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.1431359188
Short name T129
Test name
Test status
Simulation time 87390934 ps
CPU time 1.7 seconds
Started Sep 04 05:00:59 AM UTC 24
Finished Sep 04 05:01:01 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431359188 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.1431359188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_genbits.2611905577
Short name T73
Test name
Test status
Simulation time 86626444 ps
CPU time 1.92 seconds
Started Sep 04 05:00:55 AM UTC 24
Finished Sep 04 05:00:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611905577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2611905577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_intr.30395918
Short name T366
Test name
Test status
Simulation time 38051995 ps
CPU time 1.46 seconds
Started Sep 04 05:00:57 AM UTC 24
Finished Sep 04 05:01:00 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30395918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in
tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_intr.30395918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_smoke.192747157
Short name T365
Test name
Test status
Simulation time 18959059 ps
CPU time 1.39 seconds
Started Sep 04 05:00:54 AM UTC 24
Finished Sep 04 05:00:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192747157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_smoke.192747157
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/13.edn_stress_all.320025624
Short name T371
Test name
Test status
Simulation time 427912436 ps
CPU time 6.64 seconds
Started Sep 04 05:00:56 AM UTC 24
Finished Sep 04 05:01:04 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320025624 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.320025624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/130.edn_alert.2339002510
Short name T190
Test name
Test status
Simulation time 85056822 ps
CPU time 1.72 seconds
Started Sep 04 05:07:23 AM UTC 24
Finished Sep 04 05:07:26 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339002510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.2339002510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/130.edn_genbits.1150772187
Short name T749
Test name
Test status
Simulation time 136258744 ps
CPU time 1.96 seconds
Started Sep 04 05:07:23 AM UTC 24
Finished Sep 04 05:07:26 AM UTC 24
Peak memory 230684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150772187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1150772187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/131.edn_alert.3836184099
Short name T750
Test name
Test status
Simulation time 24689961 ps
CPU time 1.31 seconds
Started Sep 04 05:07:24 AM UTC 24
Finished Sep 04 05:07:26 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836184099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.3836184099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/131.edn_genbits.4275987347
Short name T754
Test name
Test status
Simulation time 63893775 ps
CPU time 3.02 seconds
Started Sep 04 05:07:24 AM UTC 24
Finished Sep 04 05:07:28 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275987347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4275987347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/132.edn_alert.1259848598
Short name T751
Test name
Test status
Simulation time 194471189 ps
CPU time 1.69 seconds
Started Sep 04 05:07:24 AM UTC 24
Finished Sep 04 05:07:27 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259848598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.1259848598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/132.edn_genbits.3839272620
Short name T752
Test name
Test status
Simulation time 54649601 ps
CPU time 1.85 seconds
Started Sep 04 05:07:24 AM UTC 24
Finished Sep 04 05:07:27 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839272620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3839272620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/133.edn_alert.4193398386
Short name T753
Test name
Test status
Simulation time 33737123 ps
CPU time 1.43 seconds
Started Sep 04 05:07:25 AM UTC 24
Finished Sep 04 05:07:27 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193398386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 133.edn_alert.4193398386
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/133.edn_genbits.2487715717
Short name T757
Test name
Test status
Simulation time 145590340 ps
CPU time 2.03 seconds
Started Sep 04 05:07:25 AM UTC 24
Finished Sep 04 05:07:28 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487715717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2487715717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/134.edn_alert.1591011844
Short name T759
Test name
Test status
Simulation time 23888056 ps
CPU time 1.21 seconds
Started Sep 04 05:07:26 AM UTC 24
Finished Sep 04 05:07:28 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591011844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.1591011844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/134.edn_genbits.2278352646
Short name T758
Test name
Test status
Simulation time 88657339 ps
CPU time 2.05 seconds
Started Sep 04 05:07:25 AM UTC 24
Finished Sep 04 05:07:28 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278352646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2278352646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/135.edn_genbits.2281181363
Short name T763
Test name
Test status
Simulation time 109593935 ps
CPU time 2.3 seconds
Started Sep 04 05:07:26 AM UTC 24
Finished Sep 04 05:07:30 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281181363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2281181363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/136.edn_alert.1314436979
Short name T762
Test name
Test status
Simulation time 53321439 ps
CPU time 1.69 seconds
Started Sep 04 05:07:26 AM UTC 24
Finished Sep 04 05:07:29 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314436979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.1314436979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/136.edn_genbits.1058559235
Short name T761
Test name
Test status
Simulation time 56976606 ps
CPU time 1.45 seconds
Started Sep 04 05:07:26 AM UTC 24
Finished Sep 04 05:07:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058559235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1058559235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/137.edn_alert.2371920135
Short name T261
Test name
Test status
Simulation time 30352062 ps
CPU time 1.92 seconds
Started Sep 04 05:07:27 AM UTC 24
Finished Sep 04 05:07:30 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371920135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.2371920135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/137.edn_genbits.2907551853
Short name T764
Test name
Test status
Simulation time 37322592 ps
CPU time 1.88 seconds
Started Sep 04 05:07:27 AM UTC 24
Finished Sep 04 05:07:30 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907551853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2907551853
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/138.edn_alert.1211353023
Short name T767
Test name
Test status
Simulation time 46398826 ps
CPU time 1.65 seconds
Started Sep 04 05:07:29 AM UTC 24
Finished Sep 04 05:07:31 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211353023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.1211353023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/138.edn_genbits.3835369083
Short name T765
Test name
Test status
Simulation time 74570751 ps
CPU time 1.97 seconds
Started Sep 04 05:07:27 AM UTC 24
Finished Sep 04 05:07:31 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835369083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3835369083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/139.edn_alert.787735833
Short name T768
Test name
Test status
Simulation time 46186299 ps
CPU time 1.61 seconds
Started Sep 04 05:07:29 AM UTC 24
Finished Sep 04 05:07:31 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787735833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 139.edn_alert.787735833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/139.edn_genbits.2952265916
Short name T766
Test name
Test status
Simulation time 29609137 ps
CPU time 1.39 seconds
Started Sep 04 05:07:29 AM UTC 24
Finished Sep 04 05:07:31 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952265916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2952265916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_alert.425326417
Short name T111
Test name
Test status
Simulation time 46897737 ps
CPU time 1.33 seconds
Started Sep 04 05:01:04 AM UTC 24
Finished Sep 04 05:01:06 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425326417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.edn_alert.425326417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_alert_test.3625895943
Short name T375
Test name
Test status
Simulation time 16894523 ps
CPU time 1.07 seconds
Started Sep 04 05:01:05 AM UTC 24
Finished Sep 04 05:01:07 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625895943 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3625895943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.2485502484
Short name T374
Test name
Test status
Simulation time 180981897 ps
CPU time 1.59 seconds
Started Sep 04 05:01:04 AM UTC 24
Finished Sep 04 05:01:07 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485502484 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.2485502484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_err.1878978695
Short name T373
Test name
Test status
Simulation time 68509879 ps
CPU time 1.45 seconds
Started Sep 04 05:01:04 AM UTC 24
Finished Sep 04 05:01:07 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878978695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.1878978695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_genbits.1113712624
Short name T340
Test name
Test status
Simulation time 46137850 ps
CPU time 1.72 seconds
Started Sep 04 05:01:01 AM UTC 24
Finished Sep 04 05:01:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113712624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1113712624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_intr.2448121860
Short name T372
Test name
Test status
Simulation time 33520251 ps
CPU time 1.53 seconds
Started Sep 04 05:01:02 AM UTC 24
Finished Sep 04 05:01:04 AM UTC 24
Peak memory 236704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448121860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.2448121860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_smoke.937387019
Short name T370
Test name
Test status
Simulation time 62433880 ps
CPU time 1.5 seconds
Started Sep 04 05:01:01 AM UTC 24
Finished Sep 04 05:01:03 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937387019 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.edn_smoke.937387019
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.2127947654
Short name T226
Test name
Test status
Simulation time 18056311698 ps
CPU time 102.44 seconds
Started Sep 04 05:01:02 AM UTC 24
Finished Sep 04 05:02:47 AM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2127947654 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all
_with_rand_reset.2127947654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/140.edn_alert.1237823519
Short name T771
Test name
Test status
Simulation time 26894490 ps
CPU time 1.87 seconds
Started Sep 04 05:07:30 AM UTC 24
Finished Sep 04 05:07:33 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237823519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.1237823519
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/140.edn_genbits.2943467258
Short name T769
Test name
Test status
Simulation time 105638163 ps
CPU time 1.73 seconds
Started Sep 04 05:07:29 AM UTC 24
Finished Sep 04 05:07:32 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943467258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2943467258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/141.edn_alert.3069467182
Short name T770
Test name
Test status
Simulation time 83169982 ps
CPU time 1.73 seconds
Started Sep 04 05:07:30 AM UTC 24
Finished Sep 04 05:07:33 AM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069467182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 141.edn_alert.3069467182
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/141.edn_genbits.756617175
Short name T772
Test name
Test status
Simulation time 41639960 ps
CPU time 2.43 seconds
Started Sep 04 05:07:30 AM UTC 24
Finished Sep 04 05:07:33 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756617175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 141.edn_genbits.756617175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/142.edn_alert.2851957611
Short name T775
Test name
Test status
Simulation time 42817873 ps
CPU time 1.8 seconds
Started Sep 04 05:07:31 AM UTC 24
Finished Sep 04 05:07:34 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851957611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.2851957611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/142.edn_genbits.216437821
Short name T773
Test name
Test status
Simulation time 70686524 ps
CPU time 2.69 seconds
Started Sep 04 05:07:30 AM UTC 24
Finished Sep 04 05:07:34 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216437821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 142.edn_genbits.216437821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/143.edn_alert.3846419181
Short name T776
Test name
Test status
Simulation time 90526422 ps
CPU time 1.74 seconds
Started Sep 04 05:07:31 AM UTC 24
Finished Sep 04 05:07:34 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846419181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.3846419181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/144.edn_alert.563702502
Short name T778
Test name
Test status
Simulation time 49020347 ps
CPU time 1.79 seconds
Started Sep 04 05:07:32 AM UTC 24
Finished Sep 04 05:07:35 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563702502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 144.edn_alert.563702502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/145.edn_alert.476623752
Short name T777
Test name
Test status
Simulation time 67276955 ps
CPU time 1.27 seconds
Started Sep 04 05:07:32 AM UTC 24
Finished Sep 04 05:07:35 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476623752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 145.edn_alert.476623752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/145.edn_genbits.4271088236
Short name T779
Test name
Test status
Simulation time 146003616 ps
CPU time 1.96 seconds
Started Sep 04 05:07:32 AM UTC 24
Finished Sep 04 05:07:35 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271088236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4271088236
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/146.edn_alert.2801821132
Short name T781
Test name
Test status
Simulation time 141762154 ps
CPU time 1.69 seconds
Started Sep 04 05:07:33 AM UTC 24
Finished Sep 04 05:07:36 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801821132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.2801821132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/146.edn_genbits.3640342700
Short name T780
Test name
Test status
Simulation time 38015556 ps
CPU time 1.89 seconds
Started Sep 04 05:07:32 AM UTC 24
Finished Sep 04 05:07:35 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640342700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3640342700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/147.edn_alert.418872668
Short name T785
Test name
Test status
Simulation time 69150719 ps
CPU time 1.63 seconds
Started Sep 04 05:07:35 AM UTC 24
Finished Sep 04 05:07:37 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418872668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 147.edn_alert.418872668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/147.edn_genbits.460905419
Short name T782
Test name
Test status
Simulation time 48562414 ps
CPU time 1.7 seconds
Started Sep 04 05:07:33 AM UTC 24
Finished Sep 04 05:07:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460905419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 147.edn_genbits.460905419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/148.edn_alert.3008498181
Short name T786
Test name
Test status
Simulation time 22060049 ps
CPU time 1.42 seconds
Started Sep 04 05:07:35 AM UTC 24
Finished Sep 04 05:07:37 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008498181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.3008498181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/148.edn_genbits.1385556230
Short name T787
Test name
Test status
Simulation time 101310507 ps
CPU time 1.71 seconds
Started Sep 04 05:07:35 AM UTC 24
Finished Sep 04 05:07:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385556230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1385556230
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/149.edn_alert.3574332102
Short name T784
Test name
Test status
Simulation time 52201787 ps
CPU time 1.46 seconds
Started Sep 04 05:07:35 AM UTC 24
Finished Sep 04 05:07:37 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574332102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.3574332102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/149.edn_genbits.2163407888
Short name T783
Test name
Test status
Simulation time 83751058 ps
CPU time 1.16 seconds
Started Sep 04 05:07:35 AM UTC 24
Finished Sep 04 05:07:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163407888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2163407888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_alert_test.3683394656
Short name T380
Test name
Test status
Simulation time 23781304 ps
CPU time 1.25 seconds
Started Sep 04 05:01:12 AM UTC 24
Finished Sep 04 05:01:14 AM UTC 24
Peak memory 217092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683394656 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3683394656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_disable.1857137962
Short name T77
Test name
Test status
Simulation time 44208006 ps
CPU time 1.22 seconds
Started Sep 04 05:01:11 AM UTC 24
Finished Sep 04 05:01:13 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857137962 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1857137962
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.56749952
Short name T381
Test name
Test status
Simulation time 44088598 ps
CPU time 1.89 seconds
Started Sep 04 05:01:12 AM UTC 24
Finished Sep 04 05:01:15 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56749952 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.56749952
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_err.2925023795
Short name T165
Test name
Test status
Simulation time 30144985 ps
CPU time 1.74 seconds
Started Sep 04 05:01:11 AM UTC 24
Finished Sep 04 05:01:13 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925023795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_err.2925023795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_genbits.4268512574
Short name T379
Test name
Test status
Simulation time 83409374 ps
CPU time 4.39 seconds
Started Sep 04 05:01:07 AM UTC 24
Finished Sep 04 05:01:13 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268512574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4268512574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_intr.1666462151
Short name T378
Test name
Test status
Simulation time 30385666 ps
CPU time 1.59 seconds
Started Sep 04 05:01:09 AM UTC 24
Finished Sep 04 05:01:11 AM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666462151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.1666462151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_smoke.2741174351
Short name T376
Test name
Test status
Simulation time 16955764 ps
CPU time 1.22 seconds
Started Sep 04 05:01:07 AM UTC 24
Finished Sep 04 05:01:10 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741174351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.2741174351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_stress_all.1734954145
Short name T377
Test name
Test status
Simulation time 23193386 ps
CPU time 1.44 seconds
Started Sep 04 05:01:07 AM UTC 24
Finished Sep 04 05:01:10 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734954145 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1734954145
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.845144693
Short name T431
Test name
Test status
Simulation time 3977375175 ps
CPU time 98.63 seconds
Started Sep 04 05:01:08 AM UTC 24
Finished Sep 04 05:02:48 AM UTC 24
Peak memory 234016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=845144693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_
with_rand_reset.845144693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/150.edn_alert.802006046
Short name T789
Test name
Test status
Simulation time 44472046 ps
CPU time 1.74 seconds
Started Sep 04 05:07:36 AM UTC 24
Finished Sep 04 05:07:39 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802006046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 150.edn_alert.802006046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/150.edn_genbits.4132911239
Short name T788
Test name
Test status
Simulation time 69497926 ps
CPU time 1.85 seconds
Started Sep 04 05:07:35 AM UTC 24
Finished Sep 04 05:07:38 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132911239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4132911239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/151.edn_alert.1719843152
Short name T790
Test name
Test status
Simulation time 73006724 ps
CPU time 1.7 seconds
Started Sep 04 05:07:36 AM UTC 24
Finished Sep 04 05:07:39 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719843152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.1719843152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/152.edn_alert.2058576659
Short name T792
Test name
Test status
Simulation time 21743371 ps
CPU time 1.26 seconds
Started Sep 04 05:07:37 AM UTC 24
Finished Sep 04 05:07:39 AM UTC 24
Peak memory 230160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058576659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.2058576659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/152.edn_genbits.2520929460
Short name T791
Test name
Test status
Simulation time 38678579 ps
CPU time 1.59 seconds
Started Sep 04 05:07:36 AM UTC 24
Finished Sep 04 05:07:39 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520929460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2520929460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/153.edn_alert.1896782043
Short name T796
Test name
Test status
Simulation time 35233968 ps
CPU time 1.64 seconds
Started Sep 04 05:07:38 AM UTC 24
Finished Sep 04 05:07:41 AM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896782043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.1896782043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/153.edn_genbits.141269886
Short name T793
Test name
Test status
Simulation time 106789202 ps
CPU time 1.96 seconds
Started Sep 04 05:07:37 AM UTC 24
Finished Sep 04 05:07:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141269886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 153.edn_genbits.141269886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/154.edn_alert.1611686191
Short name T795
Test name
Test status
Simulation time 27937086 ps
CPU time 1.59 seconds
Started Sep 04 05:07:38 AM UTC 24
Finished Sep 04 05:07:41 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611686191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 154.edn_alert.1611686191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/154.edn_genbits.389884603
Short name T797
Test name
Test status
Simulation time 38675907 ps
CPU time 1.78 seconds
Started Sep 04 05:07:38 AM UTC 24
Finished Sep 04 05:07:41 AM UTC 24
Peak memory 228192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389884603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 154.edn_genbits.389884603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/155.edn_genbits.2573058262
Short name T798
Test name
Test status
Simulation time 27096248 ps
CPU time 1.7 seconds
Started Sep 04 05:07:38 AM UTC 24
Finished Sep 04 05:07:41 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573058262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2573058262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/156.edn_alert.3124271033
Short name T799
Test name
Test status
Simulation time 127023380 ps
CPU time 1.31 seconds
Started Sep 04 05:07:39 AM UTC 24
Finished Sep 04 05:07:42 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124271033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.3124271033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/156.edn_genbits.2911438857
Short name T794
Test name
Test status
Simulation time 62973552 ps
CPU time 1.37 seconds
Started Sep 04 05:07:38 AM UTC 24
Finished Sep 04 05:07:41 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911438857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2911438857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/157.edn_genbits.3275914216
Short name T800
Test name
Test status
Simulation time 96774243 ps
CPU time 1.41 seconds
Started Sep 04 05:07:40 AM UTC 24
Finished Sep 04 05:07:42 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275914216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3275914216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/158.edn_alert.1015285681
Short name T804
Test name
Test status
Simulation time 43513814 ps
CPU time 1.58 seconds
Started Sep 04 05:07:41 AM UTC 24
Finished Sep 04 05:07:43 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015285681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.1015285681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/158.edn_genbits.1064519470
Short name T801
Test name
Test status
Simulation time 62705661 ps
CPU time 1.45 seconds
Started Sep 04 05:07:40 AM UTC 24
Finished Sep 04 05:07:42 AM UTC 24
Peak memory 226244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064519470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1064519470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/159.edn_alert.1663533472
Short name T806
Test name
Test status
Simulation time 38899253 ps
CPU time 1.74 seconds
Started Sep 04 05:07:42 AM UTC 24
Finished Sep 04 05:07:45 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663533472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 159.edn_alert.1663533472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/159.edn_genbits.3321955085
Short name T803
Test name
Test status
Simulation time 34660695 ps
CPU time 1.14 seconds
Started Sep 04 05:07:41 AM UTC 24
Finished Sep 04 05:07:43 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321955085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3321955085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_alert.2612276004
Short name T84
Test name
Test status
Simulation time 27240617 ps
CPU time 1.72 seconds
Started Sep 04 05:01:17 AM UTC 24
Finished Sep 04 05:01:20 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612276004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.2612276004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_alert_test.1215980208
Short name T384
Test name
Test status
Simulation time 19381708 ps
CPU time 1.37 seconds
Started Sep 04 05:01:20 AM UTC 24
Finished Sep 04 05:01:22 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215980208 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1215980208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_disable.3623713393
Short name T383
Test name
Test status
Simulation time 13470559 ps
CPU time 1.35 seconds
Started Sep 04 05:01:19 AM UTC 24
Finished Sep 04 05:01:21 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623713393 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3623713393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_genbits.2688093838
Short name T291
Test name
Test status
Simulation time 33651841 ps
CPU time 2.08 seconds
Started Sep 04 05:01:14 AM UTC 24
Finished Sep 04 05:01:17 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688093838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2688093838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_smoke.1715636741
Short name T382
Test name
Test status
Simulation time 28012737 ps
CPU time 1.46 seconds
Started Sep 04 05:01:14 AM UTC 24
Finished Sep 04 05:01:17 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715636741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.1715636741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_stress_all.3562338715
Short name T312
Test name
Test status
Simulation time 261665534 ps
CPU time 4.28 seconds
Started Sep 04 05:01:14 AM UTC 24
Finished Sep 04 05:01:19 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562338715 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3562338715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/16.edn_stress_all_with_rand_reset.3879904512
Short name T464
Test name
Test status
Simulation time 5074286273 ps
CPU time 126.8 seconds
Started Sep 04 05:01:15 AM UTC 24
Finished Sep 04 05:03:24 AM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3879904512 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all
_with_rand_reset.3879904512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/16.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/160.edn_genbits.3167541303
Short name T810
Test name
Test status
Simulation time 35764751 ps
CPU time 2.35 seconds
Started Sep 04 05:07:42 AM UTC 24
Finished Sep 04 05:07:45 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167541303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3167541303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/161.edn_alert.969841088
Short name T805
Test name
Test status
Simulation time 43045813 ps
CPU time 1.49 seconds
Started Sep 04 05:07:42 AM UTC 24
Finished Sep 04 05:07:45 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969841088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 161.edn_alert.969841088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/161.edn_genbits.472569053
Short name T809
Test name
Test status
Simulation time 49613627 ps
CPU time 2.05 seconds
Started Sep 04 05:07:42 AM UTC 24
Finished Sep 04 05:07:45 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472569053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.edn_genbits.472569053
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/162.edn_alert.1310120143
Short name T811
Test name
Test status
Simulation time 90990533 ps
CPU time 1.69 seconds
Started Sep 04 05:07:43 AM UTC 24
Finished Sep 04 05:07:46 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310120143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 162.edn_alert.1310120143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/162.edn_genbits.121080155
Short name T807
Test name
Test status
Simulation time 55252209 ps
CPU time 1.55 seconds
Started Sep 04 05:07:42 AM UTC 24
Finished Sep 04 05:07:45 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121080155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 162.edn_genbits.121080155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/163.edn_alert.3083933578
Short name T813
Test name
Test status
Simulation time 97187735 ps
CPU time 1.66 seconds
Started Sep 04 05:07:43 AM UTC 24
Finished Sep 04 05:07:46 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083933578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.3083933578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/164.edn_alert.1472924467
Short name T812
Test name
Test status
Simulation time 48703410 ps
CPU time 1.57 seconds
Started Sep 04 05:07:43 AM UTC 24
Finished Sep 04 05:07:46 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472924467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.1472924467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/164.edn_genbits.760181109
Short name T337
Test name
Test status
Simulation time 75814029 ps
CPU time 1.76 seconds
Started Sep 04 05:07:43 AM UTC 24
Finished Sep 04 05:07:47 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760181109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 164.edn_genbits.760181109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/165.edn_alert.1416457074
Short name T756
Test name
Test status
Simulation time 78741452 ps
CPU time 1.78 seconds
Started Sep 04 05:07:45 AM UTC 24
Finished Sep 04 05:07:49 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416457074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.1416457074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/165.edn_genbits.388886837
Short name T755
Test name
Test status
Simulation time 39421985 ps
CPU time 1.72 seconds
Started Sep 04 05:07:44 AM UTC 24
Finished Sep 04 05:07:48 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388886837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 165.edn_genbits.388886837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/166.edn_alert.2683236527
Short name T748
Test name
Test status
Simulation time 47563286 ps
CPU time 1.64 seconds
Started Sep 04 05:07:46 AM UTC 24
Finished Sep 04 05:07:49 AM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683236527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.2683236527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/166.edn_genbits.3298972707
Short name T740
Test name
Test status
Simulation time 29968051 ps
CPU time 1.67 seconds
Started Sep 04 05:07:46 AM UTC 24
Finished Sep 04 05:07:49 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298972707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3298972707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/167.edn_alert.532412695
Short name T650
Test name
Test status
Simulation time 26009831 ps
CPU time 1.66 seconds
Started Sep 04 05:07:46 AM UTC 24
Finished Sep 04 05:07:49 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532412695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 167.edn_alert.532412695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/167.edn_genbits.1177801198
Short name T814
Test name
Test status
Simulation time 84411789 ps
CPU time 1.33 seconds
Started Sep 04 05:07:46 AM UTC 24
Finished Sep 04 05:07:48 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177801198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1177801198
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/168.edn_alert.673309102
Short name T815
Test name
Test status
Simulation time 35300508 ps
CPU time 1.66 seconds
Started Sep 04 05:07:47 AM UTC 24
Finished Sep 04 05:07:50 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673309102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 168.edn_alert.673309102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/168.edn_genbits.3927047012
Short name T718
Test name
Test status
Simulation time 102537195 ps
CPU time 1.58 seconds
Started Sep 04 05:07:47 AM UTC 24
Finished Sep 04 05:07:50 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927047012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3927047012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/169.edn_alert.2862892100
Short name T194
Test name
Test status
Simulation time 70572869 ps
CPU time 1.47 seconds
Started Sep 04 05:07:47 AM UTC 24
Finished Sep 04 05:07:49 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862892100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.2862892100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/169.edn_genbits.929833247
Short name T816
Test name
Test status
Simulation time 72469941 ps
CPU time 1.78 seconds
Started Sep 04 05:07:47 AM UTC 24
Finished Sep 04 05:07:50 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929833247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.edn_genbits.929833247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_alert.832811377
Short name T162
Test name
Test status
Simulation time 36562339 ps
CPU time 1.33 seconds
Started Sep 04 05:01:23 AM UTC 24
Finished Sep 04 05:01:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832811377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.edn_alert.832811377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_alert_test.452004877
Short name T389
Test name
Test status
Simulation time 194347613 ps
CPU time 1.93 seconds
Started Sep 04 05:01:26 AM UTC 24
Finished Sep 04 05:01:30 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452004877 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.452004877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_disable.2999444027
Short name T387
Test name
Test status
Simulation time 62528220 ps
CPU time 1.27 seconds
Started Sep 04 05:01:24 AM UTC 24
Finished Sep 04 05:01:27 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999444027 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2999444027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_err.3166490492
Short name T218
Test name
Test status
Simulation time 38984516 ps
CPU time 1.13 seconds
Started Sep 04 05:01:23 AM UTC 24
Finished Sep 04 05:01:25 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166490492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.3166490492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_smoke.959311701
Short name T385
Test name
Test status
Simulation time 20877929 ps
CPU time 1.43 seconds
Started Sep 04 05:01:20 AM UTC 24
Finished Sep 04 05:01:22 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959311701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.edn_smoke.959311701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/17.edn_stress_all.2001305821
Short name T386
Test name
Test status
Simulation time 208670922 ps
CPU time 2.29 seconds
Started Sep 04 05:01:22 AM UTC 24
Finished Sep 04 05:01:25 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001305821 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2001305821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/170.edn_alert.1166889454
Short name T818
Test name
Test status
Simulation time 50649902 ps
CPU time 1.92 seconds
Started Sep 04 05:07:48 AM UTC 24
Finished Sep 04 05:07:51 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166889454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.1166889454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/170.edn_genbits.1606690024
Short name T817
Test name
Test status
Simulation time 72197729 ps
CPU time 2.49 seconds
Started Sep 04 05:07:47 AM UTC 24
Finished Sep 04 05:07:51 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606690024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1606690024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/171.edn_alert.478338393
Short name T822
Test name
Test status
Simulation time 27840547 ps
CPU time 1.84 seconds
Started Sep 04 05:07:49 AM UTC 24
Finished Sep 04 05:07:52 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478338393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 171.edn_alert.478338393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/171.edn_genbits.3736067507
Short name T821
Test name
Test status
Simulation time 34253909 ps
CPU time 1.69 seconds
Started Sep 04 05:07:49 AM UTC 24
Finished Sep 04 05:07:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736067507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3736067507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/172.edn_alert.2192474590
Short name T819
Test name
Test status
Simulation time 126582853 ps
CPU time 1.47 seconds
Started Sep 04 05:07:49 AM UTC 24
Finished Sep 04 05:07:52 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192474590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.2192474590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/172.edn_genbits.3585723644
Short name T823
Test name
Test status
Simulation time 55713450 ps
CPU time 1.87 seconds
Started Sep 04 05:07:49 AM UTC 24
Finished Sep 04 05:07:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585723644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3585723644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/173.edn_alert.2129894387
Short name T824
Test name
Test status
Simulation time 28690585 ps
CPU time 1.8 seconds
Started Sep 04 05:07:49 AM UTC 24
Finished Sep 04 05:07:52 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129894387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.2129894387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/173.edn_genbits.1516185386
Short name T820
Test name
Test status
Simulation time 100501745 ps
CPU time 1.57 seconds
Started Sep 04 05:07:49 AM UTC 24
Finished Sep 04 05:07:52 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516185386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1516185386
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/174.edn_alert.1292705058
Short name T826
Test name
Test status
Simulation time 69479215 ps
CPU time 1.59 seconds
Started Sep 04 05:07:50 AM UTC 24
Finished Sep 04 05:07:53 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292705058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.1292705058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/174.edn_genbits.806739589
Short name T825
Test name
Test status
Simulation time 65893248 ps
CPU time 1.31 seconds
Started Sep 04 05:07:50 AM UTC 24
Finished Sep 04 05:07:53 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806739589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 174.edn_genbits.806739589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/175.edn_alert.1673961359
Short name T827
Test name
Test status
Simulation time 105730200 ps
CPU time 1.89 seconds
Started Sep 04 05:07:51 AM UTC 24
Finished Sep 04 05:07:53 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673961359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.1673961359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/175.edn_genbits.1943596614
Short name T321
Test name
Test status
Simulation time 95351832 ps
CPU time 1.71 seconds
Started Sep 04 05:07:50 AM UTC 24
Finished Sep 04 05:07:53 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943596614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1943596614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/176.edn_alert.2393460399
Short name T829
Test name
Test status
Simulation time 48239848 ps
CPU time 1.83 seconds
Started Sep 04 05:07:52 AM UTC 24
Finished Sep 04 05:07:55 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393460399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.2393460399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/176.edn_genbits.1364579597
Short name T828
Test name
Test status
Simulation time 43325257 ps
CPU time 1.48 seconds
Started Sep 04 05:07:52 AM UTC 24
Finished Sep 04 05:07:54 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364579597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1364579597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/177.edn_alert.816089397
Short name T831
Test name
Test status
Simulation time 87128244 ps
CPU time 1.73 seconds
Started Sep 04 05:07:53 AM UTC 24
Finished Sep 04 05:07:55 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816089397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 177.edn_alert.816089397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/177.edn_genbits.1466705512
Short name T830
Test name
Test status
Simulation time 59283756 ps
CPU time 1.62 seconds
Started Sep 04 05:07:53 AM UTC 24
Finished Sep 04 05:07:55 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466705512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1466705512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/178.edn_alert.4260279013
Short name T833
Test name
Test status
Simulation time 31969313 ps
CPU time 1.77 seconds
Started Sep 04 05:07:53 AM UTC 24
Finished Sep 04 05:07:56 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260279013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.4260279013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/178.edn_genbits.2496907740
Short name T835
Test name
Test status
Simulation time 49751516 ps
CPU time 2.33 seconds
Started Sep 04 05:07:53 AM UTC 24
Finished Sep 04 05:07:56 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496907740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2496907740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/179.edn_alert.2894620986
Short name T834
Test name
Test status
Simulation time 23387699 ps
CPU time 1.7 seconds
Started Sep 04 05:07:53 AM UTC 24
Finished Sep 04 05:07:56 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894620986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 179.edn_alert.2894620986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/179.edn_genbits.3842418574
Short name T832
Test name
Test status
Simulation time 91226748 ps
CPU time 1.68 seconds
Started Sep 04 05:07:53 AM UTC 24
Finished Sep 04 05:07:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842418574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3842418574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_alert_test.66943642
Short name T392
Test name
Test status
Simulation time 80739327 ps
CPU time 1.16 seconds
Started Sep 04 05:01:34 AM UTC 24
Finished Sep 04 05:01:36 AM UTC 24
Peak memory 217168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66943642 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.66943642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_disable.2899861850
Short name T391
Test name
Test status
Simulation time 10821827 ps
CPU time 1.27 seconds
Started Sep 04 05:01:33 AM UTC 24
Finished Sep 04 05:01:35 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899861850 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2899861850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.2871012040
Short name T130
Test name
Test status
Simulation time 112219273 ps
CPU time 1.78 seconds
Started Sep 04 05:01:34 AM UTC 24
Finished Sep 04 05:01:37 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871012040 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.2871012040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_err.2092041740
Short name T208
Test name
Test status
Simulation time 56409916 ps
CPU time 1.28 seconds
Started Sep 04 05:01:31 AM UTC 24
Finished Sep 04 05:01:33 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092041740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.2092041740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_genbits.779698881
Short name T288
Test name
Test status
Simulation time 37832790 ps
CPU time 1.95 seconds
Started Sep 04 05:01:27 AM UTC 24
Finished Sep 04 05:01:30 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779698881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_genbits.779698881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_intr.1552401736
Short name T390
Test name
Test status
Simulation time 25312668 ps
CPU time 1.65 seconds
Started Sep 04 05:01:30 AM UTC 24
Finished Sep 04 05:01:33 AM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552401736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.1552401736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_smoke.4067424709
Short name T388
Test name
Test status
Simulation time 17507469 ps
CPU time 1.4 seconds
Started Sep 04 05:01:27 AM UTC 24
Finished Sep 04 05:01:29 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067424709 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.4067424709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.3943894507
Short name T485
Test name
Test status
Simulation time 22639914131 ps
CPU time 136.6 seconds
Started Sep 04 05:01:29 AM UTC 24
Finished Sep 04 05:03:48 AM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3943894507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all
_with_rand_reset.3943894507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/180.edn_alert.2016802013
Short name T837
Test name
Test status
Simulation time 43530545 ps
CPU time 1.78 seconds
Started Sep 04 05:07:54 AM UTC 24
Finished Sep 04 05:07:57 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016802013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.edn_alert.2016802013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/180.edn_genbits.4042394897
Short name T839
Test name
Test status
Simulation time 39530612 ps
CPU time 2.42 seconds
Started Sep 04 05:07:54 AM UTC 24
Finished Sep 04 05:07:58 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042394897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4042394897
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/181.edn_alert.1324295983
Short name T838
Test name
Test status
Simulation time 96408566 ps
CPU time 1.68 seconds
Started Sep 04 05:07:54 AM UTC 24
Finished Sep 04 05:07:57 AM UTC 24
Peak memory 232064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324295983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 181.edn_alert.1324295983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/181.edn_genbits.3124685773
Short name T836
Test name
Test status
Simulation time 38456747 ps
CPU time 1.54 seconds
Started Sep 04 05:07:54 AM UTC 24
Finished Sep 04 05:07:57 AM UTC 24
Peak memory 228164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124685773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3124685773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/182.edn_alert.3319595051
Short name T841
Test name
Test status
Simulation time 28203235 ps
CPU time 1.84 seconds
Started Sep 04 05:07:55 AM UTC 24
Finished Sep 04 05:07:58 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319595051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.3319595051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/182.edn_genbits.745472090
Short name T840
Test name
Test status
Simulation time 73472757 ps
CPU time 1.74 seconds
Started Sep 04 05:07:55 AM UTC 24
Finished Sep 04 05:07:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745472090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.edn_genbits.745472090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/183.edn_alert.3675547284
Short name T842
Test name
Test status
Simulation time 25140940 ps
CPU time 1.72 seconds
Started Sep 04 05:07:56 AM UTC 24
Finished Sep 04 05:07:59 AM UTC 24
Peak memory 230340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675547284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.3675547284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/183.edn_genbits.3595221650
Short name T843
Test name
Test status
Simulation time 45505211 ps
CPU time 1.96 seconds
Started Sep 04 05:07:56 AM UTC 24
Finished Sep 04 05:07:59 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595221650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3595221650
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/184.edn_alert.2542579362
Short name T844
Test name
Test status
Simulation time 88265292 ps
CPU time 1.6 seconds
Started Sep 04 05:07:57 AM UTC 24
Finished Sep 04 05:07:59 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542579362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.2542579362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/184.edn_genbits.2474991256
Short name T845
Test name
Test status
Simulation time 37379807 ps
CPU time 2.23 seconds
Started Sep 04 05:07:56 AM UTC 24
Finished Sep 04 05:08:00 AM UTC 24
Peak memory 231488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474991256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2474991256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/185.edn_alert.1170089512
Short name T849
Test name
Test status
Simulation time 66819075 ps
CPU time 1.67 seconds
Started Sep 04 05:07:58 AM UTC 24
Finished Sep 04 05:08:00 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170089512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 185.edn_alert.1170089512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/185.edn_genbits.3808278942
Short name T847
Test name
Test status
Simulation time 69204021 ps
CPU time 2.44 seconds
Started Sep 04 05:07:57 AM UTC 24
Finished Sep 04 05:08:00 AM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808278942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3808278942
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/186.edn_alert.1271628335
Short name T850
Test name
Test status
Simulation time 305144718 ps
CPU time 1.65 seconds
Started Sep 04 05:07:58 AM UTC 24
Finished Sep 04 05:08:01 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271628335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.1271628335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/186.edn_genbits.3489972142
Short name T846
Test name
Test status
Simulation time 46087043 ps
CPU time 1.54 seconds
Started Sep 04 05:07:58 AM UTC 24
Finished Sep 04 05:08:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489972142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3489972142
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/187.edn_alert.451696155
Short name T852
Test name
Test status
Simulation time 87304479 ps
CPU time 1.82 seconds
Started Sep 04 05:07:59 AM UTC 24
Finished Sep 04 05:08:02 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451696155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 187.edn_alert.451696155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/187.edn_genbits.3355804210
Short name T848
Test name
Test status
Simulation time 67985194 ps
CPU time 1.52 seconds
Started Sep 04 05:07:58 AM UTC 24
Finished Sep 04 05:08:00 AM UTC 24
Peak memory 230688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355804210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3355804210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/188.edn_alert.2035492031
Short name T851
Test name
Test status
Simulation time 74154894 ps
CPU time 1.58 seconds
Started Sep 04 05:07:59 AM UTC 24
Finished Sep 04 05:08:02 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035492031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.2035492031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/188.edn_genbits.2503273977
Short name T853
Test name
Test status
Simulation time 68126067 ps
CPU time 2.04 seconds
Started Sep 04 05:07:59 AM UTC 24
Finished Sep 04 05:08:02 AM UTC 24
Peak memory 229348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503273977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2503273977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/189.edn_alert.2390637410
Short name T854
Test name
Test status
Simulation time 152216100 ps
CPU time 1.74 seconds
Started Sep 04 05:08:00 AM UTC 24
Finished Sep 04 05:08:03 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390637410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.2390637410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/189.edn_genbits.1537230277
Short name T856
Test name
Test status
Simulation time 298790346 ps
CPU time 2.79 seconds
Started Sep 04 05:08:00 AM UTC 24
Finished Sep 04 05:08:04 AM UTC 24
Peak memory 231468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537230277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1537230277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_alert_test.1374993195
Short name T395
Test name
Test status
Simulation time 14165991 ps
CPU time 1.36 seconds
Started Sep 04 05:01:45 AM UTC 24
Finished Sep 04 05:01:47 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374993195 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1374993195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.111880939
Short name T394
Test name
Test status
Simulation time 130833600 ps
CPU time 1.84 seconds
Started Sep 04 05:01:44 AM UTC 24
Finished Sep 04 05:01:47 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111880939 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.111880939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_err.3085752274
Short name T143
Test name
Test status
Simulation time 49213756 ps
CPU time 1.62 seconds
Started Sep 04 05:01:42 AM UTC 24
Finished Sep 04 05:01:44 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085752274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.3085752274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_genbits.3940179527
Short name T292
Test name
Test status
Simulation time 86127973 ps
CPU time 1.8 seconds
Started Sep 04 05:01:36 AM UTC 24
Finished Sep 04 05:01:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940179527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3940179527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_smoke.4254951683
Short name T393
Test name
Test status
Simulation time 43853249 ps
CPU time 1.35 seconds
Started Sep 04 05:01:35 AM UTC 24
Finished Sep 04 05:01:38 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254951683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_smoke.4254951683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/19.edn_stress_all.911963469
Short name T244
Test name
Test status
Simulation time 178515162 ps
CPU time 4.28 seconds
Started Sep 04 05:01:37 AM UTC 24
Finished Sep 04 05:01:43 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911963469 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.911963469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/190.edn_alert.4264208067
Short name T857
Test name
Test status
Simulation time 93798481 ps
CPU time 1.78 seconds
Started Sep 04 05:08:01 AM UTC 24
Finished Sep 04 05:08:04 AM UTC 24
Peak memory 230440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264208067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.4264208067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/190.edn_genbits.3188941
Short name T855
Test name
Test status
Simulation time 32334020 ps
CPU time 1.86 seconds
Started Sep 04 05:08:00 AM UTC 24
Finished Sep 04 05:08:03 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_
genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 190.edn_genbits.3188941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/191.edn_alert.575231121
Short name T858
Test name
Test status
Simulation time 52789430 ps
CPU time 1.81 seconds
Started Sep 04 05:08:01 AM UTC 24
Finished Sep 04 05:08:04 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575231121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 191.edn_alert.575231121
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/191.edn_genbits.2974453348
Short name T859
Test name
Test status
Simulation time 30879752 ps
CPU time 1.83 seconds
Started Sep 04 05:08:01 AM UTC 24
Finished Sep 04 05:08:04 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974453348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2974453348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/192.edn_alert.590858878
Short name T860
Test name
Test status
Simulation time 28836128 ps
CPU time 1.78 seconds
Started Sep 04 05:08:01 AM UTC 24
Finished Sep 04 05:08:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590858878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 192.edn_alert.590858878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/192.edn_genbits.2370198204
Short name T862
Test name
Test status
Simulation time 91920765 ps
CPU time 2.27 seconds
Started Sep 04 05:08:01 AM UTC 24
Finished Sep 04 05:08:05 AM UTC 24
Peak memory 231528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370198204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2370198204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/193.edn_alert.2360534946
Short name T864
Test name
Test status
Simulation time 23106975 ps
CPU time 1.65 seconds
Started Sep 04 05:08:03 AM UTC 24
Finished Sep 04 05:08:05 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360534946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.2360534946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/194.edn_genbits.2062725050
Short name T863
Test name
Test status
Simulation time 172471229 ps
CPU time 1.34 seconds
Started Sep 04 05:08:03 AM UTC 24
Finished Sep 04 05:08:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062725050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2062725050
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/195.edn_alert.4136290354
Short name T865
Test name
Test status
Simulation time 34636124 ps
CPU time 1.2 seconds
Started Sep 04 05:08:04 AM UTC 24
Finished Sep 04 05:08:06 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136290354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 195.edn_alert.4136290354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/196.edn_alert.1115670336
Short name T287
Test name
Test status
Simulation time 45021294 ps
CPU time 1.74 seconds
Started Sep 04 05:08:05 AM UTC 24
Finished Sep 04 05:08:08 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115670336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 196.edn_alert.1115670336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/196.edn_genbits.1083406254
Short name T870
Test name
Test status
Simulation time 44260471 ps
CPU time 2.06 seconds
Started Sep 04 05:08:05 AM UTC 24
Finished Sep 04 05:08:08 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083406254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1083406254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/197.edn_alert.888986254
Short name T867
Test name
Test status
Simulation time 132659797 ps
CPU time 1.61 seconds
Started Sep 04 05:08:05 AM UTC 24
Finished Sep 04 05:08:08 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888986254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 197.edn_alert.888986254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/197.edn_genbits.2825337044
Short name T868
Test name
Test status
Simulation time 60507639 ps
CPU time 1.83 seconds
Started Sep 04 05:08:05 AM UTC 24
Finished Sep 04 05:08:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825337044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2825337044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/198.edn_alert.2686957797
Short name T871
Test name
Test status
Simulation time 41348322 ps
CPU time 1.54 seconds
Started Sep 04 05:08:06 AM UTC 24
Finished Sep 04 05:08:09 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686957797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.2686957797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/199.edn_alert.604360299
Short name T873
Test name
Test status
Simulation time 114093201 ps
CPU time 1.64 seconds
Started Sep 04 05:08:06 AM UTC 24
Finished Sep 04 05:08:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604360299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 199.edn_alert.604360299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/199.edn_genbits.4108819464
Short name T874
Test name
Test status
Simulation time 61660831 ps
CPU time 1.9 seconds
Started Sep 04 05:08:06 AM UTC 24
Finished Sep 04 05:08:09 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108819464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4108819464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_alert.3545839887
Short name T25
Test name
Test status
Simulation time 142085835 ps
CPU time 1.61 seconds
Started Sep 04 04:59:50 AM UTC 24
Finished Sep 04 04:59:52 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545839887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_alert.3545839887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_alert_test.4105930149
Short name T67
Test name
Test status
Simulation time 20093319 ps
CPU time 1.24 seconds
Started Sep 04 04:59:53 AM UTC 24
Finished Sep 04 04:59:55 AM UTC 24
Peak memory 226532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105930149 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.4105930149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_disable.3473804702
Short name T39
Test name
Test status
Simulation time 38652851 ps
CPU time 1.38 seconds
Started Sep 04 04:59:51 AM UTC 24
Finished Sep 04 04:59:53 AM UTC 24
Peak memory 216088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473804702 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3473804702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_err.1023658835
Short name T7
Test name
Test status
Simulation time 25411061 ps
CPU time 1.86 seconds
Started Sep 04 04:59:51 AM UTC 24
Finished Sep 04 04:59:54 AM UTC 24
Peak memory 244156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023658835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.1023658835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_intr.3434064631
Short name T42
Test name
Test status
Simulation time 62430874 ps
CPU time 1.12 seconds
Started Sep 04 04:59:50 AM UTC 24
Finished Sep 04 04:59:52 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434064631 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.3434064631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_regwen.1685308805
Short name T64
Test name
Test status
Simulation time 17755770 ps
CPU time 1.51 seconds
Started Sep 04 04:59:47 AM UTC 24
Finished Sep 04 04:59:50 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685308805 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.1685308805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_sec_cm.1045816003
Short name T58
Test name
Test status
Simulation time 1089503506 ps
CPU time 12.85 seconds
Started Sep 04 04:59:51 AM UTC 24
Finished Sep 04 05:00:05 AM UTC 24
Peak memory 262548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045816003 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1045816003
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_smoke.2610161742
Short name T63
Test name
Test status
Simulation time 20328718 ps
CPU time 1.41 seconds
Started Sep 04 04:59:47 AM UTC 24
Finished Sep 04 04:59:50 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610161742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.2610161742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/2.edn_stress_all.2533475395
Short name T41
Test name
Test status
Simulation time 333599363 ps
CPU time 5.37 seconds
Started Sep 04 04:59:48 AM UTC 24
Finished Sep 04 04:59:55 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533475395 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2533475395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_alert.1486765226
Short name T148
Test name
Test status
Simulation time 38898042 ps
CPU time 1.64 seconds
Started Sep 04 05:01:52 AM UTC 24
Finished Sep 04 05:01:55 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486765226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_alert.1486765226
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_alert_test.3716556710
Short name T400
Test name
Test status
Simulation time 16368611 ps
CPU time 1.36 seconds
Started Sep 04 05:01:58 AM UTC 24
Finished Sep 04 05:02:01 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716556710 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3716556710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_disable.2601903584
Short name T223
Test name
Test status
Simulation time 13908878 ps
CPU time 1.37 seconds
Started Sep 04 05:01:55 AM UTC 24
Finished Sep 04 05:01:58 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601903584 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2601903584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.1094161109
Short name T399
Test name
Test status
Simulation time 54161718 ps
CPU time 1.68 seconds
Started Sep 04 05:01:56 AM UTC 24
Finished Sep 04 05:01:59 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094161109 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.1094161109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_err.28346509
Short name T163
Test name
Test status
Simulation time 68939969 ps
CPU time 1.38 seconds
Started Sep 04 05:01:53 AM UTC 24
Finished Sep 04 05:01:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28346509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 20.edn_err.28346509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_genbits.2190560149
Short name T397
Test name
Test status
Simulation time 35759488 ps
CPU time 1.79 seconds
Started Sep 04 05:01:47 AM UTC 24
Finished Sep 04 05:01:50 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190560149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2190560149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_intr.409578337
Short name T398
Test name
Test status
Simulation time 62539978 ps
CPU time 1.21 seconds
Started Sep 04 05:01:50 AM UTC 24
Finished Sep 04 05:01:52 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409578337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.409578337
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_smoke.1065293030
Short name T396
Test name
Test status
Simulation time 32111190 ps
CPU time 1.49 seconds
Started Sep 04 05:01:46 AM UTC 24
Finished Sep 04 05:01:48 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065293030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_smoke.1065293030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_stress_all.2193416063
Short name T245
Test name
Test status
Simulation time 99835143 ps
CPU time 2.39 seconds
Started Sep 04 05:01:48 AM UTC 24
Finished Sep 04 05:01:51 AM UTC 24
Peak memory 229584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193416063 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2193416063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.2529116479
Short name T205
Test name
Test status
Simulation time 1001877146 ps
CPU time 14.12 seconds
Started Sep 04 05:01:49 AM UTC 24
Finished Sep 04 05:02:04 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2529116479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all
_with_rand_reset.2529116479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/200.edn_genbits.1901358515
Short name T872
Test name
Test status
Simulation time 49739549 ps
CPU time 1.6 seconds
Started Sep 04 05:08:06 AM UTC 24
Finished Sep 04 05:08:09 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901358515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1901358515
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/201.edn_genbits.3622236869
Short name T876
Test name
Test status
Simulation time 80236214 ps
CPU time 1.83 seconds
Started Sep 04 05:08:07 AM UTC 24
Finished Sep 04 05:08:10 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622236869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3622236869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/202.edn_genbits.693203354
Short name T877
Test name
Test status
Simulation time 40260636 ps
CPU time 2.52 seconds
Started Sep 04 05:08:07 AM UTC 24
Finished Sep 04 05:08:11 AM UTC 24
Peak memory 229436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693203354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 202.edn_genbits.693203354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/203.edn_genbits.89571631
Short name T875
Test name
Test status
Simulation time 73275590 ps
CPU time 1.24 seconds
Started Sep 04 05:08:07 AM UTC 24
Finished Sep 04 05:08:10 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89571631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 203.edn_genbits.89571631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/204.edn_genbits.3428151641
Short name T878
Test name
Test status
Simulation time 108087794 ps
CPU time 1.64 seconds
Started Sep 04 05:08:08 AM UTC 24
Finished Sep 04 05:08:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428151641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3428151641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/205.edn_genbits.1219076859
Short name T315
Test name
Test status
Simulation time 34774388 ps
CPU time 1.69 seconds
Started Sep 04 05:08:09 AM UTC 24
Finished Sep 04 05:08:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219076859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1219076859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/206.edn_genbits.2275882783
Short name T334
Test name
Test status
Simulation time 73285613 ps
CPU time 2.16 seconds
Started Sep 04 05:08:09 AM UTC 24
Finished Sep 04 05:08:12 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275882783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2275882783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/207.edn_genbits.2653265397
Short name T879
Test name
Test status
Simulation time 53232945 ps
CPU time 2.02 seconds
Started Sep 04 05:08:09 AM UTC 24
Finished Sep 04 05:08:12 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653265397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2653265397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/208.edn_genbits.320851496
Short name T882
Test name
Test status
Simulation time 84451466 ps
CPU time 1.57 seconds
Started Sep 04 05:08:10 AM UTC 24
Finished Sep 04 05:08:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320851496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 208.edn_genbits.320851496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/209.edn_genbits.2514121588
Short name T881
Test name
Test status
Simulation time 111002404 ps
CPU time 1.47 seconds
Started Sep 04 05:08:10 AM UTC 24
Finished Sep 04 05:08:12 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514121588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2514121588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_alert.217797706
Short name T199
Test name
Test status
Simulation time 61025587 ps
CPU time 1.98 seconds
Started Sep 04 05:02:05 AM UTC 24
Finished Sep 04 05:02:08 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217797706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_alert.217797706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_alert_test.4132157603
Short name T403
Test name
Test status
Simulation time 131696289 ps
CPU time 1.25 seconds
Started Sep 04 05:02:05 AM UTC 24
Finished Sep 04 05:02:07 AM UTC 24
Peak memory 216852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132157603 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4132157603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.128410409
Short name T404
Test name
Test status
Simulation time 27096120 ps
CPU time 1.7 seconds
Started Sep 04 05:02:05 AM UTC 24
Finished Sep 04 05:02:08 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128410409 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.128410409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_err.2930175435
Short name T116
Test name
Test status
Simulation time 29807168 ps
CPU time 1.74 seconds
Started Sep 04 05:02:05 AM UTC 24
Finished Sep 04 05:02:08 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930175435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.2930175435
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_genbits.2067383559
Short name T308
Test name
Test status
Simulation time 102483590 ps
CPU time 3.34 seconds
Started Sep 04 05:02:00 AM UTC 24
Finished Sep 04 05:02:04 AM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067383559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2067383559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_intr.536199165
Short name T402
Test name
Test status
Simulation time 25733685 ps
CPU time 1.57 seconds
Started Sep 04 05:02:02 AM UTC 24
Finished Sep 04 05:02:04 AM UTC 24
Peak memory 237840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536199165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.536199165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_smoke.275248731
Short name T401
Test name
Test status
Simulation time 30663173 ps
CPU time 1.36 seconds
Started Sep 04 05:01:58 AM UTC 24
Finished Sep 04 05:02:01 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275248731 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_smoke.275248731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_stress_all.1914125613
Short name T332
Test name
Test status
Simulation time 94619792 ps
CPU time 1.97 seconds
Started Sep 04 05:02:02 AM UTC 24
Finished Sep 04 05:02:05 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914125613 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1914125613
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.1479723554
Short name T227
Test name
Test status
Simulation time 2313994824 ps
CPU time 44.25 seconds
Started Sep 04 05:02:02 AM UTC 24
Finished Sep 04 05:02:47 AM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1479723554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.1479723554
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/210.edn_genbits.665045708
Short name T883
Test name
Test status
Simulation time 53839938 ps
CPU time 2.33 seconds
Started Sep 04 05:08:10 AM UTC 24
Finished Sep 04 05:08:13 AM UTC 24
Peak memory 229068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665045708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.665045708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/211.edn_genbits.4133773678
Short name T885
Test name
Test status
Simulation time 41588708 ps
CPU time 2.6 seconds
Started Sep 04 05:08:10 AM UTC 24
Finished Sep 04 05:08:14 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133773678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4133773678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/212.edn_genbits.757700849
Short name T880
Test name
Test status
Simulation time 35484662 ps
CPU time 1.26 seconds
Started Sep 04 05:08:10 AM UTC 24
Finished Sep 04 05:08:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757700849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 212.edn_genbits.757700849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/213.edn_genbits.638934189
Short name T884
Test name
Test status
Simulation time 185712460 ps
CPU time 1.23 seconds
Started Sep 04 05:08:11 AM UTC 24
Finished Sep 04 05:08:13 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638934189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 213.edn_genbits.638934189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/214.edn_genbits.3339114807
Short name T886
Test name
Test status
Simulation time 106600772 ps
CPU time 1.53 seconds
Started Sep 04 05:08:11 AM UTC 24
Finished Sep 04 05:08:14 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339114807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3339114807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/215.edn_genbits.578723933
Short name T890
Test name
Test status
Simulation time 117599860 ps
CPU time 2.54 seconds
Started Sep 04 05:08:12 AM UTC 24
Finished Sep 04 05:08:16 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578723933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 215.edn_genbits.578723933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/216.edn_genbits.2807590235
Short name T891
Test name
Test status
Simulation time 121711907 ps
CPU time 2.58 seconds
Started Sep 04 05:08:12 AM UTC 24
Finished Sep 04 05:08:16 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807590235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2807590235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/217.edn_genbits.1666500522
Short name T887
Test name
Test status
Simulation time 52064001 ps
CPU time 1.28 seconds
Started Sep 04 05:08:12 AM UTC 24
Finished Sep 04 05:08:14 AM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666500522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1666500522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/218.edn_genbits.14232184
Short name T889
Test name
Test status
Simulation time 126753028 ps
CPU time 2.06 seconds
Started Sep 04 05:08:12 AM UTC 24
Finished Sep 04 05:08:15 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14232184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 218.edn_genbits.14232184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/219.edn_genbits.2398090594
Short name T888
Test name
Test status
Simulation time 82618378 ps
CPU time 1.56 seconds
Started Sep 04 05:08:12 AM UTC 24
Finished Sep 04 05:08:15 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398090594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2398090594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_alert.2670205899
Short name T124
Test name
Test status
Simulation time 96337182 ps
CPU time 1.89 seconds
Started Sep 04 05:02:12 AM UTC 24
Finished Sep 04 05:02:14 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670205899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.2670205899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_alert_test.1725743359
Short name T410
Test name
Test status
Simulation time 40498270 ps
CPU time 1.6 seconds
Started Sep 04 05:02:15 AM UTC 24
Finished Sep 04 05:02:17 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725743359 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1725743359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_disable.423281545
Short name T219
Test name
Test status
Simulation time 39677538 ps
CPU time 1.25 seconds
Started Sep 04 05:02:13 AM UTC 24
Finished Sep 04 05:02:15 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423281545 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.423281545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.1879943180
Short name T121
Test name
Test status
Simulation time 43573946 ps
CPU time 2.03 seconds
Started Sep 04 05:02:15 AM UTC 24
Finished Sep 04 05:02:18 AM UTC 24
Peak memory 228180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879943180 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.1879943180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_err.3531592257
Short name T407
Test name
Test status
Simulation time 22544827 ps
CPU time 1.28 seconds
Started Sep 04 05:02:12 AM UTC 24
Finished Sep 04 05:02:14 AM UTC 24
Peak memory 228540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531592257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.edn_err.3531592257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_genbits.1589124384
Short name T80
Test name
Test status
Simulation time 81567247 ps
CPU time 2.64 seconds
Started Sep 04 05:02:08 AM UTC 24
Finished Sep 04 05:02:12 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589124384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1589124384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_intr.1840955757
Short name T406
Test name
Test status
Simulation time 36145640 ps
CPU time 1.31 seconds
Started Sep 04 05:02:08 AM UTC 24
Finished Sep 04 05:02:11 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840955757 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.1840955757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_smoke.3535537941
Short name T405
Test name
Test status
Simulation time 40198733 ps
CPU time 1.37 seconds
Started Sep 04 05:02:08 AM UTC 24
Finished Sep 04 05:02:11 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535537941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_smoke.3535537941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/22.edn_stress_all.725041949
Short name T408
Test name
Test status
Simulation time 185609363 ps
CPU time 4.93 seconds
Started Sep 04 05:02:08 AM UTC 24
Finished Sep 04 05:02:14 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725041949 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.725041949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/220.edn_genbits.2514900505
Short name T892
Test name
Test status
Simulation time 185305545 ps
CPU time 1.48 seconds
Started Sep 04 05:08:13 AM UTC 24
Finished Sep 04 05:08:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514900505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2514900505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/221.edn_genbits.4269307061
Short name T893
Test name
Test status
Simulation time 46631762 ps
CPU time 1.85 seconds
Started Sep 04 05:08:13 AM UTC 24
Finished Sep 04 05:08:16 AM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269307061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4269307061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/222.edn_genbits.56425717
Short name T895
Test name
Test status
Simulation time 60021037 ps
CPU time 1.79 seconds
Started Sep 04 05:08:13 AM UTC 24
Finished Sep 04 05:08:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56425717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 222.edn_genbits.56425717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/223.edn_genbits.1112103056
Short name T894
Test name
Test status
Simulation time 61221438 ps
CPU time 1.8 seconds
Started Sep 04 05:08:13 AM UTC 24
Finished Sep 04 05:08:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112103056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1112103056
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/224.edn_genbits.812102004
Short name T897
Test name
Test status
Simulation time 82721072 ps
CPU time 2 seconds
Started Sep 04 05:08:15 AM UTC 24
Finished Sep 04 05:08:17 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812102004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 224.edn_genbits.812102004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/225.edn_genbits.2520279560
Short name T896
Test name
Test status
Simulation time 37518322 ps
CPU time 1.3 seconds
Started Sep 04 05:08:15 AM UTC 24
Finished Sep 04 05:08:17 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520279560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2520279560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/226.edn_genbits.672738044
Short name T898
Test name
Test status
Simulation time 31227665 ps
CPU time 2.15 seconds
Started Sep 04 05:08:15 AM UTC 24
Finished Sep 04 05:08:18 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672738044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 226.edn_genbits.672738044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/227.edn_genbits.3012044865
Short name T900
Test name
Test status
Simulation time 83562302 ps
CPU time 1.79 seconds
Started Sep 04 05:08:16 AM UTC 24
Finished Sep 04 05:08:19 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012044865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3012044865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/228.edn_genbits.3375305810
Short name T899
Test name
Test status
Simulation time 44084223 ps
CPU time 1.57 seconds
Started Sep 04 05:08:16 AM UTC 24
Finished Sep 04 05:08:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375305810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3375305810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/229.edn_genbits.3755153105
Short name T904
Test name
Test status
Simulation time 46604058 ps
CPU time 2.93 seconds
Started Sep 04 05:08:16 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 231740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755153105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3755153105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_alert.4099942322
Short name T413
Test name
Test status
Simulation time 68754102 ps
CPU time 1.68 seconds
Started Sep 04 05:02:18 AM UTC 24
Finished Sep 04 05:02:21 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099942322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.4099942322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_alert_test.3332145685
Short name T415
Test name
Test status
Simulation time 41185815 ps
CPU time 1.26 seconds
Started Sep 04 05:02:21 AM UTC 24
Finished Sep 04 05:02:24 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332145685 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3332145685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.1332365390
Short name T416
Test name
Test status
Simulation time 42923539 ps
CPU time 1.63 seconds
Started Sep 04 05:02:21 AM UTC 24
Finished Sep 04 05:02:24 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332365390 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.1332365390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_err.913390898
Short name T306
Test name
Test status
Simulation time 44365109 ps
CPU time 1.58 seconds
Started Sep 04 05:02:19 AM UTC 24
Finished Sep 04 05:02:22 AM UTC 24
Peak memory 242192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913390898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.edn_err.913390898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_genbits.577221342
Short name T341
Test name
Test status
Simulation time 45713957 ps
CPU time 1.51 seconds
Started Sep 04 05:02:16 AM UTC 24
Finished Sep 04 05:02:18 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577221342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_genbits.577221342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_intr.3498258377
Short name T414
Test name
Test status
Simulation time 22089884 ps
CPU time 1.69 seconds
Started Sep 04 05:02:18 AM UTC 24
Finished Sep 04 05:02:21 AM UTC 24
Peak memory 237824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498258377 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.3498258377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_smoke.1532984033
Short name T411
Test name
Test status
Simulation time 17280990 ps
CPU time 1.58 seconds
Started Sep 04 05:02:15 AM UTC 24
Finished Sep 04 05:02:17 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532984033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.1532984033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/23.edn_stress_all.882671884
Short name T412
Test name
Test status
Simulation time 154703723 ps
CPU time 1.88 seconds
Started Sep 04 05:02:16 AM UTC 24
Finished Sep 04 05:02:19 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882671884 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.882671884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/230.edn_genbits.2573744947
Short name T901
Test name
Test status
Simulation time 33148415 ps
CPU time 1.76 seconds
Started Sep 04 05:08:17 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573744947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2573744947
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/231.edn_genbits.1404373757
Short name T902
Test name
Test status
Simulation time 81042833 ps
CPU time 1.78 seconds
Started Sep 04 05:08:17 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 227388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404373757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1404373757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/232.edn_genbits.2968808927
Short name T903
Test name
Test status
Simulation time 25436020 ps
CPU time 1.76 seconds
Started Sep 04 05:08:17 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968808927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2968808927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/233.edn_genbits.2551301049
Short name T906
Test name
Test status
Simulation time 34077302 ps
CPU time 1.81 seconds
Started Sep 04 05:08:17 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551301049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2551301049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/234.edn_genbits.2612002068
Short name T907
Test name
Test status
Simulation time 143215506 ps
CPU time 2.23 seconds
Started Sep 04 05:08:17 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612002068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2612002068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/235.edn_genbits.2853970440
Short name T905
Test name
Test status
Simulation time 65871354 ps
CPU time 1.66 seconds
Started Sep 04 05:08:17 AM UTC 24
Finished Sep 04 05:08:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853970440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2853970440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/236.edn_genbits.1604883629
Short name T908
Test name
Test status
Simulation time 30600041 ps
CPU time 1.79 seconds
Started Sep 04 05:08:18 AM UTC 24
Finished Sep 04 05:08:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604883629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1604883629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/237.edn_genbits.2555844781
Short name T869
Test name
Test status
Simulation time 37864394 ps
CPU time 2.06 seconds
Started Sep 04 05:08:18 AM UTC 24
Finished Sep 04 05:08:21 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555844781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2555844781
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/238.edn_genbits.973958506
Short name T910
Test name
Test status
Simulation time 142101082 ps
CPU time 3.12 seconds
Started Sep 04 05:08:18 AM UTC 24
Finished Sep 04 05:08:22 AM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973958506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 238.edn_genbits.973958506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/239.edn_genbits.880021148
Short name T909
Test name
Test status
Simulation time 26948962 ps
CPU time 1.74 seconds
Started Sep 04 05:08:19 AM UTC 24
Finished Sep 04 05:08:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880021148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 239.edn_genbits.880021148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_alert.3429467298
Short name T183
Test name
Test status
Simulation time 30945581 ps
CPU time 1.41 seconds
Started Sep 04 05:02:26 AM UTC 24
Finished Sep 04 05:02:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429467298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.3429467298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_alert_test.3973204568
Short name T419
Test name
Test status
Simulation time 33530177 ps
CPU time 1.31 seconds
Started Sep 04 05:02:29 AM UTC 24
Finished Sep 04 05:02:32 AM UTC 24
Peak memory 217044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973204568 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3973204568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_disable.425085222
Short name T193
Test name
Test status
Simulation time 17985434 ps
CPU time 1.13 seconds
Started Sep 04 05:02:28 AM UTC 24
Finished Sep 04 05:02:30 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425085222 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.425085222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.3147554486
Short name T305
Test name
Test status
Simulation time 34592458 ps
CPU time 1.69 seconds
Started Sep 04 05:02:29 AM UTC 24
Finished Sep 04 05:02:32 AM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147554486 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3147554486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_err.4134904828
Short name T144
Test name
Test status
Simulation time 35242015 ps
CPU time 1.65 seconds
Started Sep 04 05:02:26 AM UTC 24
Finished Sep 04 05:02:28 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134904828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.4134904828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_genbits.352422165
Short name T289
Test name
Test status
Simulation time 41361548 ps
CPU time 1.93 seconds
Started Sep 04 05:02:23 AM UTC 24
Finished Sep 04 05:02:25 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352422165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_genbits.352422165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_intr.1933637067
Short name T95
Test name
Test status
Simulation time 53864897 ps
CPU time 1.25 seconds
Started Sep 04 05:02:25 AM UTC 24
Finished Sep 04 05:02:27 AM UTC 24
Peak memory 228608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933637067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.1933637067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_smoke.2196418433
Short name T417
Test name
Test status
Simulation time 19257627 ps
CPU time 1.52 seconds
Started Sep 04 05:02:22 AM UTC 24
Finished Sep 04 05:02:25 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196418433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_smoke.2196418433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/24.edn_stress_all.816590551
Short name T418
Test name
Test status
Simulation time 462002096 ps
CPU time 3.5 seconds
Started Sep 04 05:02:25 AM UTC 24
Finished Sep 04 05:02:29 AM UTC 24
Peak memory 231248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816590551 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.816590551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/240.edn_genbits.99884181
Short name T918
Test name
Test status
Simulation time 139649621 ps
CPU time 4.88 seconds
Started Sep 04 05:08:19 AM UTC 24
Finished Sep 04 05:08:25 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99884181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 240.edn_genbits.99884181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/241.edn_genbits.773034063
Short name T914
Test name
Test status
Simulation time 49006144 ps
CPU time 2.06 seconds
Started Sep 04 05:08:20 AM UTC 24
Finished Sep 04 05:08:24 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773034063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 241.edn_genbits.773034063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/242.edn_genbits.1633965606
Short name T316
Test name
Test status
Simulation time 53483272 ps
CPU time 2.07 seconds
Started Sep 04 05:08:21 AM UTC 24
Finished Sep 04 05:08:24 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633965606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1633965606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/243.edn_genbits.3013611743
Short name T911
Test name
Test status
Simulation time 52794096 ps
CPU time 1.86 seconds
Started Sep 04 05:08:21 AM UTC 24
Finished Sep 04 05:08:23 AM UTC 24
Peak memory 228580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013611743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3013611743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/244.edn_genbits.3432507640
Short name T912
Test name
Test status
Simulation time 59528476 ps
CPU time 1.78 seconds
Started Sep 04 05:08:21 AM UTC 24
Finished Sep 04 05:08:23 AM UTC 24
Peak memory 226572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432507640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3432507640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/245.edn_genbits.836674811
Short name T913
Test name
Test status
Simulation time 29321283 ps
CPU time 1.8 seconds
Started Sep 04 05:08:21 AM UTC 24
Finished Sep 04 05:08:24 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836674811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.edn_genbits.836674811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/246.edn_genbits.2455719129
Short name T925
Test name
Test status
Simulation time 265137537 ps
CPU time 5.7 seconds
Started Sep 04 05:08:21 AM UTC 24
Finished Sep 04 05:08:27 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455719129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2455719129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/247.edn_genbits.2295977857
Short name T915
Test name
Test status
Simulation time 36241037 ps
CPU time 1.96 seconds
Started Sep 04 05:08:21 AM UTC 24
Finished Sep 04 05:08:24 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295977857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2295977857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/248.edn_genbits.3776762596
Short name T916
Test name
Test status
Simulation time 118503887 ps
CPU time 1.84 seconds
Started Sep 04 05:08:22 AM UTC 24
Finished Sep 04 05:08:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776762596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3776762596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/249.edn_genbits.3214710955
Short name T917
Test name
Test status
Simulation time 287219495 ps
CPU time 2.24 seconds
Started Sep 04 05:08:22 AM UTC 24
Finished Sep 04 05:08:25 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214710955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3214710955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_alert.3979741957
Short name T424
Test name
Test status
Simulation time 79159371 ps
CPU time 1.36 seconds
Started Sep 04 05:02:32 AM UTC 24
Finished Sep 04 05:02:35 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979741957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.3979741957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_alert_test.3093008595
Short name T426
Test name
Test status
Simulation time 51178292 ps
CPU time 1.25 seconds
Started Sep 04 05:02:37 AM UTC 24
Finished Sep 04 05:02:39 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093008595 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3093008595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_disable.4066857573
Short name T425
Test name
Test status
Simulation time 40415214 ps
CPU time 1.38 seconds
Started Sep 04 05:02:36 AM UTC 24
Finished Sep 04 05:02:38 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066857573 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4066857573
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.63328355
Short name T279
Test name
Test status
Simulation time 48752963 ps
CPU time 2.04 seconds
Started Sep 04 05:02:37 AM UTC 24
Finished Sep 04 05:02:40 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63328355 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.63328355
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_err.3018102115
Short name T180
Test name
Test status
Simulation time 18615909 ps
CPU time 1.75 seconds
Started Sep 04 05:02:33 AM UTC 24
Finished Sep 04 05:02:37 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018102115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.3018102115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_genbits.3218785362
Short name T421
Test name
Test status
Simulation time 34240587 ps
CPU time 1.63 seconds
Started Sep 04 05:02:30 AM UTC 24
Finished Sep 04 05:02:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218785362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3218785362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_intr.2699350082
Short name T423
Test name
Test status
Simulation time 29513128 ps
CPU time 1.32 seconds
Started Sep 04 05:02:32 AM UTC 24
Finished Sep 04 05:02:35 AM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699350082 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.2699350082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_smoke.3716709754
Short name T420
Test name
Test status
Simulation time 52380500 ps
CPU time 1.47 seconds
Started Sep 04 05:02:29 AM UTC 24
Finished Sep 04 05:02:32 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716709754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.3716709754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_stress_all.3273241978
Short name T422
Test name
Test status
Simulation time 66085585 ps
CPU time 2.61 seconds
Started Sep 04 05:02:31 AM UTC 24
Finished Sep 04 05:02:35 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273241978 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3273241978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.6684830
Short name T513
Test name
Test status
Simulation time 17031561354 ps
CPU time 111.37 seconds
Started Sep 04 05:02:32 AM UTC 24
Finished Sep 04 05:04:27 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=6684830 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_wi
th_rand_reset.6684830
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/250.edn_genbits.2558033394
Short name T920
Test name
Test status
Simulation time 68302250 ps
CPU time 1.64 seconds
Started Sep 04 05:08:23 AM UTC 24
Finished Sep 04 05:08:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558033394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2558033394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/251.edn_genbits.2341679544
Short name T919
Test name
Test status
Simulation time 101349092 ps
CPU time 1.45 seconds
Started Sep 04 05:08:23 AM UTC 24
Finished Sep 04 05:08:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341679544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2341679544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/252.edn_genbits.2370307756
Short name T923
Test name
Test status
Simulation time 44528467 ps
CPU time 2.02 seconds
Started Sep 04 05:08:24 AM UTC 24
Finished Sep 04 05:08:27 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370307756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2370307756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/253.edn_genbits.2009678075
Short name T328
Test name
Test status
Simulation time 43757847 ps
CPU time 2.48 seconds
Started Sep 04 05:08:24 AM UTC 24
Finished Sep 04 05:08:28 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009678075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2009678075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/254.edn_genbits.520604674
Short name T922
Test name
Test status
Simulation time 47832936 ps
CPU time 1.75 seconds
Started Sep 04 05:08:24 AM UTC 24
Finished Sep 04 05:08:27 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520604674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 254.edn_genbits.520604674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/255.edn_genbits.1082971549
Short name T921
Test name
Test status
Simulation time 103456430 ps
CPU time 1.75 seconds
Started Sep 04 05:08:24 AM UTC 24
Finished Sep 04 05:08:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082971549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1082971549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/256.edn_genbits.2420201915
Short name T926
Test name
Test status
Simulation time 101905234 ps
CPU time 2.19 seconds
Started Sep 04 05:08:24 AM UTC 24
Finished Sep 04 05:08:28 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420201915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2420201915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/257.edn_genbits.515280670
Short name T924
Test name
Test status
Simulation time 31583676 ps
CPU time 1.87 seconds
Started Sep 04 05:08:24 AM UTC 24
Finished Sep 04 05:08:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515280670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 257.edn_genbits.515280670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/258.edn_genbits.4001403137
Short name T928
Test name
Test status
Simulation time 43959358 ps
CPU time 2.46 seconds
Started Sep 04 05:08:25 AM UTC 24
Finished Sep 04 05:08:29 AM UTC 24
Peak memory 229600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001403137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4001403137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/259.edn_genbits.1670759202
Short name T927
Test name
Test status
Simulation time 66756434 ps
CPU time 1.9 seconds
Started Sep 04 05:08:25 AM UTC 24
Finished Sep 04 05:08:28 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670759202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1670759202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_alert.3899322583
Short name T220
Test name
Test status
Simulation time 59279504 ps
CPU time 1.63 seconds
Started Sep 04 05:02:41 AM UTC 24
Finished Sep 04 05:02:44 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899322583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_alert.3899322583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_alert_test.640549844
Short name T430
Test name
Test status
Simulation time 18659854 ps
CPU time 1.48 seconds
Started Sep 04 05:02:45 AM UTC 24
Finished Sep 04 05:02:47 AM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640549844 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.640549844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_disable.3620008465
Short name T429
Test name
Test status
Simulation time 22995302 ps
CPU time 1.24 seconds
Started Sep 04 05:02:43 AM UTC 24
Finished Sep 04 05:02:46 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620008465 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3620008465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.1265147630
Short name T51
Test name
Test status
Simulation time 27970972 ps
CPU time 1.51 seconds
Started Sep 04 05:02:44 AM UTC 24
Finished Sep 04 05:02:47 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265147630 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.1265147630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_err.50365803
Short name T215
Test name
Test status
Simulation time 22686688 ps
CPU time 1.25 seconds
Started Sep 04 05:02:43 AM UTC 24
Finished Sep 04 05:02:46 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50365803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 26.edn_err.50365803
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_genbits.518708913
Short name T342
Test name
Test status
Simulation time 36519322 ps
CPU time 2.08 seconds
Started Sep 04 05:02:39 AM UTC 24
Finished Sep 04 05:02:42 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518708913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_genbits.518708913
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_intr.2843140825
Short name T96
Test name
Test status
Simulation time 26526156 ps
CPU time 1.35 seconds
Started Sep 04 05:02:40 AM UTC 24
Finished Sep 04 05:02:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843140825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.2843140825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_smoke.2149651736
Short name T427
Test name
Test status
Simulation time 60726952 ps
CPU time 1.3 seconds
Started Sep 04 05:02:38 AM UTC 24
Finished Sep 04 05:02:40 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149651736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.2149651736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_stress_all.956379217
Short name T428
Test name
Test status
Simulation time 159284123 ps
CPU time 3.14 seconds
Started Sep 04 05:02:39 AM UTC 24
Finished Sep 04 05:02:43 AM UTC 24
Peak memory 227540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956379217 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.956379217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.2192153632
Short name T511
Test name
Test status
Simulation time 4162356604 ps
CPU time 103.78 seconds
Started Sep 04 05:02:40 AM UTC 24
Finished Sep 04 05:04:26 AM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2192153632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all
_with_rand_reset.2192153632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/260.edn_genbits.1606129911
Short name T930
Test name
Test status
Simulation time 43112691 ps
CPU time 1.93 seconds
Started Sep 04 05:08:27 AM UTC 24
Finished Sep 04 05:08:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606129911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1606129911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/261.edn_genbits.2305046272
Short name T931
Test name
Test status
Simulation time 54601911 ps
CPU time 2.12 seconds
Started Sep 04 05:08:27 AM UTC 24
Finished Sep 04 05:08:30 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305046272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2305046272
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/262.edn_genbits.4080614088
Short name T929
Test name
Test status
Simulation time 84460260 ps
CPU time 1.67 seconds
Started Sep 04 05:08:27 AM UTC 24
Finished Sep 04 05:08:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080614088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4080614088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/263.edn_genbits.1398761772
Short name T935
Test name
Test status
Simulation time 69181022 ps
CPU time 1.85 seconds
Started Sep 04 05:08:28 AM UTC 24
Finished Sep 04 05:08:31 AM UTC 24
Peak memory 230664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398761772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1398761772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/264.edn_genbits.2702383601
Short name T933
Test name
Test status
Simulation time 51176099 ps
CPU time 1.66 seconds
Started Sep 04 05:08:28 AM UTC 24
Finished Sep 04 05:08:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702383601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2702383601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/265.edn_genbits.2859492094
Short name T934
Test name
Test status
Simulation time 42418467 ps
CPU time 1.7 seconds
Started Sep 04 05:08:28 AM UTC 24
Finished Sep 04 05:08:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859492094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2859492094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/266.edn_genbits.185286884
Short name T932
Test name
Test status
Simulation time 35765919 ps
CPU time 1.31 seconds
Started Sep 04 05:08:28 AM UTC 24
Finished Sep 04 05:08:30 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185286884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 266.edn_genbits.185286884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/267.edn_genbits.231618368
Short name T938
Test name
Test status
Simulation time 200587723 ps
CPU time 2.51 seconds
Started Sep 04 05:08:29 AM UTC 24
Finished Sep 04 05:08:32 AM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231618368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 267.edn_genbits.231618368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/268.edn_genbits.1624448666
Short name T937
Test name
Test status
Simulation time 310747787 ps
CPU time 2.21 seconds
Started Sep 04 05:08:29 AM UTC 24
Finished Sep 04 05:08:32 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624448666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1624448666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/269.edn_genbits.3721760634
Short name T936
Test name
Test status
Simulation time 46018498 ps
CPU time 1.93 seconds
Started Sep 04 05:08:29 AM UTC 24
Finished Sep 04 05:08:32 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721760634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3721760634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_alert.2156345873
Short name T81
Test name
Test status
Simulation time 54705013 ps
CPU time 1.71 seconds
Started Sep 04 05:02:48 AM UTC 24
Finished Sep 04 05:02:51 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156345873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.2156345873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_alert_test.3779408007
Short name T437
Test name
Test status
Simulation time 141788837 ps
CPU time 1.37 seconds
Started Sep 04 05:02:50 AM UTC 24
Finished Sep 04 05:02:53 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779408007 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3779408007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_disable.1708862437
Short name T435
Test name
Test status
Simulation time 35642500 ps
CPU time 1.15 seconds
Started Sep 04 05:02:49 AM UTC 24
Finished Sep 04 05:02:51 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708862437 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1708862437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1064981468
Short name T436
Test name
Test status
Simulation time 41085578 ps
CPU time 2.15 seconds
Started Sep 04 05:02:49 AM UTC 24
Finished Sep 04 05:02:52 AM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064981468 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1064981468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_err.3023888123
Short name T434
Test name
Test status
Simulation time 23729970 ps
CPU time 1.25 seconds
Started Sep 04 05:02:48 AM UTC 24
Finished Sep 04 05:02:51 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023888123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.3023888123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_genbits.3514833433
Short name T290
Test name
Test status
Simulation time 210375868 ps
CPU time 1.6 seconds
Started Sep 04 05:02:47 AM UTC 24
Finished Sep 04 05:02:50 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514833433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3514833433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_intr.2588354280
Short name T433
Test name
Test status
Simulation time 39513201 ps
CPU time 1.16 seconds
Started Sep 04 05:02:48 AM UTC 24
Finished Sep 04 05:02:50 AM UTC 24
Peak memory 236656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588354280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.2588354280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_smoke.1964044440
Short name T432
Test name
Test status
Simulation time 88497772 ps
CPU time 1.33 seconds
Started Sep 04 05:02:46 AM UTC 24
Finished Sep 04 05:02:48 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964044440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.1964044440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/27.edn_stress_all.1346478501
Short name T246
Test name
Test status
Simulation time 218941912 ps
CPU time 1.8 seconds
Started Sep 04 05:02:47 AM UTC 24
Finished Sep 04 05:02:50 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346478501 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1346478501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/270.edn_genbits.635918482
Short name T949
Test name
Test status
Simulation time 427382575 ps
CPU time 6.45 seconds
Started Sep 04 05:08:29 AM UTC 24
Finished Sep 04 05:08:37 AM UTC 24
Peak memory 231492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635918482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 270.edn_genbits.635918482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/271.edn_genbits.138001085
Short name T941
Test name
Test status
Simulation time 115025954 ps
CPU time 2.44 seconds
Started Sep 04 05:08:30 AM UTC 24
Finished Sep 04 05:08:34 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138001085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 271.edn_genbits.138001085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/272.edn_genbits.1019328171
Short name T939
Test name
Test status
Simulation time 55119691 ps
CPU time 1.7 seconds
Started Sep 04 05:08:30 AM UTC 24
Finished Sep 04 05:08:33 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019328171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1019328171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/273.edn_genbits.2510601424
Short name T943
Test name
Test status
Simulation time 50879183 ps
CPU time 2.97 seconds
Started Sep 04 05:08:30 AM UTC 24
Finished Sep 04 05:08:34 AM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510601424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2510601424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/274.edn_genbits.457155145
Short name T940
Test name
Test status
Simulation time 60854682 ps
CPU time 2.14 seconds
Started Sep 04 05:08:30 AM UTC 24
Finished Sep 04 05:08:33 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457155145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 274.edn_genbits.457155145
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/275.edn_genbits.26923349
Short name T942
Test name
Test status
Simulation time 69092045 ps
CPU time 1.35 seconds
Started Sep 04 05:08:31 AM UTC 24
Finished Sep 04 05:08:34 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26923349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 275.edn_genbits.26923349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/276.edn_genbits.23586373
Short name T944
Test name
Test status
Simulation time 38138588 ps
CPU time 1.76 seconds
Started Sep 04 05:08:31 AM UTC 24
Finished Sep 04 05:08:34 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23586373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 276.edn_genbits.23586373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/277.edn_genbits.1939260211
Short name T946
Test name
Test status
Simulation time 88294161 ps
CPU time 2.24 seconds
Started Sep 04 05:08:32 AM UTC 24
Finished Sep 04 05:08:35 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939260211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1939260211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/278.edn_genbits.3457763400
Short name T945
Test name
Test status
Simulation time 117643381 ps
CPU time 2.01 seconds
Started Sep 04 05:08:32 AM UTC 24
Finished Sep 04 05:08:35 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457763400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3457763400
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/279.edn_genbits.1290401731
Short name T948
Test name
Test status
Simulation time 27863168 ps
CPU time 1.8 seconds
Started Sep 04 05:08:33 AM UTC 24
Finished Sep 04 05:08:35 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290401731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1290401731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_alert.2318708413
Short name T200
Test name
Test status
Simulation time 31305761 ps
CPU time 1.76 seconds
Started Sep 04 05:02:54 AM UTC 24
Finished Sep 04 05:02:56 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318708413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_alert.2318708413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_alert_test.456271625
Short name T443
Test name
Test status
Simulation time 46194709 ps
CPU time 1.56 seconds
Started Sep 04 05:02:56 AM UTC 24
Finished Sep 04 05:02:58 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456271625 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.456271625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_disable.1505048342
Short name T440
Test name
Test status
Simulation time 22927766 ps
CPU time 1.33 seconds
Started Sep 04 05:02:54 AM UTC 24
Finished Sep 04 05:02:56 AM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505048342 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1505048342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.467975357
Short name T442
Test name
Test status
Simulation time 366944398 ps
CPU time 1.71 seconds
Started Sep 04 05:02:55 AM UTC 24
Finished Sep 04 05:02:57 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467975357 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.467975357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_err.3242590804
Short name T441
Test name
Test status
Simulation time 69014290 ps
CPU time 1.44 seconds
Started Sep 04 05:02:54 AM UTC 24
Finished Sep 04 05:02:56 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242590804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.3242590804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_genbits.825497205
Short name T293
Test name
Test status
Simulation time 49841948 ps
CPU time 1.58 seconds
Started Sep 04 05:02:51 AM UTC 24
Finished Sep 04 05:02:54 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825497205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_genbits.825497205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_intr.620744423
Short name T439
Test name
Test status
Simulation time 27791963 ps
CPU time 1.22 seconds
Started Sep 04 05:02:53 AM UTC 24
Finished Sep 04 05:02:55 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620744423 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.620744423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_smoke.1881111831
Short name T438
Test name
Test status
Simulation time 30806569 ps
CPU time 1.35 seconds
Started Sep 04 05:02:50 AM UTC 24
Finished Sep 04 05:02:53 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881111831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.1881111831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_stress_all.455077916
Short name T247
Test name
Test status
Simulation time 196854711 ps
CPU time 4.8 seconds
Started Sep 04 05:02:51 AM UTC 24
Finished Sep 04 05:02:58 AM UTC 24
Peak memory 229396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455077916 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.455077916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.283283379
Short name T231
Test name
Test status
Simulation time 821251753 ps
CPU time 25.13 seconds
Started Sep 04 05:02:51 AM UTC 24
Finished Sep 04 05:03:18 AM UTC 24
Peak memory 229592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=283283379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_
with_rand_reset.283283379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/280.edn_genbits.672731976
Short name T947
Test name
Test status
Simulation time 37890328 ps
CPU time 1.64 seconds
Started Sep 04 05:08:33 AM UTC 24
Finished Sep 04 05:08:35 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672731976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 280.edn_genbits.672731976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/281.edn_genbits.3820827354
Short name T950
Test name
Test status
Simulation time 41562977 ps
CPU time 2.05 seconds
Started Sep 04 05:08:34 AM UTC 24
Finished Sep 04 05:08:37 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820827354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3820827354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/282.edn_genbits.3102118562
Short name T951
Test name
Test status
Simulation time 71289138 ps
CPU time 2.29 seconds
Started Sep 04 05:08:34 AM UTC 24
Finished Sep 04 05:08:37 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102118562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3102118562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/283.edn_genbits.3045908501
Short name T960
Test name
Test status
Simulation time 610920879 ps
CPU time 5.18 seconds
Started Sep 04 05:08:34 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045908501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3045908501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/284.edn_genbits.3480375800
Short name T953
Test name
Test status
Simulation time 101927825 ps
CPU time 1.85 seconds
Started Sep 04 05:08:35 AM UTC 24
Finished Sep 04 05:08:38 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480375800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3480375800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/285.edn_genbits.92213312
Short name T952
Test name
Test status
Simulation time 74264850 ps
CPU time 1.82 seconds
Started Sep 04 05:08:35 AM UTC 24
Finished Sep 04 05:08:38 AM UTC 24
Peak memory 228272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92213312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 285.edn_genbits.92213312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/286.edn_genbits.3100361500
Short name T957
Test name
Test status
Simulation time 74722204 ps
CPU time 3.54 seconds
Started Sep 04 05:08:35 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 231784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100361500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3100361500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/287.edn_genbits.1226362891
Short name T954
Test name
Test status
Simulation time 42554695 ps
CPU time 1.87 seconds
Started Sep 04 05:08:35 AM UTC 24
Finished Sep 04 05:08:38 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226362891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1226362891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/288.edn_genbits.36307417
Short name T955
Test name
Test status
Simulation time 33678407 ps
CPU time 2.01 seconds
Started Sep 04 05:08:35 AM UTC 24
Finished Sep 04 05:08:38 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36307417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 288.edn_genbits.36307417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/289.edn_genbits.3855959251
Short name T958
Test name
Test status
Simulation time 47251086 ps
CPU time 2.29 seconds
Started Sep 04 05:08:36 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855959251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3855959251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_alert.2200062717
Short name T117
Test name
Test status
Simulation time 74132170 ps
CPU time 1.61 seconds
Started Sep 04 05:02:59 AM UTC 24
Finished Sep 04 05:03:02 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200062717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.2200062717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_alert_test.1836978743
Short name T449
Test name
Test status
Simulation time 22635873 ps
CPU time 1.35 seconds
Started Sep 04 05:03:01 AM UTC 24
Finished Sep 04 05:03:04 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836978743 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1836978743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_disable.636818687
Short name T447
Test name
Test status
Simulation time 39466947 ps
CPU time 1.34 seconds
Started Sep 04 05:03:00 AM UTC 24
Finished Sep 04 05:03:03 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636818687 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.636818687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1889049169
Short name T448
Test name
Test status
Simulation time 201881439 ps
CPU time 1.65 seconds
Started Sep 04 05:03:00 AM UTC 24
Finished Sep 04 05:03:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889049169 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1889049169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_err.524644567
Short name T446
Test name
Test status
Simulation time 21928238 ps
CPU time 1.2 seconds
Started Sep 04 05:03:00 AM UTC 24
Finished Sep 04 05:03:02 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524644567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.edn_err.524644567
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_genbits.2571968271
Short name T343
Test name
Test status
Simulation time 34807665 ps
CPU time 1.62 seconds
Started Sep 04 05:02:57 AM UTC 24
Finished Sep 04 05:03:00 AM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571968271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2571968271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_intr.1358587833
Short name T445
Test name
Test status
Simulation time 54842370 ps
CPU time 1.2 seconds
Started Sep 04 05:02:58 AM UTC 24
Finished Sep 04 05:03:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358587833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.1358587833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_smoke.1338463698
Short name T409
Test name
Test status
Simulation time 17365266 ps
CPU time 1.51 seconds
Started Sep 04 05:02:57 AM UTC 24
Finished Sep 04 05:02:59 AM UTC 24
Peak memory 225996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338463698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.1338463698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_stress_all.1677235744
Short name T444
Test name
Test status
Simulation time 49175117 ps
CPU time 1.2 seconds
Started Sep 04 05:02:57 AM UTC 24
Finished Sep 04 05:02:59 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677235744 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1677235744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.2177184106
Short name T541
Test name
Test status
Simulation time 3643333646 ps
CPU time 120.24 seconds
Started Sep 04 05:02:58 AM UTC 24
Finished Sep 04 05:05:01 AM UTC 24
Peak memory 227760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2177184106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all
_with_rand_reset.2177184106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/290.edn_genbits.3990461885
Short name T959
Test name
Test status
Simulation time 47833045 ps
CPU time 2.43 seconds
Started Sep 04 05:08:36 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 231492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990461885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3990461885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/291.edn_genbits.972491008
Short name T956
Test name
Test status
Simulation time 44395280 ps
CPU time 2.22 seconds
Started Sep 04 05:08:36 AM UTC 24
Finished Sep 04 05:08:39 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972491008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 291.edn_genbits.972491008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/292.edn_genbits.3809422716
Short name T961
Test name
Test status
Simulation time 44667420 ps
CPU time 1.84 seconds
Started Sep 04 05:08:37 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809422716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3809422716
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/293.edn_genbits.2614619323
Short name T962
Test name
Test status
Simulation time 30438567 ps
CPU time 1.86 seconds
Started Sep 04 05:08:37 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614619323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2614619323
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/294.edn_genbits.2580841626
Short name T963
Test name
Test status
Simulation time 47587815 ps
CPU time 1.88 seconds
Started Sep 04 05:08:37 AM UTC 24
Finished Sep 04 05:08:40 AM UTC 24
Peak memory 228616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580841626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2580841626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/295.edn_genbits.3126758172
Short name T966
Test name
Test status
Simulation time 41278856 ps
CPU time 2.22 seconds
Started Sep 04 05:08:39 AM UTC 24
Finished Sep 04 05:08:42 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126758172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3126758172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/296.edn_genbits.606421890
Short name T965
Test name
Test status
Simulation time 80689912 ps
CPU time 2.2 seconds
Started Sep 04 05:08:39 AM UTC 24
Finished Sep 04 05:08:42 AM UTC 24
Peak memory 231640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606421890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 296.edn_genbits.606421890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/297.edn_genbits.1807444375
Short name T967
Test name
Test status
Simulation time 42686914 ps
CPU time 2.55 seconds
Started Sep 04 05:08:39 AM UTC 24
Finished Sep 04 05:08:42 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807444375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1807444375
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/298.edn_genbits.1508673904
Short name T964
Test name
Test status
Simulation time 95117832 ps
CPU time 2 seconds
Started Sep 04 05:08:39 AM UTC 24
Finished Sep 04 05:08:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508673904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1508673904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/299.edn_genbits.1972722543
Short name T968
Test name
Test status
Simulation time 41187041 ps
CPU time 1.55 seconds
Started Sep 04 05:08:41 AM UTC 24
Finished Sep 04 05:08:43 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972722543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1972722543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_alert_test.1102536062
Short name T68
Test name
Test status
Simulation time 21236699 ps
CPU time 1.38 seconds
Started Sep 04 04:59:59 AM UTC 24
Finished Sep 04 05:00:01 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102536062 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1102536062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_disable.1626964560
Short name T54
Test name
Test status
Simulation time 14732045 ps
CPU time 1.47 seconds
Started Sep 04 04:59:58 AM UTC 24
Finished Sep 04 05:00:00 AM UTC 24
Peak memory 216056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626964560 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1626964560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.2078514783
Short name T20
Test name
Test status
Simulation time 117941504 ps
CPU time 1.67 seconds
Started Sep 04 04:59:58 AM UTC 24
Finished Sep 04 05:00:00 AM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078514783 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.2078514783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_err.177877800
Short name T8
Test name
Test status
Simulation time 34893493 ps
CPU time 1.31 seconds
Started Sep 04 04:59:56 AM UTC 24
Finished Sep 04 04:59:59 AM UTC 24
Peak memory 244220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177877800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.edn_err.177877800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_intr.630387709
Short name T44
Test name
Test status
Simulation time 28311844 ps
CPU time 1.3 seconds
Started Sep 04 04:59:56 AM UTC 24
Finished Sep 04 04:59:59 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630387709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.630387709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_regwen.3178159759
Short name T90
Test name
Test status
Simulation time 15904216 ps
CPU time 1.48 seconds
Started Sep 04 04:59:54 AM UTC 24
Finished Sep 04 04:59:57 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178159759 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.3178159759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_sec_cm.3263337476
Short name T19
Test name
Test status
Simulation time 242955825 ps
CPU time 4.83 seconds
Started Sep 04 04:59:59 AM UTC 24
Finished Sep 04 05:00:05 AM UTC 24
Peak memory 262412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263337476 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3263337476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_smoke.3352065353
Short name T89
Test name
Test status
Simulation time 16927643 ps
CPU time 1.39 seconds
Started Sep 04 04:59:53 AM UTC 24
Finished Sep 04 04:59:55 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352065353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.3352065353
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.3080072221
Short name T35
Test name
Test status
Simulation time 2066489295 ps
CPU time 55.34 seconds
Started Sep 04 04:59:55 AM UTC 24
Finished Sep 04 05:00:52 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3080072221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.3080072221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_alert.3715856136
Short name T453
Test name
Test status
Simulation time 92686873 ps
CPU time 1.86 seconds
Started Sep 04 05:03:06 AM UTC 24
Finished Sep 04 05:03:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715856136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.3715856136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_alert_test.3706408748
Short name T455
Test name
Test status
Simulation time 22088436 ps
CPU time 1.29 seconds
Started Sep 04 05:03:11 AM UTC 24
Finished Sep 04 05:03:13 AM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706408748 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3706408748
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_disable.3806723084
Short name T207
Test name
Test status
Simulation time 56907499 ps
CPU time 1.32 seconds
Started Sep 04 05:03:08 AM UTC 24
Finished Sep 04 05:03:10 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806723084 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3806723084
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.3198529108
Short name T92
Test name
Test status
Simulation time 171118263 ps
CPU time 1.59 seconds
Started Sep 04 05:03:09 AM UTC 24
Finished Sep 04 05:03:11 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198529108 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.3198529108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_err.2257432698
Short name T454
Test name
Test status
Simulation time 22949350 ps
CPU time 1.5 seconds
Started Sep 04 05:03:08 AM UTC 24
Finished Sep 04 05:03:10 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257432698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.2257432698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_genbits.3062313106
Short name T451
Test name
Test status
Simulation time 63952416 ps
CPU time 2.57 seconds
Started Sep 04 05:03:04 AM UTC 24
Finished Sep 04 05:03:07 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062313106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3062313106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_intr.622646467
Short name T452
Test name
Test status
Simulation time 31095175 ps
CPU time 1.53 seconds
Started Sep 04 05:03:05 AM UTC 24
Finished Sep 04 05:03:07 AM UTC 24
Peak memory 237400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622646467 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.622646467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_smoke.12782858
Short name T450
Test name
Test status
Simulation time 19886901 ps
CPU time 1.61 seconds
Started Sep 04 05:03:02 AM UTC 24
Finished Sep 04 05:03:05 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12782858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_smoke.12782858
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_stress_all.478519421
Short name T248
Test name
Test status
Simulation time 415586235 ps
CPU time 11.27 seconds
Started Sep 04 05:03:04 AM UTC 24
Finished Sep 04 05:03:16 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478519421 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.478519421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.292214340
Short name T311
Test name
Test status
Simulation time 1825813875 ps
CPU time 63.33 seconds
Started Sep 04 05:03:04 AM UTC 24
Finished Sep 04 05:04:09 AM UTC 24
Peak memory 231640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=292214340 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_
with_rand_reset.292214340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_alert.638246331
Short name T177
Test name
Test status
Simulation time 51575042 ps
CPU time 1.57 seconds
Started Sep 04 05:03:16 AM UTC 24
Finished Sep 04 05:03:19 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638246331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_alert.638246331
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_alert_test.1417997955
Short name T462
Test name
Test status
Simulation time 28934451 ps
CPU time 1.36 seconds
Started Sep 04 05:03:20 AM UTC 24
Finished Sep 04 05:03:22 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417997955 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1417997955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_disable.743064247
Short name T221
Test name
Test status
Simulation time 15775931 ps
CPU time 1.42 seconds
Started Sep 04 05:03:18 AM UTC 24
Finished Sep 04 05:03:20 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743064247 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.743064247
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.3728323061
Short name T460
Test name
Test status
Simulation time 66498488 ps
CPU time 1.85 seconds
Started Sep 04 05:03:19 AM UTC 24
Finished Sep 04 05:03:22 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728323061 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.3728323061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_genbits.266084100
Short name T457
Test name
Test status
Simulation time 34435716 ps
CPU time 2.01 seconds
Started Sep 04 05:03:12 AM UTC 24
Finished Sep 04 05:03:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266084100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_genbits.266084100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_intr.260974042
Short name T458
Test name
Test status
Simulation time 25141010 ps
CPU time 1.35 seconds
Started Sep 04 05:03:14 AM UTC 24
Finished Sep 04 05:03:17 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260974042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.260974042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_smoke.2858803429
Short name T456
Test name
Test status
Simulation time 16949025 ps
CPU time 1.58 seconds
Started Sep 04 05:03:11 AM UTC 24
Finished Sep 04 05:03:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858803429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.2858803429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_stress_all.1750180883
Short name T323
Test name
Test status
Simulation time 581718596 ps
CPU time 3.57 seconds
Started Sep 04 05:03:14 AM UTC 24
Finished Sep 04 05:03:19 AM UTC 24
Peak memory 227408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750180883 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1750180883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.2974341684
Short name T232
Test name
Test status
Simulation time 14712073976 ps
CPU time 46.96 seconds
Started Sep 04 05:03:14 AM UTC 24
Finished Sep 04 05:04:03 AM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2974341684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all
_with_rand_reset.2974341684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_alert.1537942993
Short name T153
Test name
Test status
Simulation time 31827963 ps
CPU time 2.03 seconds
Started Sep 04 05:03:23 AM UTC 24
Finished Sep 04 05:03:26 AM UTC 24
Peak memory 232324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537942993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.1537942993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_alert_test.3117858021
Short name T469
Test name
Test status
Simulation time 44702596 ps
CPU time 1.15 seconds
Started Sep 04 05:03:27 AM UTC 24
Finished Sep 04 05:03:29 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117858021 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3117858021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_disable.4208678481
Short name T467
Test name
Test status
Simulation time 25129393 ps
CPU time 1.31 seconds
Started Sep 04 05:03:25 AM UTC 24
Finished Sep 04 05:03:27 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208678481 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4208678481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.2764099843
Short name T470
Test name
Test status
Simulation time 40980218 ps
CPU time 2.19 seconds
Started Sep 04 05:03:26 AM UTC 24
Finished Sep 04 05:03:29 AM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764099843 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.2764099843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_err.2359553888
Short name T168
Test name
Test status
Simulation time 19027322 ps
CPU time 1.24 seconds
Started Sep 04 05:03:24 AM UTC 24
Finished Sep 04 05:03:26 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359553888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.2359553888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_genbits.3461776855
Short name T463
Test name
Test status
Simulation time 47983129 ps
CPU time 2.22 seconds
Started Sep 04 05:03:20 AM UTC 24
Finished Sep 04 05:03:23 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461776855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3461776855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_intr.292519541
Short name T465
Test name
Test status
Simulation time 20920594 ps
CPU time 1.81 seconds
Started Sep 04 05:03:23 AM UTC 24
Finished Sep 04 05:03:26 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292519541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.292519541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_smoke.4093226278
Short name T461
Test name
Test status
Simulation time 84952487 ps
CPU time 1.3 seconds
Started Sep 04 05:03:20 AM UTC 24
Finished Sep 04 05:03:22 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093226278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.4093226278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/32.edn_stress_all.1402678542
Short name T466
Test name
Test status
Simulation time 290277040 ps
CPU time 4.42 seconds
Started Sep 04 05:03:21 AM UTC 24
Finished Sep 04 05:03:26 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402678542 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1402678542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_alert.3010931763
Short name T473
Test name
Test status
Simulation time 188778438 ps
CPU time 1.71 seconds
Started Sep 04 05:03:31 AM UTC 24
Finished Sep 04 05:03:33 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010931763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_alert.3010931763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_alert_test.762271768
Short name T475
Test name
Test status
Simulation time 124946832 ps
CPU time 1.32 seconds
Started Sep 04 05:03:35 AM UTC 24
Finished Sep 04 05:03:37 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762271768 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.762271768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_disable.1693956808
Short name T216
Test name
Test status
Simulation time 10792774 ps
CPU time 1.18 seconds
Started Sep 04 05:03:34 AM UTC 24
Finished Sep 04 05:03:36 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693956808 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1693956808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_err.2604041638
Short name T197
Test name
Test status
Simulation time 25555696 ps
CPU time 1.43 seconds
Started Sep 04 05:03:31 AM UTC 24
Finished Sep 04 05:03:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604041638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.2604041638
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_genbits.2221723470
Short name T471
Test name
Test status
Simulation time 25075294 ps
CPU time 1.68 seconds
Started Sep 04 05:03:27 AM UTC 24
Finished Sep 04 05:03:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221723470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2221723470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_intr.2406255824
Short name T472
Test name
Test status
Simulation time 33324076 ps
CPU time 1.1 seconds
Started Sep 04 05:03:31 AM UTC 24
Finished Sep 04 05:03:33 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406255824 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.2406255824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_smoke.4243883921
Short name T468
Test name
Test status
Simulation time 47230708 ps
CPU time 1.2 seconds
Started Sep 04 05:03:27 AM UTC 24
Finished Sep 04 05:03:29 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243883921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.4243883921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_stress_all.3672878869
Short name T474
Test name
Test status
Simulation time 174899279 ps
CPU time 5.91 seconds
Started Sep 04 05:03:28 AM UTC 24
Finished Sep 04 05:03:36 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672878869 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3672878869
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.2590158487
Short name T505
Test name
Test status
Simulation time 5391677132 ps
CPU time 42.73 seconds
Started Sep 04 05:03:31 AM UTC 24
Finished Sep 04 05:04:15 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2590158487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all
_with_rand_reset.2590158487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_alert.238752438
Short name T479
Test name
Test status
Simulation time 28247219 ps
CPU time 1.88 seconds
Started Sep 04 05:03:39 AM UTC 24
Finished Sep 04 05:03:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238752438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_alert.238752438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_alert_test.1797016040
Short name T482
Test name
Test status
Simulation time 25613080 ps
CPU time 1.12 seconds
Started Sep 04 05:03:43 AM UTC 24
Finished Sep 04 05:03:45 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797016040 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1797016040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_disable.2377912058
Short name T481
Test name
Test status
Simulation time 56492631 ps
CPU time 1.24 seconds
Started Sep 04 05:03:41 AM UTC 24
Finished Sep 04 05:03:44 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377912058 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2377912058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.3244037120
Short name T217
Test name
Test status
Simulation time 66909054 ps
CPU time 1.66 seconds
Started Sep 04 05:03:43 AM UTC 24
Finished Sep 04 05:03:45 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244037120 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.3244037120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_err.1510866359
Short name T480
Test name
Test status
Simulation time 29805186 ps
CPU time 1.31 seconds
Started Sep 04 05:03:40 AM UTC 24
Finished Sep 04 05:03:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510866359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.edn_err.1510866359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_genbits.2182254194
Short name T14
Test name
Test status
Simulation time 259101824 ps
CPU time 1.96 seconds
Started Sep 04 05:03:37 AM UTC 24
Finished Sep 04 05:03:40 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182254194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2182254194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_intr.4159247776
Short name T477
Test name
Test status
Simulation time 22622414 ps
CPU time 1.68 seconds
Started Sep 04 05:03:38 AM UTC 24
Finished Sep 04 05:03:41 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159247776 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.4159247776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_smoke.2383308277
Short name T476
Test name
Test status
Simulation time 93275795 ps
CPU time 1.39 seconds
Started Sep 04 05:03:36 AM UTC 24
Finished Sep 04 05:03:38 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383308277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.2383308277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_stress_all.3162404411
Short name T478
Test name
Test status
Simulation time 368065065 ps
CPU time 3.73 seconds
Started Sep 04 05:03:37 AM UTC 24
Finished Sep 04 05:03:42 AM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162404411 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3162404411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.2733307676
Short name T556
Test name
Test status
Simulation time 13589488804 ps
CPU time 114.55 seconds
Started Sep 04 05:03:37 AM UTC 24
Finished Sep 04 05:05:34 AM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2733307676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all
_with_rand_reset.2733307676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_alert.3036171333
Short name T154
Test name
Test status
Simulation time 40062504 ps
CPU time 1.65 seconds
Started Sep 04 05:03:48 AM UTC 24
Finished Sep 04 05:03:51 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036171333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.3036171333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_alert_test.1696571101
Short name T490
Test name
Test status
Simulation time 68144924 ps
CPU time 1.22 seconds
Started Sep 04 05:03:52 AM UTC 24
Finished Sep 04 05:03:54 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696571101 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1696571101
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_disable.858834599
Short name T487
Test name
Test status
Simulation time 29033193 ps
CPU time 1.23 seconds
Started Sep 04 05:03:50 AM UTC 24
Finished Sep 04 05:03:52 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858834599 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.858834599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.1952439432
Short name T488
Test name
Test status
Simulation time 77461687 ps
CPU time 1.74 seconds
Started Sep 04 05:03:51 AM UTC 24
Finished Sep 04 05:03:54 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952439432 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.1952439432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_err.48569958
Short name T158
Test name
Test status
Simulation time 18984383 ps
CPU time 1.49 seconds
Started Sep 04 05:03:49 AM UTC 24
Finished Sep 04 05:03:51 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48569958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 35.edn_err.48569958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_genbits.40006374
Short name T484
Test name
Test status
Simulation time 66701572 ps
CPU time 1.78 seconds
Started Sep 04 05:03:45 AM UTC 24
Finished Sep 04 05:03:47 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40006374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.edn_genbits.40006374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_intr.606163837
Short name T486
Test name
Test status
Simulation time 58973492 ps
CPU time 1.33 seconds
Started Sep 04 05:03:47 AM UTC 24
Finished Sep 04 05:03:49 AM UTC 24
Peak memory 237144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606163837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.606163837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_smoke.717330629
Short name T483
Test name
Test status
Simulation time 17271442 ps
CPU time 1.13 seconds
Started Sep 04 05:03:44 AM UTC 24
Finished Sep 04 05:03:46 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717330629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.edn_smoke.717330629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_stress_all.425834658
Short name T489
Test name
Test status
Simulation time 243968691 ps
CPU time 7.26 seconds
Started Sep 04 05:03:46 AM UTC 24
Finished Sep 04 05:03:54 AM UTC 24
Peak memory 227544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425834658 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.425834658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.4203124833
Short name T234
Test name
Test status
Simulation time 7487305949 ps
CPU time 122.38 seconds
Started Sep 04 05:03:46 AM UTC 24
Finished Sep 04 05:05:51 AM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4203124833 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.4203124833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_alert.3699846615
Short name T125
Test name
Test status
Simulation time 29991733 ps
CPU time 1.94 seconds
Started Sep 04 05:03:57 AM UTC 24
Finished Sep 04 05:04:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699846615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.3699846615
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_alert_test.1119604596
Short name T496
Test name
Test status
Simulation time 84479325 ps
CPU time 1.18 seconds
Started Sep 04 05:04:00 AM UTC 24
Finished Sep 04 05:04:02 AM UTC 24
Peak memory 216988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119604596 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1119604596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_disable.1159223847
Short name T203
Test name
Test status
Simulation time 18184239 ps
CPU time 1.3 seconds
Started Sep 04 05:03:59 AM UTC 24
Finished Sep 04 05:04:01 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159223847 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1159223847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_err.21336180
Short name T495
Test name
Test status
Simulation time 19333595 ps
CPU time 1.76 seconds
Started Sep 04 05:03:57 AM UTC 24
Finished Sep 04 05:03:59 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21336180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 36.edn_err.21336180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_genbits.311116585
Short name T492
Test name
Test status
Simulation time 47222262 ps
CPU time 1.93 seconds
Started Sep 04 05:03:53 AM UTC 24
Finished Sep 04 05:03:56 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311116585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_genbits.311116585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_intr.3217578371
Short name T493
Test name
Test status
Simulation time 38615311 ps
CPU time 1.46 seconds
Started Sep 04 05:03:56 AM UTC 24
Finished Sep 04 05:03:58 AM UTC 24
Peak memory 237088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217578371 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.3217578371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_smoke.1602151978
Short name T491
Test name
Test status
Simulation time 18511100 ps
CPU time 1.44 seconds
Started Sep 04 05:03:53 AM UTC 24
Finished Sep 04 05:03:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602151978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.1602151978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/36.edn_stress_all.1040546609
Short name T494
Test name
Test status
Simulation time 488053997 ps
CPU time 3.41 seconds
Started Sep 04 05:03:54 AM UTC 24
Finished Sep 04 05:03:59 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040546609 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1040546609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_alert.1543062301
Short name T126
Test name
Test status
Simulation time 48261865 ps
CPU time 1.85 seconds
Started Sep 04 05:04:04 AM UTC 24
Finished Sep 04 05:04:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543062301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.1543062301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_alert_test.3054172183
Short name T502
Test name
Test status
Simulation time 14099463 ps
CPU time 1.33 seconds
Started Sep 04 05:04:09 AM UTC 24
Finished Sep 04 05:04:11 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054172183 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3054172183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_disable.3538303918
Short name T501
Test name
Test status
Simulation time 11434461 ps
CPU time 1.35 seconds
Started Sep 04 05:04:07 AM UTC 24
Finished Sep 04 05:04:10 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538303918 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3538303918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.1998046281
Short name T280
Test name
Test status
Simulation time 116212119 ps
CPU time 1.89 seconds
Started Sep 04 05:04:07 AM UTC 24
Finished Sep 04 05:04:10 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998046281 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.1998046281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_err.4084446572
Short name T500
Test name
Test status
Simulation time 24951066 ps
CPU time 1.5 seconds
Started Sep 04 05:04:05 AM UTC 24
Finished Sep 04 05:04:08 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084446572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.4084446572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_genbits.2030441054
Short name T499
Test name
Test status
Simulation time 26438785 ps
CPU time 1.61 seconds
Started Sep 04 05:04:02 AM UTC 24
Finished Sep 04 05:04:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030441054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2030441054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_intr.4292885992
Short name T118
Test name
Test status
Simulation time 96515452 ps
CPU time 1.26 seconds
Started Sep 04 05:04:04 AM UTC 24
Finished Sep 04 05:04:06 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292885992 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.4292885992
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_smoke.1276864250
Short name T498
Test name
Test status
Simulation time 25004184 ps
CPU time 1.38 seconds
Started Sep 04 05:04:01 AM UTC 24
Finished Sep 04 05:04:03 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276864250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.1276864250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_stress_all.2736394697
Short name T309
Test name
Test status
Simulation time 1786194702 ps
CPU time 5.16 seconds
Started Sep 04 05:04:03 AM UTC 24
Finished Sep 04 05:04:09 AM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736394697 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2736394697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.3606940166
Short name T236
Test name
Test status
Simulation time 8318487337 ps
CPU time 119.71 seconds
Started Sep 04 05:04:03 AM UTC 24
Finished Sep 04 05:06:05 AM UTC 24
Peak memory 230116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3606940166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all
_with_rand_reset.3606940166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_alert.2086785647
Short name T506
Test name
Test status
Simulation time 24909739 ps
CPU time 1.6 seconds
Started Sep 04 05:04:13 AM UTC 24
Finished Sep 04 05:04:15 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086785647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_alert.2086785647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_alert_test.3813055719
Short name T509
Test name
Test status
Simulation time 56543695 ps
CPU time 1.43 seconds
Started Sep 04 05:04:16 AM UTC 24
Finished Sep 04 05:04:19 AM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813055719 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3813055719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_disable.562985884
Short name T213
Test name
Test status
Simulation time 20216107 ps
CPU time 1.32 seconds
Started Sep 04 05:04:15 AM UTC 24
Finished Sep 04 05:04:18 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562985884 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.562985884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.443506973
Short name T123
Test name
Test status
Simulation time 31874999 ps
CPU time 1.77 seconds
Started Sep 04 05:04:16 AM UTC 24
Finished Sep 04 05:04:19 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443506973 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.443506973
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_err.577160103
Short name T508
Test name
Test status
Simulation time 19417901 ps
CPU time 1.59 seconds
Started Sep 04 05:04:14 AM UTC 24
Finished Sep 04 05:04:17 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577160103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.edn_err.577160103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_genbits.3243916498
Short name T338
Test name
Test status
Simulation time 88670979 ps
CPU time 2.61 seconds
Started Sep 04 05:04:10 AM UTC 24
Finished Sep 04 05:04:13 AM UTC 24
Peak memory 231824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243916498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3243916498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_intr.1720422847
Short name T504
Test name
Test status
Simulation time 35141570 ps
CPU time 1.28 seconds
Started Sep 04 05:04:12 AM UTC 24
Finished Sep 04 05:04:14 AM UTC 24
Peak memory 236704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720422847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.1720422847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_smoke.3925772770
Short name T503
Test name
Test status
Simulation time 44048370 ps
CPU time 1.26 seconds
Started Sep 04 05:04:10 AM UTC 24
Finished Sep 04 05:04:12 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925772770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.3925772770
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/38.edn_stress_all.4090486416
Short name T507
Test name
Test status
Simulation time 556318608 ps
CPU time 4.52 seconds
Started Sep 04 05:04:11 AM UTC 24
Finished Sep 04 05:04:17 AM UTC 24
Peak memory 229360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090486416 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4090486416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_alert.2470668334
Short name T93
Test name
Test status
Simulation time 29605155 ps
CPU time 1.64 seconds
Started Sep 04 05:04:22 AM UTC 24
Finished Sep 04 05:04:24 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470668334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.2470668334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_alert_test.3398465169
Short name T514
Test name
Test status
Simulation time 35142526 ps
CPU time 1.88 seconds
Started Sep 04 05:04:25 AM UTC 24
Finished Sep 04 05:04:28 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398465169 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3398465169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_disable.510810420
Short name T182
Test name
Test status
Simulation time 42905699 ps
CPU time 1 seconds
Started Sep 04 05:04:24 AM UTC 24
Finished Sep 04 05:04:26 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510810420 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.510810420
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.2931564906
Short name T210
Test name
Test status
Simulation time 42821285 ps
CPU time 1.99 seconds
Started Sep 04 05:04:25 AM UTC 24
Finished Sep 04 05:04:28 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931564906 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.2931564906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_err.914003567
Short name T202
Test name
Test status
Simulation time 19680232 ps
CPU time 1.31 seconds
Started Sep 04 05:04:22 AM UTC 24
Finished Sep 04 05:04:24 AM UTC 24
Peak memory 246148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914003567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.edn_err.914003567
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_genbits.475973296
Short name T295
Test name
Test status
Simulation time 42186388 ps
CPU time 1.74 seconds
Started Sep 04 05:04:18 AM UTC 24
Finished Sep 04 05:04:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475973296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_genbits.475973296
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_intr.1295859421
Short name T510
Test name
Test status
Simulation time 20994981 ps
CPU time 1.58 seconds
Started Sep 04 05:04:20 AM UTC 24
Finished Sep 04 05:04:23 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295859421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.1295859421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_smoke.3737754518
Short name T459
Test name
Test status
Simulation time 29825437 ps
CPU time 1.39 seconds
Started Sep 04 05:04:18 AM UTC 24
Finished Sep 04 05:04:21 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737754518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.3737754518
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_stress_all.3475745313
Short name T512
Test name
Test status
Simulation time 615733337 ps
CPU time 5.76 seconds
Started Sep 04 05:04:19 AM UTC 24
Finished Sep 04 05:04:26 AM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475745313 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3475745313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.4165756288
Short name T233
Test name
Test status
Simulation time 6138471196 ps
CPU time 78.53 seconds
Started Sep 04 05:04:20 AM UTC 24
Finished Sep 04 05:05:41 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4165756288 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all
_with_rand_reset.4165756288
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_alert_test.2584257094
Short name T229
Test name
Test status
Simulation time 54390542 ps
CPU time 1.31 seconds
Started Sep 04 05:00:07 AM UTC 24
Finished Sep 04 05:00:09 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584257094 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2584257094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_disable.23695083
Short name T52
Test name
Test status
Simulation time 29625714 ps
CPU time 1.07 seconds
Started Sep 04 05:00:06 AM UTC 24
Finished Sep 04 05:00:09 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23695083 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.23695083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.4090191589
Short name T87
Test name
Test status
Simulation time 53479466 ps
CPU time 1.61 seconds
Started Sep 04 05:00:07 AM UTC 24
Finished Sep 04 05:00:09 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090191589 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.4090191589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_err.1202042275
Short name T9
Test name
Test status
Simulation time 23356250 ps
CPU time 1.36 seconds
Started Sep 04 05:00:06 AM UTC 24
Finished Sep 04 05:00:09 AM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202042275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.1202042275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_genbits.3864652022
Short name T45
Test name
Test status
Simulation time 79056958 ps
CPU time 3.64 seconds
Started Sep 04 05:00:00 AM UTC 24
Finished Sep 04 05:00:05 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864652022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3864652022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_intr.2265657032
Short name T31
Test name
Test status
Simulation time 30556762 ps
CPU time 1.31 seconds
Started Sep 04 05:00:01 AM UTC 24
Finished Sep 04 05:00:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265657032 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.2265657032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_regwen.1878603368
Short name T303
Test name
Test status
Simulation time 19630279 ps
CPU time 1.32 seconds
Started Sep 04 05:00:00 AM UTC 24
Finished Sep 04 05:00:02 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878603368 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_regwen.1878603368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_sec_cm.3824574242
Short name T59
Test name
Test status
Simulation time 451241421 ps
CPU time 6.54 seconds
Started Sep 04 05:00:07 AM UTC 24
Finished Sep 04 05:00:14 AM UTC 24
Peak memory 260452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824574242 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3824574242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_smoke.1378675717
Short name T346
Test name
Test status
Simulation time 80748427 ps
CPU time 1.44 seconds
Started Sep 04 05:00:00 AM UTC 24
Finished Sep 04 05:00:02 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378675717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.1378675717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/4.edn_stress_all.1325056731
Short name T103
Test name
Test status
Simulation time 2767270431 ps
CPU time 4.77 seconds
Started Sep 04 05:00:01 AM UTC 24
Finished Sep 04 05:00:11 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325056731 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1325056731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_alert.4000375562
Short name T141
Test name
Test status
Simulation time 67230398 ps
CPU time 1.63 seconds
Started Sep 04 05:04:29 AM UTC 24
Finished Sep 04 05:04:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000375562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.4000375562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_alert_test.3057671813
Short name T520
Test name
Test status
Simulation time 53515514 ps
CPU time 1.43 seconds
Started Sep 04 05:04:34 AM UTC 24
Finished Sep 04 05:04:37 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057671813 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3057671813
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_disable.2925874688
Short name T214
Test name
Test status
Simulation time 13085318 ps
CPU time 1.28 seconds
Started Sep 04 05:04:33 AM UTC 24
Finished Sep 04 05:04:36 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925874688 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2925874688
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.3793089674
Short name T518
Test name
Test status
Simulation time 78746546 ps
CPU time 1.37 seconds
Started Sep 04 05:04:33 AM UTC 24
Finished Sep 04 05:04:36 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793089674 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.3793089674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_err.2052223204
Short name T138
Test name
Test status
Simulation time 27196570 ps
CPU time 1.95 seconds
Started Sep 04 05:04:30 AM UTC 24
Finished Sep 04 05:04:34 AM UTC 24
Peak memory 243856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052223204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.2052223204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_genbits.119819619
Short name T296
Test name
Test status
Simulation time 288933124 ps
CPU time 5.8 seconds
Started Sep 04 05:04:27 AM UTC 24
Finished Sep 04 05:04:34 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119819619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_genbits.119819619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_intr.4080528367
Short name T516
Test name
Test status
Simulation time 27565764 ps
CPU time 1.47 seconds
Started Sep 04 05:04:29 AM UTC 24
Finished Sep 04 05:04:32 AM UTC 24
Peak memory 237824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080528367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.4080528367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_smoke.3494135819
Short name T515
Test name
Test status
Simulation time 30249789 ps
CPU time 1.44 seconds
Started Sep 04 05:04:27 AM UTC 24
Finished Sep 04 05:04:30 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494135819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.3494135819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/40.edn_stress_all.314980319
Short name T517
Test name
Test status
Simulation time 209725497 ps
CPU time 5.52 seconds
Started Sep 04 05:04:27 AM UTC 24
Finished Sep 04 05:04:34 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314980319 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.314980319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_alert.2964481904
Short name T184
Test name
Test status
Simulation time 55904693 ps
CPU time 1.79 seconds
Started Sep 04 05:04:38 AM UTC 24
Finished Sep 04 05:04:41 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964481904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.2964481904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_alert_test.1438241376
Short name T527
Test name
Test status
Simulation time 209938223 ps
CPU time 1.36 seconds
Started Sep 04 05:04:42 AM UTC 24
Finished Sep 04 05:04:44 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438241376 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1438241376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_disable.2826909912
Short name T524
Test name
Test status
Simulation time 42119944 ps
CPU time 1.26 seconds
Started Sep 04 05:04:41 AM UTC 24
Finished Sep 04 05:04:43 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826909912 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2826909912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.1772048431
Short name T526
Test name
Test status
Simulation time 59493264 ps
CPU time 1.89 seconds
Started Sep 04 05:04:41 AM UTC 24
Finished Sep 04 05:04:44 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772048431 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.1772048431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_err.1444106619
Short name T523
Test name
Test status
Simulation time 35862556 ps
CPU time 1.59 seconds
Started Sep 04 05:04:39 AM UTC 24
Finished Sep 04 05:04:41 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444106619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.1444106619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_genbits.1501811239
Short name T521
Test name
Test status
Simulation time 74290258 ps
CPU time 2 seconds
Started Sep 04 05:04:35 AM UTC 24
Finished Sep 04 05:04:38 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501811239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1501811239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_intr.4084331968
Short name T522
Test name
Test status
Simulation time 35822740 ps
CPU time 1.26 seconds
Started Sep 04 05:04:38 AM UTC 24
Finished Sep 04 05:04:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084331968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.4084331968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_smoke.3909321119
Short name T519
Test name
Test status
Simulation time 28936444 ps
CPU time 1.32 seconds
Started Sep 04 05:04:34 AM UTC 24
Finished Sep 04 05:04:37 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909321119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.3909321119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/41.edn_stress_all.1665989508
Short name T525
Test name
Test status
Simulation time 220486034 ps
CPU time 5.76 seconds
Started Sep 04 05:04:37 AM UTC 24
Finished Sep 04 05:04:43 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665989508 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1665989508
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_alert.2794077713
Short name T531
Test name
Test status
Simulation time 85370429 ps
CPU time 1.67 seconds
Started Sep 04 05:04:47 AM UTC 24
Finished Sep 04 05:04:50 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794077713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_alert.2794077713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_alert_test.3790737711
Short name T535
Test name
Test status
Simulation time 19460939 ps
CPU time 1.37 seconds
Started Sep 04 05:04:51 AM UTC 24
Finished Sep 04 05:04:53 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790737711 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3790737711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_disable.2955908387
Short name T533
Test name
Test status
Simulation time 23985250 ps
CPU time 1.36 seconds
Started Sep 04 05:04:49 AM UTC 24
Finished Sep 04 05:04:51 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955908387 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2955908387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.275280181
Short name T536
Test name
Test status
Simulation time 34126798 ps
CPU time 1.79 seconds
Started Sep 04 05:04:51 AM UTC 24
Finished Sep 04 05:04:53 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275280181 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.275280181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_err.1299742129
Short name T209
Test name
Test status
Simulation time 19379581 ps
CPU time 1.52 seconds
Started Sep 04 05:04:48 AM UTC 24
Finished Sep 04 05:04:50 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299742129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.1299742129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_genbits.3038303381
Short name T529
Test name
Test status
Simulation time 62492708 ps
CPU time 1.68 seconds
Started Sep 04 05:04:44 AM UTC 24
Finished Sep 04 05:04:47 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038303381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3038303381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_intr.3399320513
Short name T530
Test name
Test status
Simulation time 25617314 ps
CPU time 1.47 seconds
Started Sep 04 05:04:45 AM UTC 24
Finished Sep 04 05:04:48 AM UTC 24
Peak memory 236704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399320513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.3399320513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_smoke.247456725
Short name T528
Test name
Test status
Simulation time 26486571 ps
CPU time 1.24 seconds
Started Sep 04 05:04:44 AM UTC 24
Finished Sep 04 05:04:46 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247456725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_smoke.247456725
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/42.edn_stress_all.1907996670
Short name T532
Test name
Test status
Simulation time 294167742 ps
CPU time 5.38 seconds
Started Sep 04 05:04:44 AM UTC 24
Finished Sep 04 05:04:51 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907996670 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1907996670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_alert.3767375410
Short name T131
Test name
Test status
Simulation time 24329701 ps
CPU time 1.75 seconds
Started Sep 04 05:04:54 AM UTC 24
Finished Sep 04 05:04:57 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767375410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.3767375410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_alert_test.140660845
Short name T542
Test name
Test status
Simulation time 40337521 ps
CPU time 1.45 seconds
Started Sep 04 05:04:58 AM UTC 24
Finished Sep 04 05:05:01 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140660845 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.140660845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_disable.1365147215
Short name T539
Test name
Test status
Simulation time 22191325 ps
CPU time 1.17 seconds
Started Sep 04 05:04:57 AM UTC 24
Finished Sep 04 05:04:59 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365147215 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1365147215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.3758595317
Short name T540
Test name
Test status
Simulation time 58089770 ps
CPU time 1.57 seconds
Started Sep 04 05:04:57 AM UTC 24
Finished Sep 04 05:05:00 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758595317 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.3758595317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_err.4119236280
Short name T169
Test name
Test status
Simulation time 52121781 ps
CPU time 1.58 seconds
Started Sep 04 05:04:55 AM UTC 24
Finished Sep 04 05:04:58 AM UTC 24
Peak memory 242184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119236280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.4119236280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_genbits.1540365208
Short name T538
Test name
Test status
Simulation time 286409584 ps
CPU time 6.16 seconds
Started Sep 04 05:04:52 AM UTC 24
Finished Sep 04 05:04:59 AM UTC 24
Peak memory 231488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540365208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1540365208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_intr.409858632
Short name T98
Test name
Test status
Simulation time 31849188 ps
CPU time 1.27 seconds
Started Sep 04 05:04:54 AM UTC 24
Finished Sep 04 05:04:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409858632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.409858632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_smoke.741422643
Short name T534
Test name
Test status
Simulation time 22080636 ps
CPU time 1.08 seconds
Started Sep 04 05:04:51 AM UTC 24
Finished Sep 04 05:04:53 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741422643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.edn_smoke.741422643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_stress_all.2444110711
Short name T537
Test name
Test status
Simulation time 166436572 ps
CPU time 1.55 seconds
Started Sep 04 05:04:52 AM UTC 24
Finished Sep 04 05:04:54 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444110711 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2444110711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.3829247244
Short name T578
Test name
Test status
Simulation time 9510467689 ps
CPU time 62.3 seconds
Started Sep 04 05:04:54 AM UTC 24
Finished Sep 04 05:05:58 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3829247244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all
_with_rand_reset.3829247244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_alert.3448786191
Short name T546
Test name
Test status
Simulation time 28794362 ps
CPU time 1.87 seconds
Started Sep 04 05:05:04 AM UTC 24
Finished Sep 04 05:05:07 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448786191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.3448786191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_alert_test.3985916418
Short name T251
Test name
Test status
Simulation time 52675999 ps
CPU time 0.99 seconds
Started Sep 04 05:05:07 AM UTC 24
Finished Sep 04 05:05:09 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985916418 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3985916418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_disable.1256375578
Short name T222
Test name
Test status
Simulation time 15229884 ps
CPU time 1.18 seconds
Started Sep 04 05:05:05 AM UTC 24
Finished Sep 04 05:05:07 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256375578 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1256375578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.859211878
Short name T250
Test name
Test status
Simulation time 108708752 ps
CPU time 1.56 seconds
Started Sep 04 05:05:05 AM UTC 24
Finished Sep 04 05:05:07 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859211878 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.859211878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_err.1143823495
Short name T545
Test name
Test status
Simulation time 41293878 ps
CPU time 1.3 seconds
Started Sep 04 05:05:04 AM UTC 24
Finished Sep 04 05:05:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143823495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.1143823495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_genbits.613378412
Short name T327
Test name
Test status
Simulation time 61143626 ps
CPU time 1.41 seconds
Started Sep 04 05:05:00 AM UTC 24
Finished Sep 04 05:05:03 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613378412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_genbits.613378412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_intr.1253101469
Short name T99
Test name
Test status
Simulation time 29698875 ps
CPU time 1.32 seconds
Started Sep 04 05:05:02 AM UTC 24
Finished Sep 04 05:05:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253101469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.1253101469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_smoke.2213229466
Short name T543
Test name
Test status
Simulation time 13680539 ps
CPU time 1.44 seconds
Started Sep 04 05:05:00 AM UTC 24
Finished Sep 04 05:05:03 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213229466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.2213229466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/44.edn_stress_all.1324089466
Short name T544
Test name
Test status
Simulation time 191390247 ps
CPU time 2.76 seconds
Started Sep 04 05:05:01 AM UTC 24
Finished Sep 04 05:05:04 AM UTC 24
Peak memory 227740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324089466 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1324089466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_alert.3128545490
Short name T167
Test name
Test status
Simulation time 53042052 ps
CPU time 1.5 seconds
Started Sep 04 05:05:12 AM UTC 24
Finished Sep 04 05:05:15 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128545490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.3128545490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_alert_test.3084271994
Short name T547
Test name
Test status
Simulation time 14822564 ps
CPU time 1.24 seconds
Started Sep 04 05:05:17 AM UTC 24
Finished Sep 04 05:05:19 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084271994 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3084271994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_disable.1049939251
Short name T256
Test name
Test status
Simulation time 13793470 ps
CPU time 1.33 seconds
Started Sep 04 05:05:13 AM UTC 24
Finished Sep 04 05:05:16 AM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049939251 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1049939251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.272534873
Short name T257
Test name
Test status
Simulation time 169653036 ps
CPU time 1.72 seconds
Started Sep 04 05:05:16 AM UTC 24
Finished Sep 04 05:05:18 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272534873 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.272534873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_err.1096753837
Short name T170
Test name
Test status
Simulation time 33773793 ps
CPU time 1.54 seconds
Started Sep 04 05:05:13 AM UTC 24
Finished Sep 04 05:05:16 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096753837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.1096753837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_intr.2756712848
Short name T255
Test name
Test status
Simulation time 46339477 ps
CPU time 1.33 seconds
Started Sep 04 05:05:10 AM UTC 24
Finished Sep 04 05:05:13 AM UTC 24
Peak memory 236704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756712848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.2756712848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_smoke.1412026535
Short name T252
Test name
Test status
Simulation time 32552950 ps
CPU time 1.41 seconds
Started Sep 04 05:05:07 AM UTC 24
Finished Sep 04 05:05:09 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412026535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.1412026535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/45.edn_stress_all.664619186
Short name T253
Test name
Test status
Simulation time 48930906 ps
CPU time 2.04 seconds
Started Sep 04 05:05:08 AM UTC 24
Finished Sep 04 05:05:11 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664619186 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.664619186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_alert.1374301199
Short name T188
Test name
Test status
Simulation time 160021635 ps
CPU time 1.32 seconds
Started Sep 04 05:05:25 AM UTC 24
Finished Sep 04 05:05:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374301199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.1374301199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_alert_test.100236298
Short name T554
Test name
Test status
Simulation time 25276957 ps
CPU time 1.21 seconds
Started Sep 04 05:05:29 AM UTC 24
Finished Sep 04 05:05:32 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100236298 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.100236298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_disable.271038797
Short name T552
Test name
Test status
Simulation time 36246731 ps
CPU time 1.31 seconds
Started Sep 04 05:05:27 AM UTC 24
Finished Sep 04 05:05:30 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271038797 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.271038797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.4273646128
Short name T553
Test name
Test status
Simulation time 461674780 ps
CPU time 1.86 seconds
Started Sep 04 05:05:28 AM UTC 24
Finished Sep 04 05:05:31 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273646128 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.4273646128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_err.3277519814
Short name T551
Test name
Test status
Simulation time 18720640 ps
CPU time 1.67 seconds
Started Sep 04 05:05:26 AM UTC 24
Finished Sep 04 05:05:29 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277519814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.3277519814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_genbits.1007060542
Short name T344
Test name
Test status
Simulation time 84148358 ps
CPU time 1.89 seconds
Started Sep 04 05:05:19 AM UTC 24
Finished Sep 04 05:05:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007060542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1007060542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_intr.3274885139
Short name T549
Test name
Test status
Simulation time 23979405 ps
CPU time 1.48 seconds
Started Sep 04 05:05:23 AM UTC 24
Finished Sep 04 05:05:25 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274885139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.3274885139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_smoke.68088673
Short name T548
Test name
Test status
Simulation time 18074855 ps
CPU time 1.35 seconds
Started Sep 04 05:05:17 AM UTC 24
Finished Sep 04 05:05:19 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68088673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_smoke.68088673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_stress_all.1114158976
Short name T550
Test name
Test status
Simulation time 364886756 ps
CPU time 5.98 seconds
Started Sep 04 05:05:20 AM UTC 24
Finished Sep 04 05:05:27 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114158976 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1114158976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.980232311
Short name T235
Test name
Test status
Simulation time 5525019257 ps
CPU time 36.26 seconds
Started Sep 04 05:05:20 AM UTC 24
Finished Sep 04 05:05:58 AM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=980232311 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_
with_rand_reset.980232311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_alert.1850505042
Short name T559
Test name
Test status
Simulation time 369807447 ps
CPU time 2.25 seconds
Started Sep 04 05:05:35 AM UTC 24
Finished Sep 04 05:05:38 AM UTC 24
Peak memory 230084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850505042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.1850505042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_alert_test.2948146914
Short name T564
Test name
Test status
Simulation time 17944479 ps
CPU time 1.19 seconds
Started Sep 04 05:05:39 AM UTC 24
Finished Sep 04 05:05:41 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948146914 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2948146914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_disable.1187767954
Short name T561
Test name
Test status
Simulation time 87981103 ps
CPU time 1.27 seconds
Started Sep 04 05:05:37 AM UTC 24
Finished Sep 04 05:05:39 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187767954 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1187767954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.974864282
Short name T562
Test name
Test status
Simulation time 49004865 ps
CPU time 1.56 seconds
Started Sep 04 05:05:38 AM UTC 24
Finished Sep 04 05:05:41 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974864282 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.974864282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_err.4158101644
Short name T560
Test name
Test status
Simulation time 23473367 ps
CPU time 1.38 seconds
Started Sep 04 05:05:36 AM UTC 24
Finished Sep 04 05:05:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158101644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.4158101644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_intr.3033996756
Short name T558
Test name
Test status
Simulation time 108974097 ps
CPU time 1.45 seconds
Started Sep 04 05:05:35 AM UTC 24
Finished Sep 04 05:05:37 AM UTC 24
Peak memory 237148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033996756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.3033996756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_smoke.4019215539
Short name T555
Test name
Test status
Simulation time 77011422 ps
CPU time 1.32 seconds
Started Sep 04 05:05:30 AM UTC 24
Finished Sep 04 05:05:33 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019215539 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.4019215539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/47.edn_stress_all.466100870
Short name T557
Test name
Test status
Simulation time 90962434 ps
CPU time 2.2 seconds
Started Sep 04 05:05:33 AM UTC 24
Finished Sep 04 05:05:36 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466100870 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.466100870
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_alert.2056197275
Short name T142
Test name
Test status
Simulation time 86961952 ps
CPU time 1.73 seconds
Started Sep 04 05:05:42 AM UTC 24
Finished Sep 04 05:05:45 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056197275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.2056197275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_alert_test.2812305730
Short name T569
Test name
Test status
Simulation time 22699611 ps
CPU time 1.19 seconds
Started Sep 04 05:05:47 AM UTC 24
Finished Sep 04 05:05:49 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812305730 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2812305730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_disable.2008655186
Short name T567
Test name
Test status
Simulation time 30110680 ps
CPU time 1.24 seconds
Started Sep 04 05:05:46 AM UTC 24
Finished Sep 04 05:05:48 AM UTC 24
Peak memory 226308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008655186 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2008655186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.1947798745
Short name T568
Test name
Test status
Simulation time 119252795 ps
CPU time 1.59 seconds
Started Sep 04 05:05:46 AM UTC 24
Finished Sep 04 05:05:48 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947798745 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.1947798745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_err.1471342404
Short name T159
Test name
Test status
Simulation time 76079088 ps
CPU time 1.61 seconds
Started Sep 04 05:05:43 AM UTC 24
Finished Sep 04 05:05:46 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471342404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.1471342404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_genbits.3217635326
Short name T565
Test name
Test status
Simulation time 104557255 ps
CPU time 1.72 seconds
Started Sep 04 05:05:40 AM UTC 24
Finished Sep 04 05:05:43 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217635326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3217635326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_intr.999322482
Short name T566
Test name
Test status
Simulation time 28969218 ps
CPU time 1.26 seconds
Started Sep 04 05:05:42 AM UTC 24
Finished Sep 04 05:05:45 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999322482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.999322482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_smoke.1665092385
Short name T563
Test name
Test status
Simulation time 46371740 ps
CPU time 1.12 seconds
Started Sep 04 05:05:39 AM UTC 24
Finished Sep 04 05:05:41 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665092385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.1665092385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_stress_all.3757659953
Short name T318
Test name
Test status
Simulation time 139204730 ps
CPU time 4.44 seconds
Started Sep 04 05:05:41 AM UTC 24
Finished Sep 04 05:05:47 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757659953 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3757659953
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.2958861887
Short name T723
Test name
Test status
Simulation time 17475913513 ps
CPU time 93.13 seconds
Started Sep 04 05:05:42 AM UTC 24
Finished Sep 04 05:07:17 AM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2958861887 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all
_with_rand_reset.2958861887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_alert.3225118792
Short name T574
Test name
Test status
Simulation time 67241795 ps
CPU time 1.64 seconds
Started Sep 04 05:05:51 AM UTC 24
Finished Sep 04 05:05:54 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225118792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.3225118792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_alert_test.2888495510
Short name T576
Test name
Test status
Simulation time 15542393 ps
CPU time 1.36 seconds
Started Sep 04 05:05:54 AM UTC 24
Finished Sep 04 05:05:57 AM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888495510 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2888495510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.1157960912
Short name T577
Test name
Test status
Simulation time 107725340 ps
CPU time 1.56 seconds
Started Sep 04 05:05:54 AM UTC 24
Finished Sep 04 05:05:57 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157960912 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.1157960912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_err.2028235937
Short name T575
Test name
Test status
Simulation time 21993040 ps
CPU time 1.29 seconds
Started Sep 04 05:05:52 AM UTC 24
Finished Sep 04 05:05:55 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028235937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.2028235937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_genbits.3248971380
Short name T572
Test name
Test status
Simulation time 72834974 ps
CPU time 2.06 seconds
Started Sep 04 05:05:49 AM UTC 24
Finished Sep 04 05:05:52 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248971380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3248971380
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_intr.2694803601
Short name T573
Test name
Test status
Simulation time 37233616 ps
CPU time 1.51 seconds
Started Sep 04 05:05:51 AM UTC 24
Finished Sep 04 05:05:53 AM UTC 24
Peak memory 237824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694803601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.2694803601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_smoke.3977872659
Short name T570
Test name
Test status
Simulation time 67130346 ps
CPU time 1.43 seconds
Started Sep 04 05:05:48 AM UTC 24
Finished Sep 04 05:05:50 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977872659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.3977872659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_stress_all.2305854665
Short name T571
Test name
Test status
Simulation time 138452197 ps
CPU time 2.02 seconds
Started Sep 04 05:05:49 AM UTC 24
Finished Sep 04 05:05:52 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305854665 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2305854665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.481146004
Short name T237
Test name
Test status
Simulation time 1740823832 ps
CPU time 45.87 seconds
Started Sep 04 05:05:50 AM UTC 24
Finished Sep 04 05:06:37 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=481146004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_
with_rand_reset.481146004
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_alert.3129676816
Short name T110
Test name
Test status
Simulation time 28446740 ps
CPU time 2.04 seconds
Started Sep 04 05:00:10 AM UTC 24
Finished Sep 04 05:00:13 AM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129676816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.3129676816
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_alert_test.3880519611
Short name T347
Test name
Test status
Simulation time 15635287 ps
CPU time 1.39 seconds
Started Sep 04 05:00:11 AM UTC 24
Finished Sep 04 05:00:14 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880519611 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3880519611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_disable.1132087521
Short name T74
Test name
Test status
Simulation time 35257015 ps
CPU time 1.25 seconds
Started Sep 04 05:00:10 AM UTC 24
Finished Sep 04 05:00:12 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132087521 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1132087521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.549868670
Short name T21
Test name
Test status
Simulation time 59256722 ps
CPU time 1.55 seconds
Started Sep 04 05:00:10 AM UTC 24
Finished Sep 04 05:00:13 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549868670 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.549868670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_err.3475428769
Short name T171
Test name
Test status
Simulation time 29017966 ps
CPU time 1.29 seconds
Started Sep 04 05:00:10 AM UTC 24
Finished Sep 04 05:00:12 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475428769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.3475428769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_genbits.1531980414
Short name T285
Test name
Test status
Simulation time 59556655 ps
CPU time 1.54 seconds
Started Sep 04 05:00:08 AM UTC 24
Finished Sep 04 05:00:10 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531980414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1531980414
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_intr.3840976494
Short name T82
Test name
Test status
Simulation time 42167959 ps
CPU time 1.25 seconds
Started Sep 04 05:00:10 AM UTC 24
Finished Sep 04 05:00:12 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840976494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.3840976494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_regwen.3259426555
Short name T230
Test name
Test status
Simulation time 26486944 ps
CPU time 1.3 seconds
Started Sep 04 05:00:07 AM UTC 24
Finished Sep 04 05:00:09 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259426555 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.3259426555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_smoke.4007732905
Short name T228
Test name
Test status
Simulation time 24199458 ps
CPU time 1.27 seconds
Started Sep 04 05:00:07 AM UTC 24
Finished Sep 04 05:00:09 AM UTC 24
Peak memory 226140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007732905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.4007732905
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_stress_all.2484544053
Short name T100
Test name
Test status
Simulation time 377489964 ps
CPU time 6.59 seconds
Started Sep 04 05:00:08 AM UTC 24
Finished Sep 04 05:00:16 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484544053 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2484544053
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.3596067165
Short name T206
Test name
Test status
Simulation time 7731132489 ps
CPU time 136.37 seconds
Started Sep 04 05:00:09 AM UTC 24
Finished Sep 04 05:02:28 AM UTC 24
Peak memory 234292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3596067165 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.3596067165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/50.edn_alert.1631608221
Short name T135
Test name
Test status
Simulation time 74413263 ps
CPU time 1.67 seconds
Started Sep 04 05:05:56 AM UTC 24
Finished Sep 04 05:06:00 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631608221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 50.edn_alert.1631608221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/50.edn_err.1568916239
Short name T119
Test name
Test status
Simulation time 191963826 ps
CPU time 1.42 seconds
Started Sep 04 05:05:57 AM UTC 24
Finished Sep 04 05:06:00 AM UTC 24
Peak memory 230392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568916239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.1568916239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/50.edn_genbits.3104355407
Short name T579
Test name
Test status
Simulation time 100261816 ps
CPU time 1.74 seconds
Started Sep 04 05:05:55 AM UTC 24
Finished Sep 04 05:05:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104355407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3104355407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/51.edn_alert.3674419636
Short name T582
Test name
Test status
Simulation time 74674631 ps
CPU time 1.75 seconds
Started Sep 04 05:05:59 AM UTC 24
Finished Sep 04 05:06:02 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674419636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.3674419636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/51.edn_err.502855963
Short name T581
Test name
Test status
Simulation time 85521103 ps
CPU time 1.28 seconds
Started Sep 04 05:05:59 AM UTC 24
Finished Sep 04 05:06:01 AM UTC 24
Peak memory 246148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502855963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 51.edn_err.502855963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/51.edn_genbits.498395799
Short name T580
Test name
Test status
Simulation time 30739519 ps
CPU time 1.84 seconds
Started Sep 04 05:05:57 AM UTC 24
Finished Sep 04 05:06:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498395799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 51.edn_genbits.498395799
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/52.edn_alert.3378482346
Short name T585
Test name
Test status
Simulation time 36752113 ps
CPU time 1.55 seconds
Started Sep 04 05:06:01 AM UTC 24
Finished Sep 04 05:06:04 AM UTC 24
Peak memory 230444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378482346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 52.edn_alert.3378482346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/52.edn_err.1863274671
Short name T584
Test name
Test status
Simulation time 25646243 ps
CPU time 1.4 seconds
Started Sep 04 05:06:01 AM UTC 24
Finished Sep 04 05:06:03 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863274671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.1863274671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/52.edn_genbits.2530471656
Short name T583
Test name
Test status
Simulation time 124599744 ps
CPU time 1.61 seconds
Started Sep 04 05:06:00 AM UTC 24
Finished Sep 04 05:06:02 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530471656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2530471656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/53.edn_alert.3639500066
Short name T586
Test name
Test status
Simulation time 25246694 ps
CPU time 1.5 seconds
Started Sep 04 05:06:02 AM UTC 24
Finished Sep 04 05:06:04 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639500066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.3639500066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/53.edn_err.3567658966
Short name T587
Test name
Test status
Simulation time 22820555 ps
CPU time 1.59 seconds
Started Sep 04 05:06:03 AM UTC 24
Finished Sep 04 05:06:06 AM UTC 24
Peak memory 237036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567658966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.3567658966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/53.edn_genbits.783171214
Short name T589
Test name
Test status
Simulation time 101530955 ps
CPU time 3.53 seconds
Started Sep 04 05:06:02 AM UTC 24
Finished Sep 04 05:06:07 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783171214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 53.edn_genbits.783171214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/54.edn_alert.229695879
Short name T590
Test name
Test status
Simulation time 83280377 ps
CPU time 1.64 seconds
Started Sep 04 05:06:04 AM UTC 24
Finished Sep 04 05:06:07 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229695879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 54.edn_alert.229695879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/54.edn_err.1307227915
Short name T145
Test name
Test status
Simulation time 32236907 ps
CPU time 1.81 seconds
Started Sep 04 05:06:04 AM UTC 24
Finished Sep 04 05:06:07 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307227915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.1307227915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/54.edn_genbits.2949535564
Short name T588
Test name
Test status
Simulation time 155222419 ps
CPU time 1.84 seconds
Started Sep 04 05:06:03 AM UTC 24
Finished Sep 04 05:06:06 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949535564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2949535564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/55.edn_alert.2769332927
Short name T592
Test name
Test status
Simulation time 400804247 ps
CPU time 2.04 seconds
Started Sep 04 05:06:06 AM UTC 24
Finished Sep 04 05:06:09 AM UTC 24
Peak memory 230084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769332927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.2769332927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/55.edn_err.562784530
Short name T591
Test name
Test status
Simulation time 26524495 ps
CPU time 1.17 seconds
Started Sep 04 05:06:06 AM UTC 24
Finished Sep 04 05:06:09 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562784530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 55.edn_err.562784530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/55.edn_genbits.1637752552
Short name T329
Test name
Test status
Simulation time 85616557 ps
CPU time 2.06 seconds
Started Sep 04 05:06:05 AM UTC 24
Finished Sep 04 05:06:08 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637752552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1637752552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/56.edn_err.813229150
Short name T594
Test name
Test status
Simulation time 31236273 ps
CPU time 1.3 seconds
Started Sep 04 05:06:08 AM UTC 24
Finished Sep 04 05:06:10 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813229150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 56.edn_err.813229150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/56.edn_genbits.2106012542
Short name T593
Test name
Test status
Simulation time 111847805 ps
CPU time 1.83 seconds
Started Sep 04 05:06:06 AM UTC 24
Finished Sep 04 05:06:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106012542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2106012542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/57.edn_alert.3942239892
Short name T156
Test name
Test status
Simulation time 28988783 ps
CPU time 1.84 seconds
Started Sep 04 05:06:10 AM UTC 24
Finished Sep 04 05:06:13 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942239892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.3942239892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/57.edn_err.1980832017
Short name T595
Test name
Test status
Simulation time 23595889 ps
CPU time 1.68 seconds
Started Sep 04 05:06:10 AM UTC 24
Finished Sep 04 05:06:13 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980832017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.1980832017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/57.edn_genbits.1699596529
Short name T345
Test name
Test status
Simulation time 111755723 ps
CPU time 2.11 seconds
Started Sep 04 05:06:08 AM UTC 24
Finished Sep 04 05:06:11 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699596529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1699596529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/58.edn_alert.3361719550
Short name T596
Test name
Test status
Simulation time 78980722 ps
CPU time 1.66 seconds
Started Sep 04 05:06:11 AM UTC 24
Finished Sep 04 05:06:14 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361719550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.3361719550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/58.edn_err.1403633774
Short name T211
Test name
Test status
Simulation time 30199974 ps
CPU time 1.79 seconds
Started Sep 04 05:06:11 AM UTC 24
Finished Sep 04 05:06:14 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403633774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.1403633774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/58.edn_genbits.3467642627
Short name T598
Test name
Test status
Simulation time 96752667 ps
CPU time 2.19 seconds
Started Sep 04 05:06:11 AM UTC 24
Finished Sep 04 05:06:14 AM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467642627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3467642627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/59.edn_alert.2396054917
Short name T599
Test name
Test status
Simulation time 26841827 ps
CPU time 1.74 seconds
Started Sep 04 05:06:11 AM UTC 24
Finished Sep 04 05:06:14 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396054917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.2396054917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/59.edn_err.2107388
Short name T600
Test name
Test status
Simulation time 29134277 ps
CPU time 1.5 seconds
Started Sep 04 05:06:12 AM UTC 24
Finished Sep 04 05:06:15 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 59.edn_err.2107388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/59.edn_genbits.3554823498
Short name T597
Test name
Test status
Simulation time 46591847 ps
CPU time 1.7 seconds
Started Sep 04 05:06:11 AM UTC 24
Finished Sep 04 05:06:14 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554823498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3554823498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_alert_test.1246132813
Short name T348
Test name
Test status
Simulation time 21288800 ps
CPU time 1.09 seconds
Started Sep 04 05:00:15 AM UTC 24
Finished Sep 04 05:00:17 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246132813 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1246132813
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_disable.196735619
Short name T83
Test name
Test status
Simulation time 11286477 ps
CPU time 1.39 seconds
Started Sep 04 05:00:15 AM UTC 24
Finished Sep 04 05:00:17 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196735619 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.196735619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_err.2776273718
Short name T176
Test name
Test status
Simulation time 72892489 ps
CPU time 1.48 seconds
Started Sep 04 05:00:15 AM UTC 24
Finished Sep 04 05:00:17 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776273718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.2776273718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_genbits.2026911788
Short name T70
Test name
Test status
Simulation time 23779457 ps
CPU time 1.4 seconds
Started Sep 04 05:00:14 AM UTC 24
Finished Sep 04 05:00:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026911788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2026911788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_intr.200724943
Short name T97
Test name
Test status
Simulation time 22596254 ps
CPU time 1.39 seconds
Started Sep 04 05:00:14 AM UTC 24
Finished Sep 04 05:00:16 AM UTC 24
Peak memory 228208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200724943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.200724943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_regwen.1709912549
Short name T307
Test name
Test status
Simulation time 51553533 ps
CPU time 1.32 seconds
Started Sep 04 05:00:11 AM UTC 24
Finished Sep 04 05:00:14 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709912549 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.1709912549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_smoke.2812724128
Short name T104
Test name
Test status
Simulation time 16706880 ps
CPU time 1.5 seconds
Started Sep 04 05:00:11 AM UTC 24
Finished Sep 04 05:00:14 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812724128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.2812724128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/6.edn_stress_all.3770627954
Short name T106
Test name
Test status
Simulation time 391495030 ps
CPU time 5.99 seconds
Started Sep 04 05:00:14 AM UTC 24
Finished Sep 04 05:00:21 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770627954 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3770627954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/60.edn_alert.3130297954
Short name T601
Test name
Test status
Simulation time 291294112 ps
CPU time 2.06 seconds
Started Sep 04 05:06:13 AM UTC 24
Finished Sep 04 05:06:17 AM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130297954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.3130297954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/60.edn_err.3626582015
Short name T602
Test name
Test status
Simulation time 26942609 ps
CPU time 1.59 seconds
Started Sep 04 05:06:14 AM UTC 24
Finished Sep 04 05:06:17 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626582015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.3626582015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/60.edn_genbits.1289801501
Short name T608
Test name
Test status
Simulation time 145352354 ps
CPU time 3.91 seconds
Started Sep 04 05:06:13 AM UTC 24
Finished Sep 04 05:06:18 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289801501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1289801501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/61.edn_alert.2412761779
Short name T607
Test name
Test status
Simulation time 197404577 ps
CPU time 1.8 seconds
Started Sep 04 05:06:15 AM UTC 24
Finished Sep 04 05:06:18 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412761779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.2412761779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/61.edn_err.3107013074
Short name T604
Test name
Test status
Simulation time 17935907 ps
CPU time 1.58 seconds
Started Sep 04 05:06:15 AM UTC 24
Finished Sep 04 05:06:18 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107013074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.3107013074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/61.edn_genbits.3877045708
Short name T603
Test name
Test status
Simulation time 52039492 ps
CPU time 2.33 seconds
Started Sep 04 05:06:14 AM UTC 24
Finished Sep 04 05:06:18 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877045708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3877045708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/62.edn_alert.3986001767
Short name T606
Test name
Test status
Simulation time 21457732 ps
CPU time 1.65 seconds
Started Sep 04 05:06:16 AM UTC 24
Finished Sep 04 05:06:18 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986001767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 62.edn_alert.3986001767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/62.edn_genbits.2720877821
Short name T605
Test name
Test status
Simulation time 47470607 ps
CPU time 1.67 seconds
Started Sep 04 05:06:15 AM UTC 24
Finished Sep 04 05:06:18 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720877821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2720877821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/63.edn_alert.3985466964
Short name T610
Test name
Test status
Simulation time 23297329 ps
CPU time 1.54 seconds
Started Sep 04 05:06:19 AM UTC 24
Finished Sep 04 05:06:21 AM UTC 24
Peak memory 230404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985466964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.3985466964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/63.edn_err.2537530479
Short name T139
Test name
Test status
Simulation time 36212773 ps
CPU time 1.62 seconds
Started Sep 04 05:06:19 AM UTC 24
Finished Sep 04 05:06:21 AM UTC 24
Peak memory 230344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537530479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.2537530479
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/63.edn_genbits.3946207995
Short name T609
Test name
Test status
Simulation time 45174834 ps
CPU time 1.61 seconds
Started Sep 04 05:06:18 AM UTC 24
Finished Sep 04 05:06:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946207995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3946207995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/64.edn_alert.2169549522
Short name T613
Test name
Test status
Simulation time 54009122 ps
CPU time 1.73 seconds
Started Sep 04 05:06:19 AM UTC 24
Finished Sep 04 05:06:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169549522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.2169549522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/64.edn_err.1935433208
Short name T133
Test name
Test status
Simulation time 27592527 ps
CPU time 1.6 seconds
Started Sep 04 05:06:19 AM UTC 24
Finished Sep 04 05:06:22 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935433208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.1935433208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/64.edn_genbits.573769510
Short name T611
Test name
Test status
Simulation time 91648264 ps
CPU time 1.59 seconds
Started Sep 04 05:06:19 AM UTC 24
Finished Sep 04 05:06:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573769510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 64.edn_genbits.573769510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/65.edn_alert.314837045
Short name T615
Test name
Test status
Simulation time 99651613 ps
CPU time 1.7 seconds
Started Sep 04 05:06:21 AM UTC 24
Finished Sep 04 05:06:24 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314837045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 65.edn_alert.314837045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/65.edn_err.2748065147
Short name T614
Test name
Test status
Simulation time 20372274 ps
CPU time 1.58 seconds
Started Sep 04 05:06:21 AM UTC 24
Finished Sep 04 05:06:24 AM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748065147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.2748065147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/65.edn_genbits.3857823006
Short name T612
Test name
Test status
Simulation time 123263865 ps
CPU time 1.48 seconds
Started Sep 04 05:06:19 AM UTC 24
Finished Sep 04 05:06:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857823006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3857823006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/66.edn_alert.2265594116
Short name T618
Test name
Test status
Simulation time 28658554 ps
CPU time 1.85 seconds
Started Sep 04 05:06:22 AM UTC 24
Finished Sep 04 05:06:25 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265594116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.2265594116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/66.edn_err.2145435814
Short name T127
Test name
Test status
Simulation time 38294205 ps
CPU time 1.99 seconds
Started Sep 04 05:06:22 AM UTC 24
Finished Sep 04 05:06:25 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145435814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.2145435814
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/66.edn_genbits.942603545
Short name T617
Test name
Test status
Simulation time 22753665 ps
CPU time 1.71 seconds
Started Sep 04 05:06:22 AM UTC 24
Finished Sep 04 05:06:25 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942603545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 66.edn_genbits.942603545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/67.edn_alert.3423092413
Short name T178
Test name
Test status
Simulation time 81190873 ps
CPU time 1.74 seconds
Started Sep 04 05:06:22 AM UTC 24
Finished Sep 04 05:06:25 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423092413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.3423092413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/67.edn_err.538206393
Short name T616
Test name
Test status
Simulation time 35161829 ps
CPU time 1.23 seconds
Started Sep 04 05:06:22 AM UTC 24
Finished Sep 04 05:06:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538206393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 67.edn_err.538206393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/67.edn_genbits.3296531704
Short name T619
Test name
Test status
Simulation time 33934045 ps
CPU time 2.02 seconds
Started Sep 04 05:06:22 AM UTC 24
Finished Sep 04 05:06:25 AM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296531704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3296531704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/68.edn_alert.2493209231
Short name T620
Test name
Test status
Simulation time 28161534 ps
CPU time 1.83 seconds
Started Sep 04 05:06:25 AM UTC 24
Finished Sep 04 05:06:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493209231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 68.edn_alert.2493209231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/68.edn_err.2536871767
Short name T120
Test name
Test status
Simulation time 32825526 ps
CPU time 1.54 seconds
Started Sep 04 05:06:26 AM UTC 24
Finished Sep 04 05:06:28 AM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536871767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 68.edn_err.2536871767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/69.edn_alert.2069858251
Short name T621
Test name
Test status
Simulation time 91591036 ps
CPU time 1.67 seconds
Started Sep 04 05:06:26 AM UTC 24
Finished Sep 04 05:06:28 AM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069858251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.2069858251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/69.edn_err.3805798318
Short name T622
Test name
Test status
Simulation time 157788449 ps
CPU time 1.76 seconds
Started Sep 04 05:06:26 AM UTC 24
Finished Sep 04 05:06:29 AM UTC 24
Peak memory 230424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805798318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.3805798318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/69.edn_genbits.1870494139
Short name T15
Test name
Test status
Simulation time 70009690 ps
CPU time 1.85 seconds
Started Sep 04 05:06:26 AM UTC 24
Finished Sep 04 05:06:29 AM UTC 24
Peak memory 228700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870494139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1870494139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_alert.3463060560
Short name T53
Test name
Test status
Simulation time 30668336 ps
CPU time 1.73 seconds
Started Sep 04 05:00:18 AM UTC 24
Finished Sep 04 05:00:21 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463060560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.3463060560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_disable.2476826385
Short name T192
Test name
Test status
Simulation time 13346827 ps
CPU time 1.26 seconds
Started Sep 04 05:00:20 AM UTC 24
Finished Sep 04 05:00:22 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476826385 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2476826385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.1573483333
Short name T75
Test name
Test status
Simulation time 364076825 ps
CPU time 1.78 seconds
Started Sep 04 05:00:21 AM UTC 24
Finished Sep 04 05:00:23 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573483333 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.1573483333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_err.2078365111
Short name T107
Test name
Test status
Simulation time 20426350 ps
CPU time 1.62 seconds
Started Sep 04 05:00:18 AM UTC 24
Finished Sep 04 05:00:21 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078365111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.2078365111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_genbits.2726956379
Short name T47
Test name
Test status
Simulation time 50408128 ps
CPU time 1.63 seconds
Started Sep 04 05:00:17 AM UTC 24
Finished Sep 04 05:00:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726956379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2726956379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_intr.888477966
Short name T48
Test name
Test status
Simulation time 20216514 ps
CPU time 1.7 seconds
Started Sep 04 05:00:18 AM UTC 24
Finished Sep 04 05:00:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888477966 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.888477966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_regwen.3535466932
Short name T239
Test name
Test status
Simulation time 43605348 ps
CPU time 1.38 seconds
Started Sep 04 05:00:17 AM UTC 24
Finished Sep 04 05:00:19 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535466932 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.3535466932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_smoke.1403442549
Short name T349
Test name
Test status
Simulation time 43006746 ps
CPU time 1.24 seconds
Started Sep 04 05:00:16 AM UTC 24
Finished Sep 04 05:00:18 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403442549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.1403442549
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/7.edn_stress_all.4222199995
Short name T108
Test name
Test status
Simulation time 1157569924 ps
CPU time 7.09 seconds
Started Sep 04 05:00:17 AM UTC 24
Finished Sep 04 05:00:25 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222199995 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4222199995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/70.edn_alert.315580354
Short name T179
Test name
Test status
Simulation time 27901709 ps
CPU time 1.73 seconds
Started Sep 04 05:06:26 AM UTC 24
Finished Sep 04 05:06:29 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315580354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 70.edn_alert.315580354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/70.edn_err.3322462698
Short name T624
Test name
Test status
Simulation time 34398008 ps
CPU time 1.41 seconds
Started Sep 04 05:06:28 AM UTC 24
Finished Sep 04 05:06:30 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322462698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.3322462698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/70.edn_genbits.2605085283
Short name T623
Test name
Test status
Simulation time 128900570 ps
CPU time 1.94 seconds
Started Sep 04 05:06:26 AM UTC 24
Finished Sep 04 05:06:29 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605085283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2605085283
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/71.edn_alert.789736209
Short name T258
Test name
Test status
Simulation time 246905595 ps
CPU time 1.58 seconds
Started Sep 04 05:06:29 AM UTC 24
Finished Sep 04 05:06:32 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789736209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 71.edn_alert.789736209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/71.edn_err.1385400077
Short name T150
Test name
Test status
Simulation time 33581226 ps
CPU time 1.6 seconds
Started Sep 04 05:06:29 AM UTC 24
Finished Sep 04 05:06:32 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385400077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.1385400077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/71.edn_genbits.3801769945
Short name T625
Test name
Test status
Simulation time 55101066 ps
CPU time 1.64 seconds
Started Sep 04 05:06:29 AM UTC 24
Finished Sep 04 05:06:32 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801769945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3801769945
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/72.edn_alert.3993067241
Short name T626
Test name
Test status
Simulation time 24880264 ps
CPU time 1.7 seconds
Started Sep 04 05:06:29 AM UTC 24
Finished Sep 04 05:06:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993067241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.3993067241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/72.edn_err.123490432
Short name T198
Test name
Test status
Simulation time 50861026 ps
CPU time 1.24 seconds
Started Sep 04 05:06:29 AM UTC 24
Finished Sep 04 05:06:31 AM UTC 24
Peak memory 228544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123490432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 72.edn_err.123490432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/72.edn_genbits.1043186796
Short name T627
Test name
Test status
Simulation time 45727845 ps
CPU time 2.21 seconds
Started Sep 04 05:06:29 AM UTC 24
Finished Sep 04 05:06:32 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043186796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1043186796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/73.edn_alert.211588795
Short name T628
Test name
Test status
Simulation time 43054868 ps
CPU time 1.75 seconds
Started Sep 04 05:06:31 AM UTC 24
Finished Sep 04 05:06:34 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211588795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 73.edn_alert.211588795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/73.edn_err.2806350579
Short name T630
Test name
Test status
Simulation time 20121103 ps
CPU time 1.48 seconds
Started Sep 04 05:06:33 AM UTC 24
Finished Sep 04 05:06:35 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806350579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.2806350579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/73.edn_genbits.2891238531
Short name T633
Test name
Test status
Simulation time 72441238 ps
CPU time 4.1 seconds
Started Sep 04 05:06:30 AM UTC 24
Finished Sep 04 05:06:36 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891238531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2891238531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/74.edn_alert.2487294054
Short name T631
Test name
Test status
Simulation time 36620356 ps
CPU time 1.48 seconds
Started Sep 04 05:06:33 AM UTC 24
Finished Sep 04 05:06:35 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487294054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.2487294054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/74.edn_err.105578326
Short name T629
Test name
Test status
Simulation time 22711093 ps
CPU time 1.33 seconds
Started Sep 04 05:06:33 AM UTC 24
Finished Sep 04 05:06:35 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105578326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 74.edn_err.105578326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/74.edn_genbits.2417382793
Short name T632
Test name
Test status
Simulation time 54370624 ps
CPU time 1.71 seconds
Started Sep 04 05:06:33 AM UTC 24
Finished Sep 04 05:06:35 AM UTC 24
Peak memory 228256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417382793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2417382793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/75.edn_alert.3727600146
Short name T635
Test name
Test status
Simulation time 24435709 ps
CPU time 1.64 seconds
Started Sep 04 05:06:34 AM UTC 24
Finished Sep 04 05:06:37 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727600146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 75.edn_alert.3727600146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/75.edn_err.69896471
Short name T151
Test name
Test status
Simulation time 21103437 ps
CPU time 1.68 seconds
Started Sep 04 05:06:35 AM UTC 24
Finished Sep 04 05:06:38 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69896471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 75.edn_err.69896471
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/75.edn_genbits.2274322531
Short name T634
Test name
Test status
Simulation time 95762830 ps
CPU time 1.81 seconds
Started Sep 04 05:06:33 AM UTC 24
Finished Sep 04 05:06:36 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274322531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2274322531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/76.edn_alert.655901334
Short name T638
Test name
Test status
Simulation time 22412186 ps
CPU time 1.6 seconds
Started Sep 04 05:06:36 AM UTC 24
Finished Sep 04 05:06:39 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655901334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 76.edn_alert.655901334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/76.edn_err.1316038838
Short name T636
Test name
Test status
Simulation time 34399001 ps
CPU time 1.14 seconds
Started Sep 04 05:06:36 AM UTC 24
Finished Sep 04 05:06:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316038838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.1316038838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/76.edn_genbits.1761997256
Short name T637
Test name
Test status
Simulation time 66356588 ps
CPU time 1.71 seconds
Started Sep 04 05:06:36 AM UTC 24
Finished Sep 04 05:06:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761997256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1761997256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/77.edn_alert.3151717365
Short name T189
Test name
Test status
Simulation time 40825097 ps
CPU time 1.7 seconds
Started Sep 04 05:06:37 AM UTC 24
Finished Sep 04 05:06:40 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151717365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.3151717365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/77.edn_err.3531076079
Short name T640
Test name
Test status
Simulation time 35113880 ps
CPU time 1.48 seconds
Started Sep 04 05:06:37 AM UTC 24
Finished Sep 04 05:06:40 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531076079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.3531076079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/77.edn_genbits.3254947135
Short name T639
Test name
Test status
Simulation time 35681474 ps
CPU time 1.96 seconds
Started Sep 04 05:06:36 AM UTC 24
Finished Sep 04 05:06:39 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254947135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3254947135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/78.edn_alert.1999917455
Short name T185
Test name
Test status
Simulation time 110700964 ps
CPU time 1.49 seconds
Started Sep 04 05:06:38 AM UTC 24
Finished Sep 04 05:06:41 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999917455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 78.edn_alert.1999917455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/78.edn_err.2810863514
Short name T641
Test name
Test status
Simulation time 27499425 ps
CPU time 1.54 seconds
Started Sep 04 05:06:38 AM UTC 24
Finished Sep 04 05:06:41 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810863514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.2810863514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/78.edn_genbits.1838647828
Short name T642
Test name
Test status
Simulation time 54348778 ps
CPU time 2.75 seconds
Started Sep 04 05:06:37 AM UTC 24
Finished Sep 04 05:06:41 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838647828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1838647828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/79.edn_alert.2279400464
Short name T645
Test name
Test status
Simulation time 67964059 ps
CPU time 1.53 seconds
Started Sep 04 05:06:40 AM UTC 24
Finished Sep 04 05:06:42 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279400464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.2279400464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/79.edn_err.468467556
Short name T644
Test name
Test status
Simulation time 80044072 ps
CPU time 1.34 seconds
Started Sep 04 05:06:40 AM UTC 24
Finished Sep 04 05:06:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468467556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 79.edn_err.468467556
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/79.edn_genbits.3806857076
Short name T643
Test name
Test status
Simulation time 40604328 ps
CPU time 1.72 seconds
Started Sep 04 05:06:38 AM UTC 24
Finished Sep 04 05:06:41 AM UTC 24
Peak memory 228620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806857076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3806857076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_alert.2453144722
Short name T114
Test name
Test status
Simulation time 74625023 ps
CPU time 1.23 seconds
Started Sep 04 05:00:24 AM UTC 24
Finished Sep 04 05:00:26 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453144722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.2453144722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_alert_test.1747011227
Short name T353
Test name
Test status
Simulation time 25558648 ps
CPU time 1.39 seconds
Started Sep 04 05:00:25 AM UTC 24
Finished Sep 04 05:00:28 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747011227 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1747011227
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_disable.3412518014
Short name T352
Test name
Test status
Simulation time 20517667 ps
CPU time 1.23 seconds
Started Sep 04 05:00:25 AM UTC 24
Finished Sep 04 05:00:28 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412518014 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3412518014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.2911763244
Short name T88
Test name
Test status
Simulation time 56311662 ps
CPU time 1.86 seconds
Started Sep 04 05:00:25 AM UTC 24
Finished Sep 04 05:00:28 AM UTC 24
Peak memory 230240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911763244 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.2911763244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_err.3734803499
Short name T60
Test name
Test status
Simulation time 34871958 ps
CPU time 1.78 seconds
Started Sep 04 05:00:25 AM UTC 24
Finished Sep 04 05:00:28 AM UTC 24
Peak memory 243796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734803499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.3734803499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_genbits.42884547
Short name T71
Test name
Test status
Simulation time 55349907 ps
CPU time 2.05 seconds
Started Sep 04 05:00:22 AM UTC 24
Finished Sep 04 05:00:25 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42884547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.edn_genbits.42884547
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_regwen.1346666482
Short name T351
Test name
Test status
Simulation time 45020528 ps
CPU time 1.48 seconds
Started Sep 04 05:00:22 AM UTC 24
Finished Sep 04 05:00:24 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346666482 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.1346666482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_smoke.959792299
Short name T105
Test name
Test status
Simulation time 28324802 ps
CPU time 1.46 seconds
Started Sep 04 05:00:22 AM UTC 24
Finished Sep 04 05:00:24 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959792299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.edn_smoke.959792299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/8.edn_stress_all.2390164657
Short name T109
Test name
Test status
Simulation time 527111921 ps
CPU time 5.39 seconds
Started Sep 04 05:00:22 AM UTC 24
Finished Sep 04 05:00:28 AM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390164657 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2390164657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/80.edn_alert.3540357177
Short name T259
Test name
Test status
Simulation time 32188847 ps
CPU time 1.94 seconds
Started Sep 04 05:06:40 AM UTC 24
Finished Sep 04 05:06:43 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540357177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.3540357177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/80.edn_err.341533139
Short name T647
Test name
Test status
Simulation time 25413190 ps
CPU time 1.42 seconds
Started Sep 04 05:06:41 AM UTC 24
Finished Sep 04 05:06:43 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341533139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 80.edn_err.341533139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/80.edn_genbits.2899007552
Short name T646
Test name
Test status
Simulation time 113276318 ps
CPU time 2.04 seconds
Started Sep 04 05:06:40 AM UTC 24
Finished Sep 04 05:06:43 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899007552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2899007552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/81.edn_alert.818107918
Short name T648
Test name
Test status
Simulation time 32781543 ps
CPU time 1.99 seconds
Started Sep 04 05:06:42 AM UTC 24
Finished Sep 04 05:06:45 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818107918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 81.edn_alert.818107918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/81.edn_err.4146438299
Short name T173
Test name
Test status
Simulation time 18899307 ps
CPU time 1.69 seconds
Started Sep 04 05:06:42 AM UTC 24
Finished Sep 04 05:06:45 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146438299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.4146438299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/81.edn_genbits.1149914006
Short name T313
Test name
Test status
Simulation time 65959069 ps
CPU time 1.61 seconds
Started Sep 04 05:06:41 AM UTC 24
Finished Sep 04 05:06:43 AM UTC 24
Peak memory 228348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149914006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1149914006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/82.edn_alert.909854768
Short name T651
Test name
Test status
Simulation time 30865732 ps
CPU time 1.9 seconds
Started Sep 04 05:06:42 AM UTC 24
Finished Sep 04 05:06:45 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909854768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 82.edn_alert.909854768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/82.edn_err.3736282253
Short name T654
Test name
Test status
Simulation time 29318261 ps
CPU time 1.86 seconds
Started Sep 04 05:06:43 AM UTC 24
Finished Sep 04 05:06:46 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736282253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.3736282253
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/82.edn_genbits.1962570507
Short name T649
Test name
Test status
Simulation time 62896863 ps
CPU time 1.94 seconds
Started Sep 04 05:06:42 AM UTC 24
Finished Sep 04 05:06:45 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962570507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1962570507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/83.edn_alert.2690107906
Short name T136
Test name
Test status
Simulation time 65761534 ps
CPU time 1.72 seconds
Started Sep 04 05:06:43 AM UTC 24
Finished Sep 04 05:06:46 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690107906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.2690107906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/83.edn_err.833298804
Short name T653
Test name
Test status
Simulation time 20509377 ps
CPU time 1.57 seconds
Started Sep 04 05:06:43 AM UTC 24
Finished Sep 04 05:06:46 AM UTC 24
Peak memory 237296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833298804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 83.edn_err.833298804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/83.edn_genbits.3754337929
Short name T652
Test name
Test status
Simulation time 74484780 ps
CPU time 1.69 seconds
Started Sep 04 05:06:43 AM UTC 24
Finished Sep 04 05:06:46 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754337929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3754337929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/84.edn_alert.1153875514
Short name T655
Test name
Test status
Simulation time 25016614 ps
CPU time 1.76 seconds
Started Sep 04 05:06:44 AM UTC 24
Finished Sep 04 05:06:47 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153875514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.1153875514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/84.edn_err.2113996319
Short name T657
Test name
Test status
Simulation time 82354353 ps
CPU time 1.15 seconds
Started Sep 04 05:06:46 AM UTC 24
Finished Sep 04 05:06:48 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113996319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.2113996319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/84.edn_genbits.3287365237
Short name T656
Test name
Test status
Simulation time 26046196 ps
CPU time 1.8 seconds
Started Sep 04 05:06:44 AM UTC 24
Finished Sep 04 05:06:47 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287365237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3287365237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/85.edn_alert.3352050600
Short name T659
Test name
Test status
Simulation time 49530810 ps
CPU time 1.71 seconds
Started Sep 04 05:06:46 AM UTC 24
Finished Sep 04 05:06:48 AM UTC 24
Peak memory 228412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352050600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.3352050600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/85.edn_err.3661027832
Short name T174
Test name
Test status
Simulation time 25382275 ps
CPU time 1.55 seconds
Started Sep 04 05:06:46 AM UTC 24
Finished Sep 04 05:06:48 AM UTC 24
Peak memory 236952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661027832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.3661027832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/85.edn_genbits.36458391
Short name T658
Test name
Test status
Simulation time 62802977 ps
CPU time 1.62 seconds
Started Sep 04 05:06:46 AM UTC 24
Finished Sep 04 05:06:48 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36458391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 85.edn_genbits.36458391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/86.edn_alert.3293825265
Short name T662
Test name
Test status
Simulation time 30285102 ps
CPU time 1.88 seconds
Started Sep 04 05:06:47 AM UTC 24
Finished Sep 04 05:06:50 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293825265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.3293825265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/86.edn_err.3978647950
Short name T660
Test name
Test status
Simulation time 20271688 ps
CPU time 1.29 seconds
Started Sep 04 05:06:47 AM UTC 24
Finished Sep 04 05:06:49 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978647950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.3978647950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/86.edn_genbits.3440978521
Short name T668
Test name
Test status
Simulation time 243590841 ps
CPU time 5.03 seconds
Started Sep 04 05:06:47 AM UTC 24
Finished Sep 04 05:06:53 AM UTC 24
Peak memory 231780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440978521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3440978521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/87.edn_alert.1835980884
Short name T663
Test name
Test status
Simulation time 45405966 ps
CPU time 1.69 seconds
Started Sep 04 05:06:48 AM UTC 24
Finished Sep 04 05:06:51 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835980884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.1835980884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/87.edn_err.4249192581
Short name T160
Test name
Test status
Simulation time 44536028 ps
CPU time 1.77 seconds
Started Sep 04 05:06:48 AM UTC 24
Finished Sep 04 05:06:51 AM UTC 24
Peak memory 242180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249192581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 87.edn_err.4249192581
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/87.edn_genbits.2921448367
Short name T661
Test name
Test status
Simulation time 39088168 ps
CPU time 1.74 seconds
Started Sep 04 05:06:47 AM UTC 24
Finished Sep 04 05:06:50 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921448367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2921448367
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/88.edn_alert.2513534701
Short name T665
Test name
Test status
Simulation time 41233890 ps
CPU time 1.61 seconds
Started Sep 04 05:06:49 AM UTC 24
Finished Sep 04 05:06:52 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513534701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.2513534701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/88.edn_err.407900235
Short name T664
Test name
Test status
Simulation time 65025622 ps
CPU time 1.2 seconds
Started Sep 04 05:06:49 AM UTC 24
Finished Sep 04 05:06:51 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407900235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 88.edn_err.407900235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/88.edn_genbits.3098442524
Short name T317
Test name
Test status
Simulation time 39685804 ps
CPU time 1.87 seconds
Started Sep 04 05:06:48 AM UTC 24
Finished Sep 04 05:06:51 AM UTC 24
Peak memory 228500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098442524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3098442524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/89.edn_alert.770480218
Short name T667
Test name
Test status
Simulation time 26078016 ps
CPU time 1.57 seconds
Started Sep 04 05:06:50 AM UTC 24
Finished Sep 04 05:06:53 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770480218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 89.edn_alert.770480218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/89.edn_err.265637723
Short name T666
Test name
Test status
Simulation time 21956911 ps
CPU time 1.32 seconds
Started Sep 04 05:06:50 AM UTC 24
Finished Sep 04 05:06:53 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265637723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 89.edn_err.265637723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/89.edn_genbits.802012718
Short name T673
Test name
Test status
Simulation time 112994039 ps
CPU time 4.27 seconds
Started Sep 04 05:06:49 AM UTC 24
Finished Sep 04 05:06:54 AM UTC 24
Peak memory 231752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802012718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 89.edn_genbits.802012718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_alert.3959679258
Short name T112
Test name
Test status
Simulation time 132472468 ps
CPU time 2 seconds
Started Sep 04 05:00:29 AM UTC 24
Finished Sep 04 05:00:32 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959679258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.3959679258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_alert_test.1747013535
Short name T356
Test name
Test status
Simulation time 22317340 ps
CPU time 1.26 seconds
Started Sep 04 05:00:32 AM UTC 24
Finished Sep 04 05:00:35 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747013535 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1747013535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_disable.973611067
Short name T78
Test name
Test status
Simulation time 20803476 ps
CPU time 1.16 seconds
Started Sep 04 05:00:30 AM UTC 24
Finished Sep 04 05:00:32 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973611067 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.973611067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.878343163
Short name T155
Test name
Test status
Simulation time 28803100 ps
CPU time 1.76 seconds
Started Sep 04 05:00:31 AM UTC 24
Finished Sep 04 05:00:34 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878343163 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.878343163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_err.1844338278
Short name T191
Test name
Test status
Simulation time 22171434 ps
CPU time 1.44 seconds
Started Sep 04 05:00:30 AM UTC 24
Finished Sep 04 05:00:32 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844338278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.1844338278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_genbits.910362108
Short name T13
Test name
Test status
Simulation time 128707834 ps
CPU time 2.05 seconds
Started Sep 04 05:00:28 AM UTC 24
Finished Sep 04 05:00:31 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910362108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_genbits.910362108
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_intr.1838478817
Short name T61
Test name
Test status
Simulation time 21176862 ps
CPU time 1.89 seconds
Started Sep 04 05:00:29 AM UTC 24
Finished Sep 04 05:00:32 AM UTC 24
Peak memory 238744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838478817 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.1838478817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_regwen.137010742
Short name T240
Test name
Test status
Simulation time 19653871 ps
CPU time 1.57 seconds
Started Sep 04 05:00:27 AM UTC 24
Finished Sep 04 05:00:30 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137010742 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_regwen.137010742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_smoke.1300993653
Short name T354
Test name
Test status
Simulation time 16682981 ps
CPU time 1.42 seconds
Started Sep 04 05:00:26 AM UTC 24
Finished Sep 04 05:00:29 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300993653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.1300993653
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_stress_all.802999490
Short name T243
Test name
Test status
Simulation time 429457890 ps
CPU time 5.04 seconds
Started Sep 04 05:00:29 AM UTC 24
Finished Sep 04 05:00:35 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802999490 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.802999490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.3721117079
Short name T225
Test name
Test status
Simulation time 17156002277 ps
CPU time 112.65 seconds
Started Sep 04 05:00:29 AM UTC 24
Finished Sep 04 05:02:24 AM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3721117079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.3721117079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/90.edn_alert.1629287165
Short name T672
Test name
Test status
Simulation time 89441770 ps
CPU time 1.76 seconds
Started Sep 04 05:06:51 AM UTC 24
Finished Sep 04 05:06:54 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629287165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.1629287165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/90.edn_err.4111479043
Short name T670
Test name
Test status
Simulation time 19288828 ps
CPU time 1.52 seconds
Started Sep 04 05:06:52 AM UTC 24
Finished Sep 04 05:06:54 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111479043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 90.edn_err.4111479043
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/90.edn_genbits.3839015514
Short name T669
Test name
Test status
Simulation time 57661791 ps
CPU time 2.06 seconds
Started Sep 04 05:06:50 AM UTC 24
Finished Sep 04 05:06:53 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839015514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3839015514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/91.edn_alert.1724938771
Short name T674
Test name
Test status
Simulation time 26092168 ps
CPU time 1.72 seconds
Started Sep 04 05:06:53 AM UTC 24
Finished Sep 04 05:06:55 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724938771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.1724938771
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/91.edn_err.3371529688
Short name T134
Test name
Test status
Simulation time 47957920 ps
CPU time 1.5 seconds
Started Sep 04 05:06:53 AM UTC 24
Finished Sep 04 05:06:55 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371529688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 91.edn_err.3371529688
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/91.edn_genbits.67738383
Short name T671
Test name
Test status
Simulation time 68119949 ps
CPU time 1.49 seconds
Started Sep 04 05:06:52 AM UTC 24
Finished Sep 04 05:06:54 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67738383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 91.edn_genbits.67738383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/92.edn_alert.1559296224
Short name T676
Test name
Test status
Simulation time 25626693 ps
CPU time 1.69 seconds
Started Sep 04 05:06:54 AM UTC 24
Finished Sep 04 05:06:56 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559296224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 92.edn_alert.1559296224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/92.edn_err.1301442458
Short name T675
Test name
Test status
Simulation time 22747316 ps
CPU time 1.36 seconds
Started Sep 04 05:06:54 AM UTC 24
Finished Sep 04 05:06:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301442458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.1301442458
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/92.edn_genbits.351828990
Short name T677
Test name
Test status
Simulation time 35664637 ps
CPU time 1.7 seconds
Started Sep 04 05:06:54 AM UTC 24
Finished Sep 04 05:06:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351828990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 92.edn_genbits.351828990
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/93.edn_alert.1714833436
Short name T681
Test name
Test status
Simulation time 77563622 ps
CPU time 1.9 seconds
Started Sep 04 05:06:55 AM UTC 24
Finished Sep 04 05:06:58 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714833436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.1714833436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/93.edn_err.4001817443
Short name T679
Test name
Test status
Simulation time 33070416 ps
CPU time 1.34 seconds
Started Sep 04 05:06:55 AM UTC 24
Finished Sep 04 05:06:57 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001817443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.4001817443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/93.edn_genbits.4084131987
Short name T678
Test name
Test status
Simulation time 31511800 ps
CPU time 1.89 seconds
Started Sep 04 05:06:54 AM UTC 24
Finished Sep 04 05:06:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084131987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4084131987
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/94.edn_alert.2120004560
Short name T682
Test name
Test status
Simulation time 48234380 ps
CPU time 1.84 seconds
Started Sep 04 05:06:55 AM UTC 24
Finished Sep 04 05:06:58 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120004560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.2120004560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/94.edn_err.1129813930
Short name T683
Test name
Test status
Simulation time 44473374 ps
CPU time 1.68 seconds
Started Sep 04 05:06:56 AM UTC 24
Finished Sep 04 05:06:59 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129813930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.1129813930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/94.edn_genbits.3754368344
Short name T680
Test name
Test status
Simulation time 79579069 ps
CPU time 1.65 seconds
Started Sep 04 05:06:55 AM UTC 24
Finished Sep 04 05:06:58 AM UTC 24
Peak memory 230188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754368344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3754368344
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/95.edn_err.3829963489
Short name T684
Test name
Test status
Simulation time 68347650 ps
CPU time 1.56 seconds
Started Sep 04 05:06:57 AM UTC 24
Finished Sep 04 05:07:00 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829963489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.3829963489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/95.edn_genbits.2200657286
Short name T320
Test name
Test status
Simulation time 158278322 ps
CPU time 4.84 seconds
Started Sep 04 05:06:56 AM UTC 24
Finished Sep 04 05:07:02 AM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200657286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2200657286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/96.edn_alert.3241893348
Short name T157
Test name
Test status
Simulation time 45115740 ps
CPU time 1.75 seconds
Started Sep 04 05:06:58 AM UTC 24
Finished Sep 04 05:07:00 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241893348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.3241893348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/96.edn_err.1188631860
Short name T686
Test name
Test status
Simulation time 34560248 ps
CPU time 1.31 seconds
Started Sep 04 05:06:59 AM UTC 24
Finished Sep 04 05:07:01 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188631860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 96.edn_err.1188631860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/96.edn_genbits.4234385226
Short name T685
Test name
Test status
Simulation time 70031370 ps
CPU time 1.52 seconds
Started Sep 04 05:06:57 AM UTC 24
Finished Sep 04 05:07:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234385226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4234385226
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/97.edn_alert.1079053596
Short name T687
Test name
Test status
Simulation time 173082509 ps
CPU time 1.59 seconds
Started Sep 04 05:06:59 AM UTC 24
Finished Sep 04 05:07:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079053596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.1079053596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/97.edn_err.422387796
Short name T175
Test name
Test status
Simulation time 18380651 ps
CPU time 1.55 seconds
Started Sep 04 05:06:59 AM UTC 24
Finished Sep 04 05:07:01 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422387796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 97.edn_err.422387796
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/97.edn_genbits.1167798454
Short name T688
Test name
Test status
Simulation time 70807181 ps
CPU time 1.67 seconds
Started Sep 04 05:06:59 AM UTC 24
Finished Sep 04 05:07:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167798454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1167798454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/98.edn_alert.3868484280
Short name T691
Test name
Test status
Simulation time 107367505 ps
CPU time 1.55 seconds
Started Sep 04 05:07:01 AM UTC 24
Finished Sep 04 05:07:04 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868484280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.3868484280
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/98.edn_err.980951732
Short name T690
Test name
Test status
Simulation time 20507521 ps
CPU time 1.5 seconds
Started Sep 04 05:07:01 AM UTC 24
Finished Sep 04 05:07:03 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980951732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 98.edn_err.980951732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/98.edn_genbits.291444792
Short name T689
Test name
Test status
Simulation time 55766666 ps
CPU time 1.98 seconds
Started Sep 04 05:07:00 AM UTC 24
Finished Sep 04 05:07:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291444792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 98.edn_genbits.291444792
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/99.edn_alert.3550739219
Short name T692
Test name
Test status
Simulation time 39562527 ps
CPU time 1.92 seconds
Started Sep 04 05:07:01 AM UTC 24
Finished Sep 04 05:07:04 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550739219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 99.edn_alert.3550739219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/99.edn_err.2066415321
Short name T187
Test name
Test status
Simulation time 18406817 ps
CPU time 1.69 seconds
Started Sep 04 05:07:02 AM UTC 24
Finished Sep 04 05:07:05 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066415321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.2066415321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/default/99.edn_genbits.3986029666
Short name T693
Test name
Test status
Simulation time 73577189 ps
CPU time 2.62 seconds
Started Sep 04 05:07:01 AM UTC 24
Finished Sep 04 05:07:05 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986029666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3986029666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/99.edn_genbits/latest
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