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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.83 98.25 93.79 97.02 92.44 96.37 99.77 93.18


Total test records in report: 1113
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T1006 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.2551290127 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:03 AM UTC 24 40195744 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3626358743 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:03 AM UTC 24 14023115 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.365240399 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:03 AM UTC 24 33836946 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1473204273 Sep 09 10:50:00 AM UTC 24 Sep 09 10:50:04 AM UTC 24 53850900 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1489318822 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:04 AM UTC 24 23742214 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2567672868 Sep 09 10:49:58 AM UTC 24 Sep 09 10:50:04 AM UTC 24 121789603 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2066995783 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:04 AM UTC 24 15853528 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2011513003 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:04 AM UTC 24 162953388 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.912638388 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:07 AM UTC 24 14796420 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.4174613689 Sep 09 10:50:00 AM UTC 24 Sep 09 10:50:05 AM UTC 24 69954270 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.4103022859 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:05 AM UTC 24 400958461 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3889726974 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:05 AM UTC 24 39665341 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.3983513782 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:05 AM UTC 24 16038405 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3708666775 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:05 AM UTC 24 12503729 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.831309958 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:05 AM UTC 24 114838183 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.1120774267 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:05 AM UTC 24 12128178 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.198519169 Sep 09 10:50:01 AM UTC 24 Sep 09 10:50:05 AM UTC 24 235962023 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.4205778615 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:06 AM UTC 24 51655734 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.81814899 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:06 AM UTC 24 168378162 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.795088761 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:06 AM UTC 24 57871437 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2602449789 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:06 AM UTC 24 130308820 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.133692786 Sep 09 10:50:05 AM UTC 24 Sep 09 10:50:07 AM UTC 24 33155904 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.2388058724 Sep 09 10:50:05 AM UTC 24 Sep 09 10:50:07 AM UTC 24 189866338 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1662954298 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:07 AM UTC 24 60896195 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3326151134 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:07 AM UTC 24 33836569 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2034052903 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:07 AM UTC 24 19788955 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3159109744 Sep 09 10:50:05 AM UTC 24 Sep 09 10:50:07 AM UTC 24 30158040 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.574871799 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:08 AM UTC 24 24170529 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.4135813132 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:08 AM UTC 24 108428041 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2016867679 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:08 AM UTC 24 194185681 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.459044941 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:08 AM UTC 24 94054235 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.4129396725 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:08 AM UTC 24 14755048 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3474367431 Sep 09 10:50:05 AM UTC 24 Sep 09 10:50:08 AM UTC 24 151712594 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.1105370788 Sep 09 10:50:03 AM UTC 24 Sep 09 10:50:08 AM UTC 24 979385034 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1658563586 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:08 AM UTC 24 51597097 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2273572817 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:08 AM UTC 24 121722093 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1909000860 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:09 AM UTC 24 46832607 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.676331581 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:09 AM UTC 24 575307508 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4222976424 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:09 AM UTC 24 92532814 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.44369511 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:09 AM UTC 24 65225008 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.985377223 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:09 AM UTC 24 39063922 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2338815182 Sep 09 10:50:04 AM UTC 24 Sep 09 10:50:09 AM UTC 24 180755071 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2471095588 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:09 AM UTC 24 14748296 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.1346221724 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:09 AM UTC 24 114754720 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3938294211 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:09 AM UTC 24 16929966 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3354529776 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:09 AM UTC 24 20925773 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1109053261 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:10 AM UTC 24 75691187 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1956560263 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:10 AM UTC 24 54572719 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.2026785266 Sep 09 10:50:06 AM UTC 24 Sep 09 10:50:10 AM UTC 24 424100939 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3295470477 Sep 09 10:50:08 AM UTC 24 Sep 09 10:50:11 AM UTC 24 60587947 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3739095484 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:11 AM UTC 24 36599294 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1672595785 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:11 AM UTC 24 53124422 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2604390194 Sep 09 10:50:08 AM UTC 24 Sep 09 10:50:11 AM UTC 24 28014226 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.332995012 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:11 AM UTC 24 24417945 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.452084982 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:11 AM UTC 24 30491483 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3212121100 Sep 09 10:50:07 AM UTC 24 Sep 09 10:50:11 AM UTC 24 96678939 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2819869249 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:11 AM UTC 24 18942131 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.586072120 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:11 AM UTC 24 65319120 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.244216589 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:12 AM UTC 24 144935673 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2016213702 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:12 AM UTC 24 214304661 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1142651715 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:12 AM UTC 24 22242387 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.608064667 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:12 AM UTC 24 45795493 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.708057797 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:12 AM UTC 24 26509232 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3477728671 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:13 AM UTC 24 53392230 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2502379377 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:13 AM UTC 24 88556399 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.2445819730 Sep 09 10:50:09 AM UTC 24 Sep 09 10:50:13 AM UTC 24 83342331 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3693822812 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:13 AM UTC 24 34052315 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1122210970 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:13 AM UTC 24 46586250 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1654853144 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:13 AM UTC 24 23414873 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.202536985 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:13 AM UTC 24 158696585 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.133550953 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 35279412 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.131227168 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 73522244 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2763117762 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 19356288 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3884013263 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 40340570 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.2293058556 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 27387170 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1398495211 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:14 AM UTC 24 158275411 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.1337571584 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 14905213 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.795313300 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 41848449 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.1279544118 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 12494323 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3661343753 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 47438139 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4189319775 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 28808653 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2118182168 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:14 AM UTC 24 118533764 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.1032690921 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:15 AM UTC 24 303633751 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3133006231 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:15 AM UTC 24 54894260 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.843103956 Sep 09 10:50:10 AM UTC 24 Sep 09 10:50:15 AM UTC 24 98373451 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1728964422 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 29774822 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2148597123 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 56390306 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2525220460 Sep 09 10:50:12 AM UTC 24 Sep 09 10:50:15 AM UTC 24 26594355 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.153344996 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 41974526 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.2138696053 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 17133255 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1577730294 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 27029201 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3661660152 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 12616672 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3443556496 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:15 AM UTC 24 15418644 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.983688167 Sep 09 10:50:13 AM UTC 24 Sep 09 10:50:16 AM UTC 24 13289304 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3758407358 Sep 09 10:50:16 AM UTC 24 Sep 09 10:50:19 AM UTC 24 71640240 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.588243459 Sep 09 10:50:16 AM UTC 24 Sep 09 10:50:19 AM UTC 24 33087854 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.461846699 Sep 09 10:50:16 AM UTC 24 Sep 09 10:50:19 AM UTC 24 12514474 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3637861650 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 13136684 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.1286747426 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 15664001 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.4099289002 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 34717496 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.718963835 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 34667893 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.142816290 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 40915358 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3958055955 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 16294867 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3909214771 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 14673073 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1529368044 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 41363595 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.844127590 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 38507154 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.2270036323 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 11923656 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.570325968 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 45134295 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2646937068 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 23756419 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2461442345 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 44312074 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.1485924519 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:20 AM UTC 24 23705069 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.71455806 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:30 AM UTC 24 25856474 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.10627516 Sep 09 10:50:15 AM UTC 24 Sep 09 10:50:30 AM UTC 24 25968625 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_genbits.2720577289
Short name T11
Test name
Test status
Simulation time 271263885 ps
CPU time 4.4 seconds
Started Sep 09 11:40:42 AM UTC 24
Finished Sep 09 11:40:47 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720577289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2720577289
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_sec_cm.3973811201
Short name T18
Test name
Test status
Simulation time 1799213667 ps
CPU time 10.47 seconds
Started Sep 09 11:40:49 AM UTC 24
Finished Sep 09 11:41:01 AM UTC 24
Peak memory 262484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973811201 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3973811201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_alert.3517927449
Short name T10
Test name
Test status
Simulation time 79499540 ps
CPU time 1.82 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:40:47 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517927449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.3517927449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_genbits.264359534
Short name T54
Test name
Test status
Simulation time 82973391 ps
CPU time 2.27 seconds
Started Sep 09 11:41:15 AM UTC 24
Finished Sep 09 11:41:19 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264359534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_genbits.264359534
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_stress_all.3247579337
Short name T39
Test name
Test status
Simulation time 383667996 ps
CPU time 3.45 seconds
Started Sep 09 11:40:48 AM UTC 24
Finished Sep 09 11:40:52 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247579337 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3247579337
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_disable.395911166
Short name T51
Test name
Test status
Simulation time 13625753 ps
CPU time 1.14 seconds
Started Sep 09 11:40:57 AM UTC 24
Finished Sep 09 11:40:59 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395911166 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.395911166
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.3860468498
Short name T36
Test name
Test status
Simulation time 6727130812 ps
CPU time 41.53 seconds
Started Sep 09 11:41:05 AM UTC 24
Finished Sep 09 11:41:48 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3860468498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.3860468498
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.1879717158
Short name T19
Test name
Test status
Simulation time 105644371 ps
CPU time 1.48 seconds
Started Sep 09 11:40:49 AM UTC 24
Finished Sep 09 11:40:52 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879717158 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1879717158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_err.76862570
Short name T5
Test name
Test status
Simulation time 28339104 ps
CPU time 1.42 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:40:47 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76862570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.edn_err.76862570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_alert.2252098796
Short name T86
Test name
Test status
Simulation time 27623963 ps
CPU time 1.96 seconds
Started Sep 09 11:41:05 AM UTC 24
Finished Sep 09 11:41:08 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252098796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.2252098796
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_stress_all.1087250543
Short name T114
Test name
Test status
Simulation time 1696230463 ps
CPU time 4.36 seconds
Started Sep 09 11:40:55 AM UTC 24
Finished Sep 09 11:41:01 AM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087250543 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1087250543
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_alert.1958165957
Short name T142
Test name
Test status
Simulation time 79166589 ps
CPU time 1.61 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:04 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958165957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.1958165957
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_alert.318083029
Short name T218
Test name
Test status
Simulation time 44058628 ps
CPU time 1.61 seconds
Started Sep 09 11:42:18 AM UTC 24
Finished Sep 09 11:42:21 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318083029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.edn_alert.318083029
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.2480949821
Short name T59
Test name
Test status
Simulation time 60188237 ps
CPU time 1.6 seconds
Started Sep 09 11:41:06 AM UTC 24
Finished Sep 09 11:41:09 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480949821 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.2480949821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_disable.1864878456
Short name T21
Test name
Test status
Simulation time 25971953 ps
CPU time 1.29 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:40:47 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864878456 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1864878456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_alert.2524170845
Short name T211
Test name
Test status
Simulation time 64589189 ps
CPU time 1.93 seconds
Started Sep 09 11:41:44 AM UTC 24
Finished Sep 09 11:41:47 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524170845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.2524170845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1231672234
Short name T279
Test name
Test status
Simulation time 70871084 ps
CPU time 1.18 seconds
Started Sep 09 10:49:52 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231672234 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1231672234
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.308729322
Short name T77
Test name
Test status
Simulation time 39172520 ps
CPU time 1.97 seconds
Started Sep 09 11:41:14 AM UTC 24
Finished Sep 09 11:41:17 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308729322 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.308729322
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_disable.1029226813
Short name T25
Test name
Test status
Simulation time 49962356 ps
CPU time 1.29 seconds
Started Sep 09 11:40:53 AM UTC 24
Finished Sep 09 11:40:56 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029226813 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1029226813
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_regwen.1204990453
Short name T89
Test name
Test status
Simulation time 20132773 ps
CPU time 1.57 seconds
Started Sep 09 11:40:54 AM UTC 24
Finished Sep 09 11:40:57 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204990453 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.1204990453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_genbits.709339401
Short name T109
Test name
Test status
Simulation time 133285306 ps
CPU time 1.97 seconds
Started Sep 09 11:42:42 AM UTC 24
Finished Sep 09 11:42:45 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709339401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_genbits.709339401
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.1171990644
Short name T306
Test name
Test status
Simulation time 76637736 ps
CPU time 2.79 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 227668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171990644 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1171990644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_disable.1810136525
Short name T534
Test name
Test status
Simulation time 50386796 ps
CPU time 1.13 seconds
Started Sep 09 11:43:18 AM UTC 24
Finished Sep 09 11:43:20 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810136525 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1810136525
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_alert.769430881
Short name T139
Test name
Test status
Simulation time 91364641 ps
CPU time 1.91 seconds
Started Sep 09 11:41:42 AM UTC 24
Finished Sep 09 11:41:45 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769430881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.edn_alert.769430881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_alert.2778148227
Short name T78
Test name
Test status
Simulation time 84551546 ps
CPU time 1.67 seconds
Started Sep 09 11:41:17 AM UTC 24
Finished Sep 09 11:41:19 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778148227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.2778148227
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_stress_all.2122232239
Short name T129
Test name
Test status
Simulation time 845055160 ps
CPU time 6.52 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:09 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122232239 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2122232239
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_intr.2753141695
Short name T32
Test name
Test status
Simulation time 45661553 ps
CPU time 1.37 seconds
Started Sep 09 11:41:17 AM UTC 24
Finished Sep 09 11:41:19 AM UTC 24
Peak memory 228480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753141695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.2753141695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_err.1957984155
Short name T221
Test name
Test status
Simulation time 23349218 ps
CPU time 1.47 seconds
Started Sep 09 11:41:51 AM UTC 24
Finished Sep 09 11:41:53 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957984155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.1957984155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1550103690
Short name T311
Test name
Test status
Simulation time 195088474 ps
CPU time 1.68 seconds
Started Sep 09 11:42:25 AM UTC 24
Finished Sep 09 11:42:28 AM UTC 24
Peak memory 226616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550103690 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1550103690
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/77.edn_alert.667500022
Short name T158
Test name
Test status
Simulation time 47261855 ps
CPU time 1.65 seconds
Started Sep 09 11:43:58 AM UTC 24
Finished Sep 09 11:44:01 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667500022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 77.edn_alert.667500022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.3820681630
Short name T190
Test name
Test status
Simulation time 39046315 ps
CPU time 1.61 seconds
Started Sep 09 11:41:59 AM UTC 24
Finished Sep 09 11:42:02 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820681630 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.3820681630
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_alert.466109431
Short name T57
Test name
Test status
Simulation time 28174199 ps
CPU time 1.74 seconds
Started Sep 09 11:41:39 AM UTC 24
Finished Sep 09 11:41:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466109431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.edn_alert.466109431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/95.edn_err.3485318115
Short name T31
Test name
Test status
Simulation time 97529471 ps
CPU time 1.44 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 237524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485318115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.3485318115
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_alert_test.3136687252
Short name T22
Test name
Test status
Simulation time 203873386 ps
CPU time 1.33 seconds
Started Sep 09 11:40:45 AM UTC 24
Finished Sep 09 11:40:48 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136687252 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3136687252
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/101.edn_alert.4270612717
Short name T701
Test name
Test status
Simulation time 45915925 ps
CPU time 1.41 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:15 AM UTC 24
Peak memory 228380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270612717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 101.edn_alert.4270612717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_disable.3245024097
Short name T195
Test name
Test status
Simulation time 33481984 ps
CPU time 1.29 seconds
Started Sep 09 11:41:28 AM UTC 24
Finished Sep 09 11:41:31 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245024097 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3245024097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_alert.182345500
Short name T26
Test name
Test status
Simulation time 29047690 ps
CPU time 1.91 seconds
Started Sep 09 11:40:52 AM UTC 24
Finished Sep 09 11:40:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182345500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.edn_alert.182345500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_disable.3589735314
Short name T232
Test name
Test status
Simulation time 20529961 ps
CPU time 1.24 seconds
Started Sep 09 11:43:22 AM UTC 24
Finished Sep 09 11:43:24 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589735314 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3589735314
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.4276447775
Short name T244
Test name
Test status
Simulation time 12566789003 ps
CPU time 67.14 seconds
Started Sep 09 11:40:55 AM UTC 24
Finished Sep 09 11:42:05 AM UTC 24
Peak memory 233952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4276447775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.4276447775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/106.edn_alert.3918175448
Short name T710
Test name
Test status
Simulation time 47185119 ps
CPU time 1.44 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918175448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.3918175448
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/108.edn_alert.714851812
Short name T171
Test name
Test status
Simulation time 72745493 ps
CPU time 1.22 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 230444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714851812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 108.edn_alert.714851812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/130.edn_alert.3129325626
Short name T747
Test name
Test status
Simulation time 25901374 ps
CPU time 1.49 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129325626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.3129325626
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/156.edn_alert.3056973592
Short name T800
Test name
Test status
Simulation time 87483146 ps
CPU time 1.36 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056973592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.3056973592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.1573272764
Short name T161
Test name
Test status
Simulation time 45395836 ps
CPU time 2.05 seconds
Started Sep 09 11:41:46 AM UTC 24
Finished Sep 09 11:41:49 AM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573272764 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.1573272764
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_disable.4023585532
Short name T96
Test name
Test status
Simulation time 15201055 ps
CPU time 1.05 seconds
Started Sep 09 11:41:51 AM UTC 24
Finished Sep 09 11:41:53 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023585532 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.4023585532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/182.edn_alert.1255050120
Short name T842
Test name
Test status
Simulation time 350770209 ps
CPU time 1.29 seconds
Started Sep 09 11:44:41 AM UTC 24
Finished Sep 09 11:44:50 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255050120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.1255050120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.740980056
Short name T185
Test name
Test status
Simulation time 120202831 ps
CPU time 1.58 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740980056 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.740980056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_disable.3420883806
Short name T223
Test name
Test status
Simulation time 10658618 ps
CPU time 1.3 seconds
Started Sep 09 11:43:05 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420883806 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3420883806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_err.1314096119
Short name T216
Test name
Test status
Simulation time 34005448 ps
CPU time 1.5 seconds
Started Sep 09 11:43:13 AM UTC 24
Finished Sep 09 11:43:15 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314096119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.1314096119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_disable.813728548
Short name T224
Test name
Test status
Simulation time 13260552 ps
CPU time 1.07 seconds
Started Sep 09 11:43:15 AM UTC 24
Finished Sep 09 11:43:17 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813728548 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.813728548
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_genbits.1860170226
Short name T312
Test name
Test status
Simulation time 52967909 ps
CPU time 2.31 seconds
Started Sep 09 11:41:50 AM UTC 24
Finished Sep 09 11:41:53 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860170226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1860170226
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/66.edn_genbits.817085123
Short name T347
Test name
Test status
Simulation time 59349774 ps
CPU time 2.8 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:54 AM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817085123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 66.edn_genbits.817085123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_genbits.3429365335
Short name T44
Test name
Test status
Simulation time 92731638 ps
CPU time 1.88 seconds
Started Sep 09 11:41:12 AM UTC 24
Finished Sep 09 11:41:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429365335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3429365335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_genbits.1777081463
Short name T118
Test name
Test status
Simulation time 62201314 ps
CPU time 1.74 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:41:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777081463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1777081463
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/168.edn_genbits.1185262037
Short name T354
Test name
Test status
Simulation time 41922912 ps
CPU time 1.42 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185262037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1185262037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_genbits.1855909744
Short name T76
Test name
Test status
Simulation time 52019521 ps
CPU time 1.97 seconds
Started Sep 09 11:41:44 AM UTC 24
Finished Sep 09 11:41:47 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855909744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1855909744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_intr.4020756908
Short name T33
Test name
Test status
Simulation time 104059239 ps
CPU time 1.23 seconds
Started Sep 09 11:41:40 AM UTC 24
Finished Sep 09 11:41:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020756908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.4020756908
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3474367431
Short name T314
Test name
Test status
Simulation time 151712594 ps
CPU time 2.45 seconds
Started Sep 09 10:50:05 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474367431 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3474367431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_regwen.3174329941
Short name T2
Test name
Test status
Simulation time 119538203 ps
CPU time 1.39 seconds
Started Sep 09 11:40:41 AM UTC 24
Finished Sep 09 11:40:43 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174329941 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.3174329941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/123.edn_genbits.520274474
Short name T351
Test name
Test status
Simulation time 98737854 ps
CPU time 1.57 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520274474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 123.edn_genbits.520274474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/126.edn_genbits.3640905293
Short name T328
Test name
Test status
Simulation time 28378833 ps
CPU time 1.26 seconds
Started Sep 09 11:44:20 AM UTC 24
Finished Sep 09 11:44:23 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640905293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3640905293
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/128.edn_genbits.3382808087
Short name T335
Test name
Test status
Simulation time 36506870 ps
CPU time 1.58 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382808087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3382808087
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.434131274
Short name T563
Test name
Test status
Simulation time 5150111356 ps
CPU time 110.97 seconds
Started Sep 09 11:41:37 AM UTC 24
Finished Sep 09 11:43:31 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=434131274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_
with_rand_reset.434131274
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/140.edn_genbits.2188359189
Short name T341
Test name
Test status
Simulation time 36990826 ps
CPU time 1.77 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188359189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2188359189
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/144.edn_genbits.3360108037
Short name T773
Test name
Test status
Simulation time 45569574 ps
CPU time 1.12 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:29 AM UTC 24
Peak memory 230680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360108037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3360108037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/192.edn_genbits.3886904010
Short name T345
Test name
Test status
Simulation time 46819512 ps
CPU time 1.62 seconds
Started Sep 09 11:44:50 AM UTC 24
Finished Sep 09 11:44:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886904010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3886904010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_intr.3250905450
Short name T29
Test name
Test status
Simulation time 38099087 ps
CPU time 1.31 seconds
Started Sep 09 11:41:34 AM UTC 24
Finished Sep 09 11:41:36 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250905450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.3250905450
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_intr.775961194
Short name T147
Test name
Test status
Simulation time 24470242 ps
CPU time 1.37 seconds
Started Sep 09 11:42:18 AM UTC 24
Finished Sep 09 11:42:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775961194 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.775961194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/110.edn_alert.2700479009
Short name T150
Test name
Test status
Simulation time 26760938 ps
CPU time 1.54 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700479009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.2700479009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_err.2464122505
Short name T6
Test name
Test status
Simulation time 59573792 ps
CPU time 2.04 seconds
Started Sep 09 11:40:48 AM UTC 24
Finished Sep 09 11:40:51 AM UTC 24
Peak memory 243816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464122505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.2464122505
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/112.edn_genbits.1061992557
Short name T718
Test name
Test status
Simulation time 45614232 ps
CPU time 1.51 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061992557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1061992557
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.1848506860
Short name T280
Test name
Test status
Simulation time 40847871 ps
CPU time 1.45 seconds
Started Sep 09 10:49:52 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848506860 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1848506860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.260169361
Short name T985
Test name
Test status
Simulation time 238750640 ps
CPU time 4.08 seconds
Started Sep 09 10:49:52 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 217516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260169361 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.260169361
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.2545506064
Short name T259
Test name
Test status
Simulation time 115469103 ps
CPU time 1.28 seconds
Started Sep 09 10:49:52 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545506064 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2545506064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1126539170
Short name T982
Test name
Test status
Simulation time 33861266 ps
CPU time 1.64 seconds
Started Sep 09 10:49:53 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1126539170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1126539170
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.1640893452
Short name T979
Test name
Test status
Simulation time 15622271 ps
CPU time 1.47 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:54 AM UTC 24
Peak memory 216968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640893452 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1640893452
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.491092853
Short name T290
Test name
Test status
Simulation time 33338834 ps
CPU time 1.12 seconds
Started Sep 09 10:49:52 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491092853 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.491092853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.1246184417
Short name T980
Test name
Test status
Simulation time 77378766 ps
CPU time 2.61 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246184417 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1246184417
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.2913046837
Short name T260
Test name
Test status
Simulation time 157390722 ps
CPU time 1.89 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:57 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913046837 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2913046837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.461095033
Short name T288
Test name
Test status
Simulation time 138109377 ps
CPU time 3.5 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461095033 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.461095033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.1916529574
Short name T984
Test name
Test status
Simulation time 58224246 ps
CPU time 1.2 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:56 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916529574 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1916529574
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3143351156
Short name T268
Test name
Test status
Simulation time 50169109 ps
CPU time 1.38 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:57 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3143351156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3143351156
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.522183028
Short name T291
Test name
Test status
Simulation time 14429508 ps
CPU time 1.07 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:56 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522183028 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.522183028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.202944546
Short name T981
Test name
Test status
Simulation time 47248545 ps
CPU time 1.1 seconds
Started Sep 09 10:49:53 AM UTC 24
Finished Sep 09 10:49:55 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202944546 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.202944546
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.3995914132
Short name T292
Test name
Test status
Simulation time 33244355 ps
CPU time 1.43 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:57 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995914132 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.3995914132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.710384648
Short name T983
Test name
Test status
Simulation time 32190579 ps
CPU time 1.93 seconds
Started Sep 09 10:49:53 AM UTC 24
Finished Sep 09 10:49:56 AM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710384648 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.710384648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.824255731
Short name T307
Test name
Test status
Simulation time 153226853 ps
CPU time 2.58 seconds
Started Sep 09 10:49:53 AM UTC 24
Finished Sep 09 10:49:57 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824255731 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.824255731
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1662954298
Short name T1029
Test name
Test status
Simulation time 60896195 ps
CPU time 1.31 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1662954298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1662954298
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.912638388
Short name T1014
Test name
Test status
Simulation time 14796420 ps
CPU time 1.32 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 214576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912638388 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.912638388
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2602449789
Short name T1026
Test name
Test status
Simulation time 130308820 ps
CPU time 1.14 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:06 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602449789 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2602449789
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3326151134
Short name T1030
Test name
Test status
Simulation time 33836569 ps
CPU time 1.51 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326151134 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.3326151134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4222976424
Short name T1043
Test name
Test status
Simulation time 92532814 ps
CPU time 3.52 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222976424 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4222976424
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.459044941
Short name T1036
Test name
Test status
Simulation time 94054235 ps
CPU time 2.57 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 217384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459044941 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.459044941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2273572817
Short name T1040
Test name
Test status
Simulation time 121722093 ps
CPU time 1.81 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2273572817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2273572817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.2388058724
Short name T1028
Test name
Test status
Simulation time 189866338 ps
CPU time 1 seconds
Started Sep 09 10:50:05 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388058724 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2388058724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.133692786
Short name T1027
Test name
Test status
Simulation time 33155904 ps
CPU time 1.03 seconds
Started Sep 09 10:50:05 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133692786 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.133692786
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3159109744
Short name T1032
Test name
Test status
Simulation time 30158040 ps
CPU time 1.25 seconds
Started Sep 09 10:50:05 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159109744 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.3159109744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2338815182
Short name T1046
Test name
Test status
Simulation time 180755071 ps
CPU time 3.57 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338815182 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2338815182
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1909000860
Short name T1041
Test name
Test status
Simulation time 46832607 ps
CPU time 1.62 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1909000860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1909000860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.574871799
Short name T1033
Test name
Test status
Simulation time 24170529 ps
CPU time 0.88 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 215336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574871799 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.574871799
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.4129396725
Short name T1037
Test name
Test status
Simulation time 14755048 ps
CPU time 1.28 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129396725 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4129396725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1658563586
Short name T1039
Test name
Test status
Simulation time 51597097 ps
CPU time 1.17 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658563586 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.1658563586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.2026785266
Short name T1053
Test name
Test status
Simulation time 424100939 ps
CPU time 3.72 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:10 AM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026785266 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2026785266
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.676331581
Short name T1042
Test name
Test status
Simulation time 575307508 ps
CPU time 1.92 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676331581 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.676331581
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1956560263
Short name T1052
Test name
Test status
Simulation time 54572719 ps
CPU time 2.18 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:10 AM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1956560263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1956560263
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.1346221724
Short name T1048
Test name
Test status
Simulation time 114754720 ps
CPU time 1.1 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346221724 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1346221724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.985377223
Short name T1045
Test name
Test status
Simulation time 39063922 ps
CPU time 0.94 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985377223 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.985377223
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2471095588
Short name T1047
Test name
Test status
Simulation time 14748296 ps
CPU time 1.06 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471095588 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.2471095588
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1109053261
Short name T1051
Test name
Test status
Simulation time 75691187 ps
CPU time 2.94 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:10 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109053261 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1109053261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.44369511
Short name T1044
Test name
Test status
Simulation time 65225008 ps
CPU time 1.95 seconds
Started Sep 09 10:50:06 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44369511 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.44369511
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2604390194
Short name T1056
Test name
Test status
Simulation time 28014226 ps
CPU time 1.47 seconds
Started Sep 09 10:50:08 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2604390194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2604390194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3354529776
Short name T1050
Test name
Test status
Simulation time 20925773 ps
CPU time 1.02 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354529776 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3354529776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3938294211
Short name T1049
Test name
Test status
Simulation time 16929966 ps
CPU time 0.99 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:09 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938294211 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3938294211
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3295470477
Short name T1054
Test name
Test status
Simulation time 60587947 ps
CPU time 1.35 seconds
Started Sep 09 10:50:08 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295470477 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.3295470477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1672595785
Short name T1055
Test name
Test status
Simulation time 53124422 ps
CPU time 2.75 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672595785 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1672595785
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3212121100
Short name T1059
Test name
Test status
Simulation time 96678939 ps
CPU time 2.84 seconds
Started Sep 09 10:50:07 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 217024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212121100 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3212121100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2819869249
Short name T1060
Test name
Test status
Simulation time 18942131 ps
CPU time 1.35 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2819869249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2819869249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3739095484
Short name T286
Test name
Test status
Simulation time 36599294 ps
CPU time 1.1 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739095484 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3739095484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.332995012
Short name T1057
Test name
Test status
Simulation time 24417945 ps
CPU time 1.32 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332995012 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.332995012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.586072120
Short name T1061
Test name
Test status
Simulation time 65319120 ps
CPU time 1.36 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586072120 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.586072120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2502379377
Short name T1067
Test name
Test status
Simulation time 88556399 ps
CPU time 3.2 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502379377 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2502379377
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.244216589
Short name T315
Test name
Test status
Simulation time 144935673 ps
CPU time 1.93 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244216589 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.244216589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1654853144
Short name T1071
Test name
Test status
Simulation time 23414873 ps
CPU time 2.04 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 227808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1654853144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1654853144
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1142651715
Short name T1063
Test name
Test status
Simulation time 22242387 ps
CPU time 1.05 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:12 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142651715 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1142651715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.452084982
Short name T1058
Test name
Test status
Simulation time 30491483 ps
CPU time 1.16 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452084982 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.452084982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3693822812
Short name T1069
Test name
Test status
Simulation time 34052315 ps
CPU time 1.82 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693822812 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.3693822812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.2445819730
Short name T1068
Test name
Test status
Simulation time 83342331 ps
CPU time 3.07 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445819730 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2445819730
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2016213702
Short name T1062
Test name
Test status
Simulation time 214304661 ps
CPU time 1.8 seconds
Started Sep 09 10:50:09 AM UTC 24
Finished Sep 09 10:50:12 AM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016213702 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2016213702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.202536985
Short name T1072
Test name
Test status
Simulation time 158696585 ps
CPU time 1.74 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=202536985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.202536985
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.708057797
Short name T1065
Test name
Test status
Simulation time 26509232 ps
CPU time 1.22 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:12 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708057797 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.708057797
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.608064667
Short name T1064
Test name
Test status
Simulation time 45795493 ps
CPU time 1.13 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608064667 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.608064667
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1122210970
Short name T1070
Test name
Test status
Simulation time 46586250 ps
CPU time 1.62 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 215204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122210970 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.1122210970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.1032690921
Short name T1084
Test name
Test status
Simulation time 303633751 ps
CPU time 3.55 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032690921 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1032690921
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3477728671
Short name T1066
Test name
Test status
Simulation time 53392230 ps
CPU time 1.58 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:13 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477728671 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3477728671
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4189319775
Short name T1082
Test name
Test status
Simulation time 28808653 ps
CPU time 1.55 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4189319775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4189319775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2763117762
Short name T1075
Test name
Test status
Simulation time 19356288 ps
CPU time 1.17 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763117762 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2763117762
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.133550953
Short name T1073
Test name
Test status
Simulation time 35279412 ps
CPU time 0.93 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133550953 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.133550953
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.131227168
Short name T1074
Test name
Test status
Simulation time 73522244 ps
CPU time 1.09 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131227168 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.131227168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.843103956
Short name T1085
Test name
Test status
Simulation time 98373451 ps
CPU time 3.52 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843103956 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.843103956
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1398495211
Short name T1077
Test name
Test status
Simulation time 158275411 ps
CPU time 2.37 seconds
Started Sep 09 10:50:10 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398495211 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1398495211
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3661343753
Short name T1081
Test name
Test status
Simulation time 47438139 ps
CPU time 1.29 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3661343753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3661343753
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.2293058556
Short name T287
Test name
Test status
Simulation time 27387170 ps
CPU time 1.07 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293058556 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2293058556
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3884013263
Short name T1076
Test name
Test status
Simulation time 40340570 ps
CPU time 1.06 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884013263 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3884013263
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2118182168
Short name T1083
Test name
Test status
Simulation time 118533764 ps
CPU time 1.49 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118182168 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.2118182168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2525220460
Short name T1088
Test name
Test status
Simulation time 26594355 ps
CPU time 2.38 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525220460 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2525220460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3133006231
Short name T316
Test name
Test status
Simulation time 54894260 ps
CPU time 2.01 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133006231 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3133006231
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.2758739423
Short name T987
Test name
Test status
Simulation time 31151857 ps
CPU time 1.15 seconds
Started Sep 09 10:49:55 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 215356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758739423 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2758739423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.388538677
Short name T990
Test name
Test status
Simulation time 62386940 ps
CPU time 2.47 seconds
Started Sep 09 10:49:55 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 217444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388538677 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.388538677
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2363636656
Short name T281
Test name
Test status
Simulation time 70618549 ps
CPU time 1.35 seconds
Started Sep 09 10:49:55 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363636656 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2363636656
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2323707779
Short name T261
Test name
Test status
Simulation time 37031866 ps
CPU time 1.24 seconds
Started Sep 09 10:49:56 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2323707779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2323707779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.867875615
Short name T282
Test name
Test status
Simulation time 24391428 ps
CPU time 1.35 seconds
Started Sep 09 10:49:55 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867875615 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.867875615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.777453760
Short name T986
Test name
Test status
Simulation time 14035806 ps
CPU time 1.28 seconds
Started Sep 09 10:49:55 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 215384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777453760 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.777453760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.635800612
Short name T293
Test name
Test status
Simulation time 141195626 ps
CPU time 1.53 seconds
Started Sep 09 10:49:56 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635800612 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.635800612
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.3933194559
Short name T988
Test name
Test status
Simulation time 52442479 ps
CPU time 3.59 seconds
Started Sep 09 10:49:54 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933194559 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3933194559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.3614941448
Short name T308
Test name
Test status
Simulation time 86375175 ps
CPU time 2.81 seconds
Started Sep 09 10:49:55 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614941448 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3614941448
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.795313300
Short name T1079
Test name
Test status
Simulation time 41848449 ps
CPU time 1.1 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795313300 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.795313300
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.1337571584
Short name T1078
Test name
Test status
Simulation time 14905213 ps
CPU time 1.04 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337571584 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1337571584
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.1279544118
Short name T1080
Test name
Test status
Simulation time 12494323 ps
CPU time 0.98 seconds
Started Sep 09 10:50:12 AM UTC 24
Finished Sep 09 10:50:14 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279544118 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1279544118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.153344996
Short name T1089
Test name
Test status
Simulation time 41974526 ps
CPU time 1.05 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153344996 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.153344996
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2148597123
Short name T1087
Test name
Test status
Simulation time 56390306 ps
CPU time 0.92 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148597123 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2148597123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1728964422
Short name T1086
Test name
Test status
Simulation time 29774822 ps
CPU time 0.85 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728964422 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1728964422
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.2138696053
Short name T1090
Test name
Test status
Simulation time 17133255 ps
CPU time 0.89 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138696053 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2138696053
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1577730294
Short name T1091
Test name
Test status
Simulation time 27029201 ps
CPU time 0.97 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577730294 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1577730294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3661660152
Short name T1092
Test name
Test status
Simulation time 12616672 ps
CPU time 0.97 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661660152 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3661660152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3443556496
Short name T1093
Test name
Test status
Simulation time 15418644 ps
CPU time 1.06 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443556496 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3443556496
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.4209423892
Short name T992
Test name
Test status
Simulation time 34930400 ps
CPU time 1.84 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:50:00 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209423892 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4209423892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.4192275929
Short name T996
Test name
Test status
Simulation time 37542614 ps
CPU time 2.23 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:50:01 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192275929 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4192275929
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.722182467
Short name T989
Test name
Test status
Simulation time 37895210 ps
CPU time 1.03 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722182467 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.722182467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3221398636
Short name T997
Test name
Test status
Simulation time 42311734 ps
CPU time 1.46 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:01 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3221398636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3221398636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2024437827
Short name T283
Test name
Test status
Simulation time 25572602 ps
CPU time 1.01 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024437827 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2024437827
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.2325517610
Short name T991
Test name
Test status
Simulation time 37894899 ps
CPU time 1.15 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325517610 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2325517610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.3599979058
Short name T294
Test name
Test status
Simulation time 37787629 ps
CPU time 1.47 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:50:00 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599979058 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.3599979058
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.2387080034
Short name T994
Test name
Test status
Simulation time 30543341 ps
CPU time 2.42 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:50:00 AM UTC 24
Peak memory 227844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387080034 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2387080034
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.3909416022
Short name T993
Test name
Test status
Simulation time 93030455 ps
CPU time 2.3 seconds
Started Sep 09 10:49:57 AM UTC 24
Finished Sep 09 10:50:00 AM UTC 24
Peak memory 217700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909416022 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3909416022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.983688167
Short name T1094
Test name
Test status
Simulation time 13289304 ps
CPU time 1.07 seconds
Started Sep 09 10:50:13 AM UTC 24
Finished Sep 09 10:50:16 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983688167 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.983688167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.4099289002
Short name T1100
Test name
Test status
Simulation time 34717496 ps
CPU time 1 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099289002 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4099289002
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.1286747426
Short name T1099
Test name
Test status
Simulation time 15664001 ps
CPU time 0.95 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286747426 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1286747426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3637861650
Short name T1098
Test name
Test status
Simulation time 13136684 ps
CPU time 1.05 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637861650 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3637861650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.718963835
Short name T1101
Test name
Test status
Simulation time 34667893 ps
CPU time 0.98 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718963835 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.718963835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3958055955
Short name T1103
Test name
Test status
Simulation time 16294867 ps
CPU time 1.14 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958055955 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3958055955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3909214771
Short name T1104
Test name
Test status
Simulation time 14673073 ps
CPU time 1.05 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909214771 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3909214771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.142816290
Short name T1102
Test name
Test status
Simulation time 40915358 ps
CPU time 1.03 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142816290 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.142816290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.1485924519
Short name T1111
Test name
Test status
Simulation time 23705069 ps
CPU time 1.31 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485924519 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1485924519
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.844127590
Short name T1106
Test name
Test status
Simulation time 38507154 ps
CPU time 1 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844127590 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.844127590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.166577666
Short name T285
Test name
Test status
Simulation time 29712328 ps
CPU time 1.29 seconds
Started Sep 09 10:49:59 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166577666 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.166577666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.1342689857
Short name T289
Test name
Test status
Simulation time 110793569 ps
CPU time 3.08 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342689857 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1342689857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.4021789878
Short name T284
Test name
Test status
Simulation time 60757498 ps
CPU time 1.15 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:01 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021789878 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4021789878
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3360308021
Short name T998
Test name
Test status
Simulation time 49397072 ps
CPU time 1.15 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3360308021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3360308021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2125281973
Short name T295
Test name
Test status
Simulation time 12168100 ps
CPU time 0.99 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:00 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125281973 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2125281973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.582763236
Short name T995
Test name
Test status
Simulation time 19869510 ps
CPU time 1 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:00 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582763236 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.582763236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.1096124832
Short name T296
Test name
Test status
Simulation time 182134128 ps
CPU time 1.41 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096124832 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.1096124832
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2567672868
Short name T1011
Test name
Test status
Simulation time 121789603 ps
CPU time 4.33 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:04 AM UTC 24
Peak memory 228052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567672868 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2567672868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.3355414194
Short name T313
Test name
Test status
Simulation time 42865265 ps
CPU time 1.76 seconds
Started Sep 09 10:49:58 AM UTC 24
Finished Sep 09 10:50:01 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355414194 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3355414194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.2270036323
Short name T1107
Test name
Test status
Simulation time 11923656 ps
CPU time 0.92 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270036323 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2270036323
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1529368044
Short name T1105
Test name
Test status
Simulation time 41363595 ps
CPU time 0.96 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529368044 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1529368044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.570325968
Short name T1108
Test name
Test status
Simulation time 45134295 ps
CPU time 0.91 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570325968 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.570325968
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2646937068
Short name T1109
Test name
Test status
Simulation time 23756419 ps
CPU time 0.98 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646937068 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2646937068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2461442345
Short name T1110
Test name
Test status
Simulation time 44312074 ps
CPU time 1.02 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:20 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461442345 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2461442345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.10627516
Short name T1113
Test name
Test status
Simulation time 25968625 ps
CPU time 1.09 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:30 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10627516 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.10627516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.71455806
Short name T1112
Test name
Test status
Simulation time 25856474 ps
CPU time 1.01 seconds
Started Sep 09 10:50:15 AM UTC 24
Finished Sep 09 10:50:30 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71455806 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.71455806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3758407358
Short name T1095
Test name
Test status
Simulation time 71640240 ps
CPU time 0.75 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:50:19 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758407358 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3758407358
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.588243459
Short name T1096
Test name
Test status
Simulation time 33087854 ps
CPU time 0.73 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:50:19 AM UTC 24
Peak memory 215372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588243459 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.588243459
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.461846699
Short name T1097
Test name
Test status
Simulation time 12514474 ps
CPU time 0.82 seconds
Started Sep 09 10:50:16 AM UTC 24
Finished Sep 09 10:50:19 AM UTC 24
Peak memory 215384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461846699 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.461846699
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1376211832
Short name T1002
Test name
Test status
Simulation time 255208809 ps
CPU time 1.62 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1376211832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1376211832
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.4066804128
Short name T297
Test name
Test status
Simulation time 40164415 ps
CPU time 1.18 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066804128 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4066804128
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.1944655667
Short name T999
Test name
Test status
Simulation time 38034078 ps
CPU time 1.06 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944655667 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1944655667
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.2619746995
Short name T1000
Test name
Test status
Simulation time 13808334 ps
CPU time 1.19 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619746995 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.2619746995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1473204273
Short name T1009
Test name
Test status
Simulation time 53850900 ps
CPU time 2.64 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:04 AM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473204273 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1473204273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.944798797
Short name T1001
Test name
Test status
Simulation time 50193335 ps
CPU time 1.62 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:02 AM UTC 24
Peak memory 215340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944798797 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.944798797
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1489318822
Short name T1010
Test name
Test status
Simulation time 23742214 ps
CPU time 1.44 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:04 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1489318822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1489318822
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.2551290127
Short name T1006
Test name
Test status
Simulation time 40195744 ps
CPU time 1.26 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551290127 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2551290127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2566714083
Short name T1005
Test name
Test status
Simulation time 13859361 ps
CPU time 1.34 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566714083 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2566714083
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3626358743
Short name T1007
Test name
Test status
Simulation time 14023115 ps
CPU time 1.13 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626358743 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.3626358743
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.4174613689
Short name T1015
Test name
Test status
Simulation time 69954270 ps
CPU time 3.46 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174613689 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4174613689
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.926949161
Short name T1003
Test name
Test status
Simulation time 62989848 ps
CPU time 1.82 seconds
Started Sep 09 10:50:00 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926949161 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.926949161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2066995783
Short name T1012
Test name
Test status
Simulation time 15853528 ps
CPU time 1.36 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:04 AM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2066995783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2066995783
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.365240399
Short name T1008
Test name
Test status
Simulation time 33836946 ps
CPU time 1.14 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365240399 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.365240399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.575160161
Short name T1004
Test name
Test status
Simulation time 12441770 ps
CPU time 1 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:03 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575160161 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.575160161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2011513003
Short name T1013
Test name
Test status
Simulation time 162953388 ps
CPU time 1.55 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:04 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011513003 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.2011513003
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.198519169
Short name T1022
Test name
Test status
Simulation time 235962023 ps
CPU time 3.06 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198519169 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.198519169
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.4103022859
Short name T1016
Test name
Test status
Simulation time 400958461 ps
CPU time 2.34 seconds
Started Sep 09 10:50:01 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103022859 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4103022859
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.81814899
Short name T1024
Test name
Test status
Simulation time 168378162 ps
CPU time 1.73 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:06 AM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=81814899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.81814899
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3889726974
Short name T1017
Test name
Test status
Simulation time 39665341 ps
CPU time 0.98 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889726974 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3889726974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.3983513782
Short name T1018
Test name
Test status
Simulation time 16038405 ps
CPU time 1.26 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983513782 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3983513782
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.831309958
Short name T1020
Test name
Test status
Simulation time 114838183 ps
CPU time 1.28 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831309958 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.831309958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.1105370788
Short name T1038
Test name
Test status
Simulation time 979385034 ps
CPU time 4.42 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 228068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105370788 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1105370788
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2016867679
Short name T1035
Test name
Test status
Simulation time 194185681 ps
CPU time 4.2 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016867679 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2016867679
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2034052903
Short name T1031
Test name
Test status
Simulation time 19788955 ps
CPU time 1.72 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:07 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2034052903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2034052903
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3708666775
Short name T1019
Test name
Test status
Simulation time 12503729 ps
CPU time 0.95 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708666775 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3708666775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.1120774267
Short name T1021
Test name
Test status
Simulation time 12128178 ps
CPU time 1.32 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:05 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120774267 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1120774267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.795088761
Short name T1025
Test name
Test status
Simulation time 57871437 ps
CPU time 1.1 seconds
Started Sep 09 10:50:04 AM UTC 24
Finished Sep 09 10:50:06 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795088761 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.795088761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.4135813132
Short name T1034
Test name
Test status
Simulation time 108428041 ps
CPU time 3.8 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:08 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135813132 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4135813132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.4205778615
Short name T1023
Test name
Test status
Simulation time 51655734 ps
CPU time 1.65 seconds
Started Sep 09 10:50:03 AM UTC 24
Finished Sep 09 10:50:06 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205778615 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4205778615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.2442118697
Short name T9
Test name
Test status
Simulation time 113124157 ps
CPU time 1.02 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:40:46 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442118697 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.2442118697
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_intr.599415859
Short name T4
Test name
Test status
Simulation time 21662096 ps
CPU time 1.65 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:40:46 AM UTC 24
Peak memory 228484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599415859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.599415859
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_sec_cm.1236257727
Short name T16
Test name
Test status
Simulation time 1126361483 ps
CPU time 4.84 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:40:50 AM UTC 24
Peak memory 260436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236257727 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1236257727
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_smoke.477622485
Short name T1
Test name
Test status
Simulation time 132804770 ps
CPU time 1.4 seconds
Started Sep 09 11:40:41 AM UTC 24
Finished Sep 09 11:40:43 AM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477622485 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.edn_smoke.477622485
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_stress_all.4277172383
Short name T3
Test name
Test status
Simulation time 84881814 ps
CPU time 1.71 seconds
Started Sep 09 11:40:42 AM UTC 24
Finished Sep 09 11:40:45 AM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277172383 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4277172383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.3012787328
Short name T35
Test name
Test status
Simulation time 14767538637 ps
CPU time 58.47 seconds
Started Sep 09 11:40:44 AM UTC 24
Finished Sep 09 11:41:44 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3012787328 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_
with_rand_reset.3012787328
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_alert.3668651871
Short name T15
Test name
Test status
Simulation time 32547121 ps
CPU time 1.99 seconds
Started Sep 09 11:40:48 AM UTC 24
Finished Sep 09 11:40:51 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668651871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.3668651871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_alert_test.1266178839
Short name T67
Test name
Test status
Simulation time 56523044 ps
CPU time 1.43 seconds
Started Sep 09 11:40:49 AM UTC 24
Finished Sep 09 11:40:52 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266178839 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1266178839
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_disable.1792866328
Short name T24
Test name
Test status
Simulation time 10746432 ps
CPU time 1.04 seconds
Started Sep 09 11:40:48 AM UTC 24
Finished Sep 09 11:40:50 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792866328 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1792866328
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_genbits.4127509121
Short name T27
Test name
Test status
Simulation time 41133243 ps
CPU time 1.74 seconds
Started Sep 09 11:40:47 AM UTC 24
Finished Sep 09 11:40:49 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127509121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4127509121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_intr.3148860761
Short name T28
Test name
Test status
Simulation time 39852112 ps
CPU time 1.2 seconds
Started Sep 09 11:40:48 AM UTC 24
Finished Sep 09 11:40:50 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148860761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.3148860761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_regwen.1810833744
Short name T23
Test name
Test status
Simulation time 20511893 ps
CPU time 1.51 seconds
Started Sep 09 11:40:46 AM UTC 24
Finished Sep 09 11:40:48 AM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810833744 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.1810833744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_smoke.1189077487
Short name T70
Test name
Test status
Simulation time 15941904 ps
CPU time 1.49 seconds
Started Sep 09 11:40:45 AM UTC 24
Finished Sep 09 11:40:48 AM UTC 24
Peak memory 225972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189077487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.1189077487
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.318855672
Short name T245
Test name
Test status
Simulation time 5542171073 ps
CPU time 88.02 seconds
Started Sep 09 11:40:48 AM UTC 24
Finished Sep 09 11:42:18 AM UTC 24
Peak memory 233820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=318855672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_w
ith_rand_reset.318855672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_alert.1084145962
Short name T140
Test name
Test status
Simulation time 95302659 ps
CPU time 1.78 seconds
Started Sep 09 11:41:24 AM UTC 24
Finished Sep 09 11:41:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084145962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.1084145962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_alert_test.1347501520
Short name T273
Test name
Test status
Simulation time 24509625 ps
CPU time 1.51 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:41:28 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347501520 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1347501520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_disable.3202673384
Short name T75
Test name
Test status
Simulation time 12197188 ps
CPU time 1.33 seconds
Started Sep 09 11:41:24 AM UTC 24
Finished Sep 09 11:41:27 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202673384 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3202673384
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.3830199322
Short name T156
Test name
Test status
Simulation time 64375577 ps
CPU time 1.84 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:41:29 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830199322 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.3830199322
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_err.4214606844
Short name T230
Test name
Test status
Simulation time 41808361 ps
CPU time 1.81 seconds
Started Sep 09 11:41:24 AM UTC 24
Finished Sep 09 11:41:27 AM UTC 24
Peak memory 242128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214606844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.4214606844
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_genbits.743632759
Short name T13
Test name
Test status
Simulation time 28956271 ps
CPU time 1.49 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743632759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_genbits.743632759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_intr.2090719281
Short name T117
Test name
Test status
Simulation time 69461432 ps
CPU time 1.26 seconds
Started Sep 09 11:41:24 AM UTC 24
Finished Sep 09 11:41:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090719281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.2090719281
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_smoke.4191557730
Short name T371
Test name
Test status
Simulation time 32027812 ps
CPU time 1.42 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191557730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.4191557730
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_stress_all.1567246504
Short name T274
Test name
Test status
Simulation time 318451108 ps
CPU time 5.79 seconds
Started Sep 09 11:41:23 AM UTC 24
Finished Sep 09 11:41:30 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567246504 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1567246504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.1208213004
Short name T247
Test name
Test status
Simulation time 9123639828 ps
CPU time 67.93 seconds
Started Sep 09 11:41:23 AM UTC 24
Finished Sep 09 11:42:33 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1208213004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all
_with_rand_reset.1208213004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/100.edn_alert.1141621452
Short name T697
Test name
Test status
Simulation time 80620606 ps
CPU time 1.31 seconds
Started Sep 09 11:44:12 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141621452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 100.edn_alert.1141621452
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/100.edn_genbits.2659260547
Short name T699
Test name
Test status
Simulation time 39191095 ps
CPU time 1.84 seconds
Started Sep 09 11:44:12 AM UTC 24
Finished Sep 09 11:44:15 AM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659260547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2659260547
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/101.edn_genbits.1217222356
Short name T704
Test name
Test status
Simulation time 37745506 ps
CPU time 1.62 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:16 AM UTC 24
Peak memory 228288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217222356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1217222356
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/102.edn_alert.3284450021
Short name T703
Test name
Test status
Simulation time 25322340 ps
CPU time 1.51 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:16 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284450021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.3284450021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/102.edn_genbits.3919710397
Short name T706
Test name
Test status
Simulation time 100873011 ps
CPU time 1.95 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:16 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919710397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3919710397
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/103.edn_alert.3788076781
Short name T702
Test name
Test status
Simulation time 24930210 ps
CPU time 1.42 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:15 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788076781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.3788076781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/103.edn_genbits.3899673550
Short name T700
Test name
Test status
Simulation time 222824086 ps
CPU time 1.17 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:15 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899673550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3899673550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/104.edn_alert.752015207
Short name T707
Test name
Test status
Simulation time 57823701 ps
CPU time 1.26 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752015207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 104.edn_alert.752015207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/104.edn_genbits.1626054363
Short name T705
Test name
Test status
Simulation time 94183087 ps
CPU time 1.39 seconds
Started Sep 09 11:44:13 AM UTC 24
Finished Sep 09 11:44:16 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626054363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1626054363
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/105.edn_alert.2650486471
Short name T711
Test name
Test status
Simulation time 43923221 ps
CPU time 1.71 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650486471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 105.edn_alert.2650486471
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/105.edn_genbits.355037768
Short name T343
Test name
Test status
Simulation time 64608891 ps
CPU time 2.64 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 231556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355037768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 105.edn_genbits.355037768
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/106.edn_genbits.1010753256
Short name T712
Test name
Test status
Simulation time 40171909 ps
CPU time 1.64 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010753256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1010753256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/107.edn_alert.1555199232
Short name T709
Test name
Test status
Simulation time 87441345 ps
CPU time 1.25 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555199232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.1555199232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/107.edn_genbits.3761899793
Short name T708
Test name
Test status
Simulation time 87729782 ps
CPU time 1.32 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761899793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3761899793
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/108.edn_genbits.4181826494
Short name T714
Test name
Test status
Simulation time 32251553 ps
CPU time 1.9 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181826494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4181826494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/109.edn_alert.3106878498
Short name T305
Test name
Test status
Simulation time 93738323 ps
CPU time 1.29 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106878498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.3106878498
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/109.edn_genbits.2084680869
Short name T713
Test name
Test status
Simulation time 130019387 ps
CPU time 1.48 seconds
Started Sep 09 11:44:14 AM UTC 24
Finished Sep 09 11:44:17 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084680869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2084680869
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_alert.1019252408
Short name T79
Test name
Test status
Simulation time 24233558 ps
CPU time 1.75 seconds
Started Sep 09 11:41:27 AM UTC 24
Finished Sep 09 11:41:30 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019252408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.1019252408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_alert_test.958097122
Short name T372
Test name
Test status
Simulation time 17640819 ps
CPU time 1.36 seconds
Started Sep 09 11:41:29 AM UTC 24
Finished Sep 09 11:41:32 AM UTC 24
Peak memory 216804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958097122 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.958097122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.1495787740
Short name T110
Test name
Test status
Simulation time 77788502 ps
CPU time 1.64 seconds
Started Sep 09 11:41:28 AM UTC 24
Finished Sep 09 11:41:31 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495787740 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.1495787740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_err.2803818558
Short name T135
Test name
Test status
Simulation time 39963133 ps
CPU time 1.42 seconds
Started Sep 09 11:41:27 AM UTC 24
Finished Sep 09 11:41:30 AM UTC 24
Peak memory 243796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803818558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.2803818558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_intr.3950082853
Short name T55
Test name
Test status
Simulation time 28324266 ps
CPU time 1.38 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:41:29 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950082853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.3950082853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_smoke.4131670282
Short name T134
Test name
Test status
Simulation time 21556184 ps
CPU time 1.35 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:41:28 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131670282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.4131670282
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_stress_all.2930937889
Short name T124
Test name
Test status
Simulation time 148294489 ps
CPU time 4.68 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:41:32 AM UTC 24
Peak memory 227528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930937889 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2930937889
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.2988848264
Short name T514
Test name
Test status
Simulation time 7718748555 ps
CPU time 102.95 seconds
Started Sep 09 11:41:26 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 231848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2988848264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all
_with_rand_reset.2988848264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/110.edn_genbits.1155732368
Short name T719
Test name
Test status
Simulation time 100278149 ps
CPU time 1.62 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155732368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1155732368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/111.edn_alert.3385018558
Short name T717
Test name
Test status
Simulation time 48818831 ps
CPU time 1.44 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385018558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.3385018558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/111.edn_genbits.1404154255
Short name T715
Test name
Test status
Simulation time 91638404 ps
CPU time 1.16 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404154255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1404154255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/112.edn_alert.3588263313
Short name T720
Test name
Test status
Simulation time 27982467 ps
CPU time 1.49 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588263313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.3588263313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/113.edn_alert.2426056717
Short name T721
Test name
Test status
Simulation time 23559218 ps
CPU time 1.25 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426056717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.2426056717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/113.edn_genbits.4258890326
Short name T716
Test name
Test status
Simulation time 26754878 ps
CPU time 1.04 seconds
Started Sep 09 11:44:16 AM UTC 24
Finished Sep 09 11:44:18 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258890326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4258890326
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/114.edn_alert.3028886816
Short name T728
Test name
Test status
Simulation time 29456383 ps
CPU time 1.76 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028886816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.3028886816
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/114.edn_genbits.687536238
Short name T725
Test name
Test status
Simulation time 105081532 ps
CPU time 1.55 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687536238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 114.edn_genbits.687536238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/115.edn_alert.4152562920
Short name T726
Test name
Test status
Simulation time 25276912 ps
CPU time 1.44 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152562920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.4152562920
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/115.edn_genbits.2486297750
Short name T723
Test name
Test status
Simulation time 46921610 ps
CPU time 1.48 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486297750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2486297750
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/116.edn_alert.2371322446
Short name T722
Test name
Test status
Simulation time 91105459 ps
CPU time 1.32 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371322446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.2371322446
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/116.edn_genbits.2915071725
Short name T727
Test name
Test status
Simulation time 38455288 ps
CPU time 1.72 seconds
Started Sep 09 11:44:17 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915071725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2915071725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/117.edn_alert.1101370344
Short name T729
Test name
Test status
Simulation time 102560952 ps
CPU time 1.58 seconds
Started Sep 09 11:44:18 AM UTC 24
Finished Sep 09 11:44:21 AM UTC 24
Peak memory 227920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101370344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.1101370344
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/117.edn_genbits.397234267
Short name T685
Test name
Test status
Simulation time 183715544 ps
CPU time 1.21 seconds
Started Sep 09 11:44:18 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 226112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397234267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 117.edn_genbits.397234267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/118.edn_alert.2616733147
Short name T730
Test name
Test status
Simulation time 47241531 ps
CPU time 1.29 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:21 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616733147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.2616733147
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/118.edn_genbits.4268573761
Short name T724
Test name
Test status
Simulation time 334181916 ps
CPU time 1.28 seconds
Started Sep 09 11:44:18 AM UTC 24
Finished Sep 09 11:44:20 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268573761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4268573761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/119.edn_alert.4067607670
Short name T731
Test name
Test status
Simulation time 120317711 ps
CPU time 1.09 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:21 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067607670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.4067607670
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/119.edn_genbits.2232094142
Short name T737
Test name
Test status
Simulation time 40715570 ps
CPU time 1.78 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232094142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2232094142
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_alert.3226570847
Short name T83
Test name
Test status
Simulation time 29644224 ps
CPU time 1.6 seconds
Started Sep 09 11:41:31 AM UTC 24
Finished Sep 09 11:41:33 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226570847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.3226570847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_alert_test.3803009893
Short name T375
Test name
Test status
Simulation time 18282220 ps
CPU time 1.37 seconds
Started Sep 09 11:41:32 AM UTC 24
Finished Sep 09 11:41:35 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803009893 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3803009893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_disable.3805902855
Short name T84
Test name
Test status
Simulation time 14159670 ps
CPU time 1.43 seconds
Started Sep 09 11:41:32 AM UTC 24
Finished Sep 09 11:41:35 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805902855 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3805902855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.501729972
Short name T377
Test name
Test status
Simulation time 30433501 ps
CPU time 1.72 seconds
Started Sep 09 11:41:32 AM UTC 24
Finished Sep 09 11:41:35 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501729972 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.501729972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_err.3410313605
Short name T115
Test name
Test status
Simulation time 52161368 ps
CPU time 1.29 seconds
Started Sep 09 11:41:31 AM UTC 24
Finished Sep 09 11:41:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410313605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.3410313605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_genbits.316878031
Short name T374
Test name
Test status
Simulation time 54333122 ps
CPU time 1.87 seconds
Started Sep 09 11:41:30 AM UTC 24
Finished Sep 09 11:41:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316878031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_genbits.316878031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_intr.3526169422
Short name T93
Test name
Test status
Simulation time 23971802 ps
CPU time 1.66 seconds
Started Sep 09 11:41:31 AM UTC 24
Finished Sep 09 11:41:33 AM UTC 24
Peak memory 237280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526169422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.3526169422
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_smoke.415322236
Short name T373
Test name
Test status
Simulation time 19134965 ps
CPU time 1.45 seconds
Started Sep 09 11:41:30 AM UTC 24
Finished Sep 09 11:41:32 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415322236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.edn_smoke.415322236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_stress_all.3617067317
Short name T128
Test name
Test status
Simulation time 808236608 ps
CPU time 6.39 seconds
Started Sep 09 11:41:30 AM UTC 24
Finished Sep 09 11:41:37 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617067317 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3617067317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.1848801047
Short name T540
Test name
Test status
Simulation time 18458905187 ps
CPU time 111.21 seconds
Started Sep 09 11:41:30 AM UTC 24
Finished Sep 09 11:43:23 AM UTC 24
Peak memory 233884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1848801047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all
_with_rand_reset.1848801047
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/120.edn_alert.2834300065
Short name T733
Test name
Test status
Simulation time 102321873 ps
CPU time 1.44 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834300065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.2834300065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/120.edn_genbits.2856348083
Short name T739
Test name
Test status
Simulation time 76503028 ps
CPU time 1.99 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856348083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2856348083
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/121.edn_alert.1937013149
Short name T735
Test name
Test status
Simulation time 75454784 ps
CPU time 1.36 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937013149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.1937013149
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/121.edn_genbits.3877483864
Short name T743
Test name
Test status
Simulation time 298479120 ps
CPU time 2.92 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:23 AM UTC 24
Peak memory 231484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877483864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3877483864
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/122.edn_alert.228709984
Short name T738
Test name
Test status
Simulation time 48873608 ps
CPU time 1.61 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228709984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 122.edn_alert.228709984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/122.edn_genbits.4244074199
Short name T741
Test name
Test status
Simulation time 35823397 ps
CPU time 1.97 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244074199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4244074199
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/123.edn_alert.3182451088
Short name T734
Test name
Test status
Simulation time 27195375 ps
CPU time 1.23 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182451088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.3182451088
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/124.edn_alert.1802511785
Short name T740
Test name
Test status
Simulation time 89073197 ps
CPU time 1.71 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802511785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.1802511785
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/124.edn_genbits.1961765105
Short name T751
Test name
Test status
Simulation time 743889838 ps
CPU time 4.72 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:25 AM UTC 24
Peak memory 231500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961765105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1961765105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/125.edn_alert.3027119984
Short name T732
Test name
Test status
Simulation time 68352681 ps
CPU time 1.19 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027119984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.3027119984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/125.edn_genbits.842665752
Short name T736
Test name
Test status
Simulation time 40992079 ps
CPU time 1.39 seconds
Started Sep 09 11:44:19 AM UTC 24
Finished Sep 09 11:44:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842665752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 125.edn_genbits.842665752
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/126.edn_alert.986440667
Short name T742
Test name
Test status
Simulation time 76728582 ps
CPU time 1.07 seconds
Started Sep 09 11:44:20 AM UTC 24
Finished Sep 09 11:44:23 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986440667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 126.edn_alert.986440667
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/127.edn_alert.2606322834
Short name T748
Test name
Test status
Simulation time 46247420 ps
CPU time 1.58 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606322834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.2606322834
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/127.edn_genbits.3543909548
Short name T744
Test name
Test status
Simulation time 90128892 ps
CPU time 1.28 seconds
Started Sep 09 11:44:21 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543909548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3543909548
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/128.edn_alert.3633816027
Short name T159
Test name
Test status
Simulation time 45473109 ps
CPU time 1.01 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 228116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633816027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.3633816027
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/129.edn_alert.772459734
Short name T746
Test name
Test status
Simulation time 39795854 ps
CPU time 1.33 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772459734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 129.edn_alert.772459734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/129.edn_genbits.3101002855
Short name T758
Test name
Test status
Simulation time 77240388 ps
CPU time 2.95 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101002855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3101002855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_alert.1452490068
Short name T58
Test name
Test status
Simulation time 72047490 ps
CPU time 1.65 seconds
Started Sep 09 11:41:35 AM UTC 24
Finished Sep 09 11:41:38 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452490068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.1452490068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_alert_test.3422487066
Short name T379
Test name
Test status
Simulation time 24395214 ps
CPU time 1.28 seconds
Started Sep 09 11:41:36 AM UTC 24
Finished Sep 09 11:41:38 AM UTC 24
Peak memory 217228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422487066 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3422487066
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_disable.3741484218
Short name T196
Test name
Test status
Simulation time 35796865 ps
CPU time 1.32 seconds
Started Sep 09 11:41:35 AM UTC 24
Finished Sep 09 11:41:37 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741484218 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3741484218
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2505324005
Short name T378
Test name
Test status
Simulation time 128688857 ps
CPU time 1.78 seconds
Started Sep 09 11:41:35 AM UTC 24
Finished Sep 09 11:41:38 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505324005 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2505324005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_err.3832016094
Short name T231
Test name
Test status
Simulation time 54359779 ps
CPU time 1.55 seconds
Started Sep 09 11:41:35 AM UTC 24
Finished Sep 09 11:41:38 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832016094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.3832016094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_genbits.1196611985
Short name T56
Test name
Test status
Simulation time 69050422 ps
CPU time 2.2 seconds
Started Sep 09 11:41:32 AM UTC 24
Finished Sep 09 11:41:36 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196611985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1196611985
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_smoke.1161795235
Short name T376
Test name
Test status
Simulation time 24924441 ps
CPU time 1.39 seconds
Started Sep 09 11:41:32 AM UTC 24
Finished Sep 09 11:41:35 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161795235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.1161795235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/13.edn_stress_all.3995804048
Short name T358
Test name
Test status
Simulation time 160582394 ps
CPU time 4 seconds
Started Sep 09 11:41:33 AM UTC 24
Finished Sep 09 11:41:38 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995804048 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3995804048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/130.edn_genbits.1612154431
Short name T745
Test name
Test status
Simulation time 59966631 ps
CPU time 1.32 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 228548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612154431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1612154431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/131.edn_alert.2652217064
Short name T750
Test name
Test status
Simulation time 79072675 ps
CPU time 1.03 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:25 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652217064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.2652217064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/131.edn_genbits.1430539632
Short name T749
Test name
Test status
Simulation time 96946222 ps
CPU time 1.57 seconds
Started Sep 09 11:44:22 AM UTC 24
Finished Sep 09 11:44:24 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430539632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1430539632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/132.edn_alert.1615978383
Short name T756
Test name
Test status
Simulation time 26006814 ps
CPU time 1.47 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615978383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.1615978383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/132.edn_genbits.1741469917
Short name T753
Test name
Test status
Simulation time 89082969 ps
CPU time 1.27 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741469917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1741469917
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/133.edn_alert.741441623
Short name T752
Test name
Test status
Simulation time 70461595 ps
CPU time 1.11 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:25 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741441623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 133.edn_alert.741441623
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/133.edn_genbits.1766486743
Short name T754
Test name
Test status
Simulation time 55189631 ps
CPU time 1.23 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766486743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1766486743
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/134.edn_alert.1293889497
Short name T755
Test name
Test status
Simulation time 23750696 ps
CPU time 1.29 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293889497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.1293889497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/134.edn_genbits.2795178080
Short name T764
Test name
Test status
Simulation time 76670334 ps
CPU time 2.47 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:27 AM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795178080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2795178080
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/135.edn_alert.997344517
Short name T759
Test name
Test status
Simulation time 80156756 ps
CPU time 1.22 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997344517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 135.edn_alert.997344517
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/135.edn_genbits.4171622908
Short name T761
Test name
Test status
Simulation time 54144975 ps
CPU time 1.51 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171622908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.4171622908
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/136.edn_alert.328979103
Short name T760
Test name
Test status
Simulation time 25597208 ps
CPU time 1.23 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328979103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 136.edn_alert.328979103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/136.edn_genbits.1793615628
Short name T757
Test name
Test status
Simulation time 151042310 ps
CPU time 1.31 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793615628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1793615628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/137.edn_alert.2875216474
Short name T762
Test name
Test status
Simulation time 34915321 ps
CPU time 1.54 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875216474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.2875216474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/137.edn_genbits.1522657638
Short name T352
Test name
Test status
Simulation time 96114728 ps
CPU time 1.38 seconds
Started Sep 09 11:44:23 AM UTC 24
Finished Sep 09 11:44:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522657638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1522657638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/138.edn_alert.447261944
Short name T766
Test name
Test status
Simulation time 25105281 ps
CPU time 1.45 seconds
Started Sep 09 11:44:24 AM UTC 24
Finished Sep 09 11:44:27 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447261944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 138.edn_alert.447261944
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/138.edn_genbits.1475831416
Short name T329
Test name
Test status
Simulation time 55480783 ps
CPU time 1.31 seconds
Started Sep 09 11:44:24 AM UTC 24
Finished Sep 09 11:44:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475831416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1475831416
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/139.edn_alert.2197441350
Short name T763
Test name
Test status
Simulation time 27485643 ps
CPU time 1.25 seconds
Started Sep 09 11:44:25 AM UTC 24
Finished Sep 09 11:44:27 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197441350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.2197441350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/139.edn_genbits.1744427343
Short name T765
Test name
Test status
Simulation time 33189611 ps
CPU time 1.24 seconds
Started Sep 09 11:44:24 AM UTC 24
Finished Sep 09 11:44:27 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744427343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1744427343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_alert_test.3002016429
Short name T383
Test name
Test status
Simulation time 18354878 ps
CPU time 1.34 seconds
Started Sep 09 11:41:39 AM UTC 24
Finished Sep 09 11:41:42 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002016429 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3002016429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_disable.2274184218
Short name T238
Test name
Test status
Simulation time 41923976 ps
CPU time 1.33 seconds
Started Sep 09 11:41:39 AM UTC 24
Finished Sep 09 11:41:41 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274184218 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2274184218
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.2110581734
Short name T94
Test name
Test status
Simulation time 106507834 ps
CPU time 1.67 seconds
Started Sep 09 11:41:39 AM UTC 24
Finished Sep 09 11:41:42 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110581734 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.2110581734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_err.3731426753
Short name T203
Test name
Test status
Simulation time 25347431 ps
CPU time 1.18 seconds
Started Sep 09 11:41:39 AM UTC 24
Finished Sep 09 11:41:41 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731426753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.3731426753
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_genbits.3331539869
Short name T380
Test name
Test status
Simulation time 40247318 ps
CPU time 1.39 seconds
Started Sep 09 11:41:36 AM UTC 24
Finished Sep 09 11:41:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331539869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3331539869
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_intr.3892940323
Short name T381
Test name
Test status
Simulation time 29989518 ps
CPU time 1.29 seconds
Started Sep 09 11:41:37 AM UTC 24
Finished Sep 09 11:41:40 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892940323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.3892940323
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_smoke.4041748945
Short name T133
Test name
Test status
Simulation time 37141971 ps
CPU time 1.41 seconds
Started Sep 09 11:41:36 AM UTC 24
Finished Sep 09 11:41:39 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041748945 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.4041748945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/14.edn_stress_all.2017128442
Short name T309
Test name
Test status
Simulation time 939210395 ps
CPU time 5.77 seconds
Started Sep 09 11:41:36 AM UTC 24
Finished Sep 09 11:41:43 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017128442 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2017128442
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/140.edn_alert.2392216798
Short name T767
Test name
Test status
Simulation time 171795881 ps
CPU time 1.29 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:28 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392216798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.2392216798
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/141.edn_alert.974575302
Short name T172
Test name
Test status
Simulation time 101931861 ps
CPU time 1.45 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:28 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974575302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 141.edn_alert.974575302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/141.edn_genbits.1898163475
Short name T772
Test name
Test status
Simulation time 56571935 ps
CPU time 2.18 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:29 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898163475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1898163475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/142.edn_alert.2643801294
Short name T768
Test name
Test status
Simulation time 27387703 ps
CPU time 1.27 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:28 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643801294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.2643801294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/142.edn_genbits.1228942233
Short name T770
Test name
Test status
Simulation time 34820822 ps
CPU time 1.75 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228942233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1228942233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/143.edn_alert.2088767670
Short name T774
Test name
Test status
Simulation time 50671832 ps
CPU time 1.32 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:29 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088767670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.2088767670
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/143.edn_genbits.3645480316
Short name T769
Test name
Test status
Simulation time 42557664 ps
CPU time 1.35 seconds
Started Sep 09 11:44:26 AM UTC 24
Finished Sep 09 11:44:28 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645480316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3645480316
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/144.edn_alert.828329591
Short name T277
Test name
Test status
Simulation time 101323441 ps
CPU time 1.01 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:29 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828329591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 144.edn_alert.828329591
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/145.edn_alert.2196800021
Short name T777
Test name
Test status
Simulation time 32089801 ps
CPU time 1.48 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196800021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 145.edn_alert.2196800021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/145.edn_genbits.303329301
Short name T784
Test name
Test status
Simulation time 87826368 ps
CPU time 2.58 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 231836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303329301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 145.edn_genbits.303329301
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/146.edn_alert.4272166819
Short name T776
Test name
Test status
Simulation time 37719191 ps
CPU time 1.37 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272166819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.4272166819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/146.edn_genbits.4288188988
Short name T792
Test name
Test status
Simulation time 184063348 ps
CPU time 3.12 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288188988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.4288188988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/147.edn_alert.678114966
Short name T779
Test name
Test status
Simulation time 83726677 ps
CPU time 1.55 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678114966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 147.edn_alert.678114966
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/147.edn_genbits.3959294456
Short name T781
Test name
Test status
Simulation time 36083982 ps
CPU time 1.81 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959294456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3959294456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/148.edn_alert.4174078057
Short name T780
Test name
Test status
Simulation time 22724178 ps
CPU time 1.55 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174078057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.4174078057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/148.edn_genbits.2189227905
Short name T783
Test name
Test status
Simulation time 42126514 ps
CPU time 1.78 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189227905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2189227905
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/149.edn_alert.554361437
Short name T778
Test name
Test status
Simulation time 30532489 ps
CPU time 1.5 seconds
Started Sep 09 11:44:28 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554361437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 149.edn_alert.554361437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/149.edn_genbits.2918926153
Short name T775
Test name
Test status
Simulation time 28119558 ps
CPU time 1.18 seconds
Started Sep 09 11:44:27 AM UTC 24
Finished Sep 09 11:44:30 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918926153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2918926153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_alert_test.938688034
Short name T252
Test name
Test status
Simulation time 53729809 ps
CPU time 1.45 seconds
Started Sep 09 11:41:42 AM UTC 24
Finished Sep 09 11:41:45 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938688034 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.938688034
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_disable.3515823685
Short name T95
Test name
Test status
Simulation time 23031769 ps
CPU time 1.34 seconds
Started Sep 09 11:41:42 AM UTC 24
Finished Sep 09 11:41:45 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515823685 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3515823685
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2973660103
Short name T102
Test name
Test status
Simulation time 103063090 ps
CPU time 1.77 seconds
Started Sep 09 11:41:42 AM UTC 24
Finished Sep 09 11:41:45 AM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973660103 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2973660103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_err.3597102803
Short name T250
Test name
Test status
Simulation time 23038294 ps
CPU time 1.35 seconds
Started Sep 09 11:41:42 AM UTC 24
Finished Sep 09 11:41:45 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597102803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_err.3597102803
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_genbits.651061192
Short name T80
Test name
Test status
Simulation time 206930641 ps
CPU time 1.94 seconds
Started Sep 09 11:41:40 AM UTC 24
Finished Sep 09 11:41:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651061192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_genbits.651061192
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_smoke.2047138200
Short name T382
Test name
Test status
Simulation time 32627665 ps
CPU time 1 seconds
Started Sep 09 11:41:39 AM UTC 24
Finished Sep 09 11:41:41 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047138200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.2047138200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/15.edn_stress_all.2911755418
Short name T116
Test name
Test status
Simulation time 124699909 ps
CPU time 2 seconds
Started Sep 09 11:41:40 AM UTC 24
Finished Sep 09 11:41:43 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911755418 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2911755418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/150.edn_alert.3600828458
Short name T785
Test name
Test status
Simulation time 78128932 ps
CPU time 1.28 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600828458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.3600828458
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/150.edn_genbits.1692386239
Short name T794
Test name
Test status
Simulation time 251109533 ps
CPU time 3.67 seconds
Started Sep 09 11:44:28 AM UTC 24
Finished Sep 09 11:44:32 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692386239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1692386239
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/151.edn_alert.1017648912
Short name T790
Test name
Test status
Simulation time 109620579 ps
CPU time 1.46 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017648912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.1017648912
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/151.edn_genbits.2670975780
Short name T786
Test name
Test status
Simulation time 45120105 ps
CPU time 1.29 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670975780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2670975780
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/152.edn_alert.3900741999
Short name T789
Test name
Test status
Simulation time 79383836 ps
CPU time 1.32 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900741999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.3900741999
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/152.edn_genbits.3168633499
Short name T802
Test name
Test status
Simulation time 143721921 ps
CPU time 3.08 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168633499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3168633499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/153.edn_alert.3486144905
Short name T788
Test name
Test status
Simulation time 25565912 ps
CPU time 1.19 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486144905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.3486144905
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/153.edn_genbits.2691983769
Short name T791
Test name
Test status
Simulation time 156380436 ps
CPU time 1.45 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691983769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2691983769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/154.edn_alert.1237522784
Short name T793
Test name
Test status
Simulation time 40763659 ps
CPU time 1.48 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:32 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237522784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 154.edn_alert.1237522784
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/154.edn_genbits.595291025
Short name T787
Test name
Test status
Simulation time 43309723 ps
CPU time 1.16 seconds
Started Sep 09 11:44:29 AM UTC 24
Finished Sep 09 11:44:31 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595291025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 154.edn_genbits.595291025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/155.edn_alert.3505891069
Short name T795
Test name
Test status
Simulation time 69490678 ps
CPU time 1.16 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:32 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505891069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.3505891069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/155.edn_genbits.2492668000
Short name T798
Test name
Test status
Simulation time 75387158 ps
CPU time 1.51 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492668000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2492668000
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/156.edn_genbits.211637858
Short name T799
Test name
Test status
Simulation time 40700372 ps
CPU time 1.46 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211637858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 156.edn_genbits.211637858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/157.edn_alert.2317040414
Short name T803
Test name
Test status
Simulation time 25548018 ps
CPU time 1.64 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 230452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317040414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.2317040414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/157.edn_genbits.1441804837
Short name T353
Test name
Test status
Simulation time 84964459 ps
CPU time 2.04 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441804837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1441804837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/158.edn_alert.3020360183
Short name T801
Test name
Test status
Simulation time 40973229 ps
CPU time 1.34 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 232140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020360183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.3020360183
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/158.edn_genbits.2907432913
Short name T805
Test name
Test status
Simulation time 63015326 ps
CPU time 1.79 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907432913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2907432913
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/159.edn_alert.1429085136
Short name T808
Test name
Test status
Simulation time 27972106 ps
CPU time 1.21 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429085136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 159.edn_alert.1429085136
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/159.edn_genbits.1429906986
Short name T797
Test name
Test status
Simulation time 78808180 ps
CPU time 1.12 seconds
Started Sep 09 11:44:30 AM UTC 24
Finished Sep 09 11:44:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429906986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1429906986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_alert_test.1152841007
Short name T384
Test name
Test status
Simulation time 13896764 ps
CPU time 1.36 seconds
Started Sep 09 11:41:46 AM UTC 24
Finished Sep 09 11:41:48 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152841007 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1152841007
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_disable.1809989365
Short name T90
Test name
Test status
Simulation time 13284877 ps
CPU time 1.42 seconds
Started Sep 09 11:41:45 AM UTC 24
Finished Sep 09 11:41:48 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809989365 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1809989365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_err.873776350
Short name T226
Test name
Test status
Simulation time 25107235 ps
CPU time 1.45 seconds
Started Sep 09 11:41:45 AM UTC 24
Finished Sep 09 11:41:48 AM UTC 24
Peak memory 230328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873776350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.edn_err.873776350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_intr.2247788005
Short name T253
Test name
Test status
Simulation time 21283903 ps
CPU time 1.78 seconds
Started Sep 09 11:41:44 AM UTC 24
Finished Sep 09 11:41:47 AM UTC 24
Peak memory 237340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247788005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.2247788005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_smoke.1738165186
Short name T251
Test name
Test status
Simulation time 41736426 ps
CPU time 1.35 seconds
Started Sep 09 11:41:43 AM UTC 24
Finished Sep 09 11:41:45 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738165186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.1738165186
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/16.edn_stress_all.1583509332
Short name T267
Test name
Test status
Simulation time 867490221 ps
CPU time 5.89 seconds
Started Sep 09 11:41:44 AM UTC 24
Finished Sep 09 11:41:51 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583509332 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1583509332
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/160.edn_alert.3089804401
Short name T806
Test name
Test status
Simulation time 23761202 ps
CPU time 1.17 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089804401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.3089804401
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/160.edn_genbits.273439569
Short name T810
Test name
Test status
Simulation time 82690220 ps
CPU time 1.52 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273439569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 160.edn_genbits.273439569
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/161.edn_alert.1981214828
Short name T807
Test name
Test status
Simulation time 22807322 ps
CPU time 1.13 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981214828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.1981214828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/161.edn_genbits.2916577960
Short name T813
Test name
Test status
Simulation time 369781550 ps
CPU time 3.31 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:36 AM UTC 24
Peak memory 231748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916577960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2916577960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/162.edn_alert.440814098
Short name T804
Test name
Test status
Simulation time 360956038 ps
CPU time 1.45 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:35 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440814098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 162.edn_alert.440814098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/162.edn_genbits.1403800490
Short name T812
Test name
Test status
Simulation time 59527547 ps
CPU time 1.22 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403800490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1403800490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/163.edn_alert.4121425499
Short name T811
Test name
Test status
Simulation time 84076334 ps
CPU time 1.4 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121425499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.4121425499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/163.edn_genbits.3160987534
Short name T782
Test name
Test status
Simulation time 104821599 ps
CPU time 1.37 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160987534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3160987534
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/164.edn_alert.294373103
Short name T771
Test name
Test status
Simulation time 217004877 ps
CPU time 1.36 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294373103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 164.edn_alert.294373103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/164.edn_genbits.4064558833
Short name T809
Test name
Test status
Simulation time 69628306 ps
CPU time 1.03 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:34 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064558833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4064558833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/165.edn_alert.1318521216
Short name T854
Test name
Test status
Simulation time 41817283 ps
CPU time 1.01 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318521216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.1318521216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/165.edn_genbits.1933693168
Short name T330
Test name
Test status
Simulation time 46785429 ps
CPU time 2.08 seconds
Started Sep 09 11:44:32 AM UTC 24
Finished Sep 09 11:44:35 AM UTC 24
Peak memory 229584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933693168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1933693168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/166.edn_alert.1682138307
Short name T834
Test name
Test status
Simulation time 125706713 ps
CPU time 1.29 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682138307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.1682138307
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/166.edn_genbits.347686152
Short name T857
Test name
Test status
Simulation time 54941043 ps
CPU time 1.3 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:56 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347686152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 166.edn_genbits.347686152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/167.edn_alert.3552725638
Short name T856
Test name
Test status
Simulation time 301567219 ps
CPU time 1.08 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552725638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.3552725638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/167.edn_genbits.3875501416
Short name T835
Test name
Test status
Simulation time 132006313 ps
CPU time 1.41 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875501416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3875501416
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/168.edn_alert.639681560
Short name T814
Test name
Test status
Simulation time 22684318 ps
CPU time 1.1 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639681560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 168.edn_alert.639681560
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/169.edn_alert.129365787
Short name T215
Test name
Test status
Simulation time 55179736 ps
CPU time 1.14 seconds
Started Sep 09 11:44:34 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129365787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 169.edn_alert.129365787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/169.edn_genbits.3387582921
Short name T815
Test name
Test status
Simulation time 120731067 ps
CPU time 1.14 seconds
Started Sep 09 11:44:33 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387582921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3387582921
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_alert.1393743476
Short name T266
Test name
Test status
Simulation time 52001076 ps
CPU time 1.73 seconds
Started Sep 09 11:41:48 AM UTC 24
Finished Sep 09 11:41:51 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393743476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.1393743476
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_alert_test.387239321
Short name T386
Test name
Test status
Simulation time 94740581 ps
CPU time 1.37 seconds
Started Sep 09 11:41:49 AM UTC 24
Finished Sep 09 11:41:52 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387239321 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.387239321
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_disable.763004734
Short name T91
Test name
Test status
Simulation time 156829318 ps
CPU time 1.33 seconds
Started Sep 09 11:41:49 AM UTC 24
Finished Sep 09 11:41:52 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763004734 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.763004734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.3188740736
Short name T388
Test name
Test status
Simulation time 64813613 ps
CPU time 1.83 seconds
Started Sep 09 11:41:49 AM UTC 24
Finished Sep 09 11:41:52 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188740736 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.3188740736
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_err.3616193394
Short name T263
Test name
Test status
Simulation time 22798928 ps
CPU time 1.1 seconds
Started Sep 09 11:41:48 AM UTC 24
Finished Sep 09 11:41:50 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616193394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.3616193394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_genbits.2143454368
Short name T262
Test name
Test status
Simulation time 41159821 ps
CPU time 2.11 seconds
Started Sep 09 11:41:46 AM UTC 24
Finished Sep 09 11:41:49 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143454368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2143454368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_intr.2403165409
Short name T264
Test name
Test status
Simulation time 22726373 ps
CPU time 1.64 seconds
Started Sep 09 11:41:48 AM UTC 24
Finished Sep 09 11:41:51 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403165409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.2403165409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_smoke.84086163
Short name T385
Test name
Test status
Simulation time 34783302 ps
CPU time 1.43 seconds
Started Sep 09 11:41:46 AM UTC 24
Finished Sep 09 11:41:48 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84086163 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_smoke.84086163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_stress_all.611673575
Short name T265
Test name
Test status
Simulation time 450294742 ps
CPU time 2.93 seconds
Started Sep 09 11:41:47 AM UTC 24
Finished Sep 09 11:41:51 AM UTC 24
Peak memory 227416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611673575 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.611673575
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.2189197291
Short name T467
Test name
Test status
Simulation time 14892482933 ps
CPU time 63.73 seconds
Started Sep 09 11:41:47 AM UTC 24
Finished Sep 09 11:42:52 AM UTC 24
Peak memory 230076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2189197291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all
_with_rand_reset.2189197291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/170.edn_alert.3637376807
Short name T859
Test name
Test status
Simulation time 184658335 ps
CPU time 1.18 seconds
Started Sep 09 11:44:34 AM UTC 24
Finished Sep 09 11:44:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637376807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.3637376807
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/170.edn_genbits.2914085400
Short name T816
Test name
Test status
Simulation time 39484399 ps
CPU time 1 seconds
Started Sep 09 11:44:34 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914085400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2914085400
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/171.edn_alert.831955203
Short name T898
Test name
Test status
Simulation time 58401366 ps
CPU time 1.23 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831955203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 171.edn_alert.831955203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/171.edn_genbits.343584310
Short name T905
Test name
Test status
Simulation time 91628106 ps
CPU time 1.49 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343584310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 171.edn_genbits.343584310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/172.edn_alert.3718538675
Short name T824
Test name
Test status
Simulation time 30158697 ps
CPU time 1.31 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:44 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718538675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.3718538675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/172.edn_genbits.1009099841
Short name T845
Test name
Test status
Simulation time 79369017 ps
CPU time 1.69 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:51 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009099841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1009099841
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/173.edn_alert.666306964
Short name T822
Test name
Test status
Simulation time 72081634 ps
CPU time 1.09 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:44 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666306964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 173.edn_alert.666306964
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/173.edn_genbits.2246011683
Short name T825
Test name
Test status
Simulation time 55352330 ps
CPU time 1.38 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:44 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246011683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2246011683
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/174.edn_alert.1270294172
Short name T827
Test name
Test status
Simulation time 108415122 ps
CPU time 1.38 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:45 AM UTC 24
Peak memory 230320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270294172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.1270294172
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/174.edn_genbits.256615267
Short name T826
Test name
Test status
Simulation time 35497550 ps
CPU time 1.36 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:45 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256615267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 174.edn_genbits.256615267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/175.edn_alert.3671956822
Short name T823
Test name
Test status
Simulation time 77107483 ps
CPU time 1.01 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:44 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671956822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.3671956822
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/175.edn_genbits.3433087702
Short name T828
Test name
Test status
Simulation time 82254910 ps
CPU time 1.42 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:45 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433087702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3433087702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/176.edn_alert.59728963
Short name T817
Test name
Test status
Simulation time 39470813 ps
CPU time 1.05 seconds
Started Sep 09 11:44:36 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59728963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 176.edn_alert.59728963
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/176.edn_genbits.2761481520
Short name T832
Test name
Test status
Simulation time 73251140 ps
CPU time 2.34 seconds
Started Sep 09 11:44:35 AM UTC 24
Finished Sep 09 11:44:46 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761481520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2761481520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/177.edn_alert.714111753
Short name T819
Test name
Test status
Simulation time 26000183 ps
CPU time 1.28 seconds
Started Sep 09 11:44:36 AM UTC 24
Finished Sep 09 11:44:40 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714111753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 177.edn_alert.714111753
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/177.edn_genbits.1692733851
Short name T821
Test name
Test status
Simulation time 169974488 ps
CPU time 1.99 seconds
Started Sep 09 11:44:36 AM UTC 24
Finished Sep 09 11:44:40 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692733851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1692733851
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/178.edn_alert.1750700350
Short name T818
Test name
Test status
Simulation time 43835903 ps
CPU time 1.11 seconds
Started Sep 09 11:44:37 AM UTC 24
Finished Sep 09 11:44:39 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750700350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.1750700350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/178.edn_genbits.961670787
Short name T820
Test name
Test status
Simulation time 62550513 ps
CPU time 1.44 seconds
Started Sep 09 11:44:36 AM UTC 24
Finished Sep 09 11:44:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961670787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 178.edn_genbits.961670787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/179.edn_alert.1489003857
Short name T831
Test name
Test status
Simulation time 43700931 ps
CPU time 1.31 seconds
Started Sep 09 11:44:39 AM UTC 24
Finished Sep 09 11:44:45 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489003857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 179.edn_alert.1489003857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/179.edn_genbits.2997582467
Short name T833
Test name
Test status
Simulation time 160467157 ps
CPU time 2.15 seconds
Started Sep 09 11:44:39 AM UTC 24
Finished Sep 09 11:44:46 AM UTC 24
Peak memory 231500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997582467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2997582467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_alert.3951552805
Short name T182
Test name
Test status
Simulation time 48955289 ps
CPU time 1.34 seconds
Started Sep 09 11:41:51 AM UTC 24
Finished Sep 09 11:41:53 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951552805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.3951552805
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_alert_test.357943154
Short name T390
Test name
Test status
Simulation time 202566219 ps
CPU time 1.11 seconds
Started Sep 09 11:41:51 AM UTC 24
Finished Sep 09 11:41:53 AM UTC 24
Peak memory 216240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357943154 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.357943154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.1859832206
Short name T392
Test name
Test status
Simulation time 131261790 ps
CPU time 1.41 seconds
Started Sep 09 11:41:51 AM UTC 24
Finished Sep 09 11:41:54 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859832206 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.1859832206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_intr.1846004702
Short name T34
Test name
Test status
Simulation time 22397700 ps
CPU time 1.3 seconds
Started Sep 09 11:41:50 AM UTC 24
Finished Sep 09 11:41:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846004702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.1846004702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_smoke.4281456621
Short name T387
Test name
Test status
Simulation time 14706610 ps
CPU time 1.46 seconds
Started Sep 09 11:41:50 AM UTC 24
Finished Sep 09 11:41:52 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281456621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.4281456621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_stress_all.3951439910
Short name T391
Test name
Test status
Simulation time 342470159 ps
CPU time 2.74 seconds
Started Sep 09 11:41:50 AM UTC 24
Finished Sep 09 11:41:53 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951439910 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3951439910
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.2528051626
Short name T246
Test name
Test status
Simulation time 2412407556 ps
CPU time 31.1 seconds
Started Sep 09 11:41:50 AM UTC 24
Finished Sep 09 11:42:22 AM UTC 24
Peak memory 228028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2528051626 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all
_with_rand_reset.2528051626
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/180.edn_alert.673222122
Short name T829
Test name
Test status
Simulation time 96475195 ps
CPU time 1.11 seconds
Started Sep 09 11:44:39 AM UTC 24
Finished Sep 09 11:44:45 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673222122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 180.edn_alert.673222122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/180.edn_genbits.2754763393
Short name T830
Test name
Test status
Simulation time 53765689 ps
CPU time 1.25 seconds
Started Sep 09 11:44:39 AM UTC 24
Finished Sep 09 11:44:45 AM UTC 24
Peak memory 230404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754763393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2754763393
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/181.edn_alert.831951348
Short name T892
Test name
Test status
Simulation time 96484891 ps
CPU time 1.04 seconds
Started Sep 09 11:44:41 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831951348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 181.edn_alert.831951348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/181.edn_genbits.2009680402
Short name T853
Test name
Test status
Simulation time 37828335 ps
CPU time 1.41 seconds
Started Sep 09 11:44:40 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009680402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2009680402
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/182.edn_genbits.664571783
Short name T897
Test name
Test status
Simulation time 115261882 ps
CPU time 1.18 seconds
Started Sep 09 11:44:41 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664571783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.edn_genbits.664571783
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/183.edn_alert.1783697468
Short name T895
Test name
Test status
Simulation time 95834956 ps
CPU time 1.02 seconds
Started Sep 09 11:44:41 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783697468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.1783697468
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/183.edn_genbits.2763135734
Short name T896
Test name
Test status
Simulation time 286867888 ps
CPU time 1.07 seconds
Started Sep 09 11:44:41 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763135734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2763135734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/184.edn_alert.605232474
Short name T900
Test name
Test status
Simulation time 79608769 ps
CPU time 1.05 seconds
Started Sep 09 11:44:45 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605232474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 184.edn_alert.605232474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/184.edn_genbits.1941102459
Short name T863
Test name
Test status
Simulation time 81280002 ps
CPU time 1.46 seconds
Started Sep 09 11:44:45 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941102459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1941102459
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/185.edn_alert.3050371
Short name T844
Test name
Test status
Simulation time 74265220 ps
CPU time 1.08 seconds
Started Sep 09 11:44:45 AM UTC 24
Finished Sep 09 11:44:50 AM UTC 24
Peak memory 228416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al
ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 185.edn_alert.3050371
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/185.edn_genbits.3133856978
Short name T902
Test name
Test status
Simulation time 34117086 ps
CPU time 1.17 seconds
Started Sep 09 11:44:45 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133856978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3133856978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/186.edn_alert.2254018447
Short name T278
Test name
Test status
Simulation time 134811765 ps
CPU time 1.31 seconds
Started Sep 09 11:44:45 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254018447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.2254018447
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/186.edn_genbits.2179396460
Short name T843
Test name
Test status
Simulation time 44753934 ps
CPU time 1.09 seconds
Started Sep 09 11:44:45 AM UTC 24
Finished Sep 09 11:44:50 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179396460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2179396460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/187.edn_alert.3668560236
Short name T836
Test name
Test status
Simulation time 34987188 ps
CPU time 1.06 seconds
Started Sep 09 11:44:46 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668560236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.3668560236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/187.edn_genbits.343516524
Short name T837
Test name
Test status
Simulation time 57718940 ps
CPU time 1.05 seconds
Started Sep 09 11:44:46 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343516524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 187.edn_genbits.343516524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/188.edn_alert.4237692428
Short name T840
Test name
Test status
Simulation time 24364416 ps
CPU time 1.24 seconds
Started Sep 09 11:44:46 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237692428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.4237692428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/188.edn_genbits.897673848
Short name T838
Test name
Test status
Simulation time 78806521 ps
CPU time 1.04 seconds
Started Sep 09 11:44:46 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897673848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 188.edn_genbits.897673848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/189.edn_alert.3523503619
Short name T839
Test name
Test status
Simulation time 24135019 ps
CPU time 1.02 seconds
Started Sep 09 11:44:46 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523503619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.3523503619
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/189.edn_genbits.3091218731
Short name T841
Test name
Test status
Simulation time 53725430 ps
CPU time 1.19 seconds
Started Sep 09 11:44:46 AM UTC 24
Finished Sep 09 11:44:49 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091218731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3091218731
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_alert.1520089269
Short name T394
Test name
Test status
Simulation time 65721945 ps
CPU time 1.74 seconds
Started Sep 09 11:41:52 AM UTC 24
Finished Sep 09 11:41:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520089269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.1520089269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_alert_test.1661405708
Short name T396
Test name
Test status
Simulation time 13717764 ps
CPU time 1.24 seconds
Started Sep 09 11:41:54 AM UTC 24
Finished Sep 09 11:41:56 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661405708 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1661405708
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_disable.771155863
Short name T103
Test name
Test status
Simulation time 20595347 ps
CPU time 1.05 seconds
Started Sep 09 11:41:54 AM UTC 24
Finished Sep 09 11:41:56 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771155863 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.771155863
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.916351600
Short name T104
Test name
Test status
Simulation time 27148794 ps
CPU time 1.31 seconds
Started Sep 09 11:41:54 AM UTC 24
Finished Sep 09 11:41:56 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916351600 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.916351600
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_err.264012527
Short name T398
Test name
Test status
Simulation time 53936225 ps
CPU time 1.63 seconds
Started Sep 09 11:41:54 AM UTC 24
Finished Sep 09 11:41:56 AM UTC 24
Peak memory 230968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264012527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.edn_err.264012527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_genbits.2093503956
Short name T389
Test name
Test status
Simulation time 31652937 ps
CPU time 1.17 seconds
Started Sep 09 11:41:52 AM UTC 24
Finished Sep 09 11:41:54 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093503956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2093503956
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_intr.1604688609
Short name T101
Test name
Test status
Simulation time 69520817 ps
CPU time 0.85 seconds
Started Sep 09 11:41:52 AM UTC 24
Finished Sep 09 11:41:54 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604688609 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.1604688609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_smoke.967292021
Short name T393
Test name
Test status
Simulation time 19478663 ps
CPU time 1.52 seconds
Started Sep 09 11:41:51 AM UTC 24
Finished Sep 09 11:41:54 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967292021 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_smoke.967292021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_stress_all.610817878
Short name T395
Test name
Test status
Simulation time 45332475 ps
CPU time 1.96 seconds
Started Sep 09 11:41:52 AM UTC 24
Finished Sep 09 11:41:55 AM UTC 24
Peak memory 226668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610817878 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.610817878
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.3031297506
Short name T696
Test name
Test status
Simulation time 9766377809 ps
CPU time 138.84 seconds
Started Sep 09 11:41:52 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 233980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3031297506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all
_with_rand_reset.3031297506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/190.edn_alert.2616663980
Short name T849
Test name
Test status
Simulation time 160487776 ps
CPU time 1.14 seconds
Started Sep 09 11:44:49 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616663980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.2616663980
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/190.edn_genbits.2833949666
Short name T851
Test name
Test status
Simulation time 41092634 ps
CPU time 1.49 seconds
Started Sep 09 11:44:49 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833949666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2833949666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/191.edn_alert.543501141
Short name T858
Test name
Test status
Simulation time 23858170 ps
CPU time 1.2 seconds
Started Sep 09 11:44:50 AM UTC 24
Finished Sep 09 11:44:56 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543501141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 191.edn_alert.543501141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/191.edn_genbits.2904830288
Short name T848
Test name
Test status
Simulation time 66369935 ps
CPU time 1.66 seconds
Started Sep 09 11:44:50 AM UTC 24
Finished Sep 09 11:44:54 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904830288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2904830288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/192.edn_alert.2167439534
Short name T847
Test name
Test status
Simulation time 26192835 ps
CPU time 1.16 seconds
Started Sep 09 11:44:51 AM UTC 24
Finished Sep 09 11:44:54 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167439534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.2167439534
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/193.edn_alert.2595906433
Short name T865
Test name
Test status
Simulation time 24376194 ps
CPU time 1.16 seconds
Started Sep 09 11:44:51 AM UTC 24
Finished Sep 09 11:44:59 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595906433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.2595906433
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/193.edn_genbits.3601332168
Short name T866
Test name
Test status
Simulation time 43809904 ps
CPU time 1.3 seconds
Started Sep 09 11:44:51 AM UTC 24
Finished Sep 09 11:44:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601332168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3601332168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/194.edn_alert.2651089612
Short name T846
Test name
Test status
Simulation time 59476914 ps
CPU time 0.95 seconds
Started Sep 09 11:44:52 AM UTC 24
Finished Sep 09 11:44:54 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651089612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.2651089612
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/194.edn_genbits.2221619800
Short name T862
Test name
Test status
Simulation time 77587505 ps
CPU time 1.07 seconds
Started Sep 09 11:44:51 AM UTC 24
Finished Sep 09 11:44:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221619800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2221619800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/195.edn_alert.295705134
Short name T850
Test name
Test status
Simulation time 24952220 ps
CPU time 1.07 seconds
Started Sep 09 11:44:52 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295705134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 195.edn_alert.295705134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/195.edn_genbits.498684329
Short name T852
Test name
Test status
Simulation time 37550070 ps
CPU time 1.27 seconds
Started Sep 09 11:44:52 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498684329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 195.edn_genbits.498684329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/196.edn_alert.3844113951
Short name T874
Test name
Test status
Simulation time 273234852 ps
CPU time 1.48 seconds
Started Sep 09 11:44:54 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844113951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 196.edn_alert.3844113951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/196.edn_genbits.1195905345
Short name T855
Test name
Test status
Simulation time 51710896 ps
CPU time 1.38 seconds
Started Sep 09 11:44:53 AM UTC 24
Finished Sep 09 11:44:55 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195905345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1195905345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/197.edn_alert.2433721609
Short name T881
Test name
Test status
Simulation time 273411833 ps
CPU time 0.99 seconds
Started Sep 09 11:44:55 AM UTC 24
Finished Sep 09 11:45:04 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433721609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 197.edn_alert.2433721609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/197.edn_genbits.1854381326
Short name T869
Test name
Test status
Simulation time 64202136 ps
CPU time 1.3 seconds
Started Sep 09 11:44:54 AM UTC 24
Finished Sep 09 11:44:59 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854381326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1854381326
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/198.edn_alert.1617957541
Short name T882
Test name
Test status
Simulation time 94458512 ps
CPU time 1.01 seconds
Started Sep 09 11:44:55 AM UTC 24
Finished Sep 09 11:45:04 AM UTC 24
Peak memory 228400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617957541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.1617957541
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/198.edn_genbits.3882446673
Short name T886
Test name
Test status
Simulation time 57136320 ps
CPU time 1.68 seconds
Started Sep 09 11:44:55 AM UTC 24
Finished Sep 09 11:45:05 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882446673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3882446673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/199.edn_alert.3079722717
Short name T868
Test name
Test status
Simulation time 26083931 ps
CPU time 1.09 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:44:59 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079722717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.3079722717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/199.edn_genbits.1869742972
Short name T867
Test name
Test status
Simulation time 203481719 ps
CPU time 1.13 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:44:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869742972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1869742972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_alert_test.1293113894
Short name T69
Test name
Test status
Simulation time 36406338 ps
CPU time 1.29 seconds
Started Sep 09 11:40:53 AM UTC 24
Finished Sep 09 11:40:56 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293113894 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1293113894
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.1642225092
Short name T38
Test name
Test status
Simulation time 293283819 ps
CPU time 1.73 seconds
Started Sep 09 11:40:53 AM UTC 24
Finished Sep 09 11:40:56 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642225092 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.1642225092
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_err.3004683695
Short name T7
Test name
Test status
Simulation time 101070038 ps
CPU time 1.61 seconds
Started Sep 09 11:40:52 AM UTC 24
Finished Sep 09 11:40:55 AM UTC 24
Peak memory 246624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004683695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.3004683695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_genbits.973551318
Short name T20
Test name
Test status
Simulation time 89058317 ps
CPU time 1.69 seconds
Started Sep 09 11:40:51 AM UTC 24
Finished Sep 09 11:40:54 AM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973551318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_genbits.973551318
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_intr.2766919579
Short name T40
Test name
Test status
Simulation time 21141234 ps
CPU time 1.64 seconds
Started Sep 09 11:40:51 AM UTC 24
Finished Sep 09 11:40:54 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766919579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.2766919579
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_regwen.636213977
Short name T68
Test name
Test status
Simulation time 15694929 ps
CPU time 1.45 seconds
Started Sep 09 11:40:51 AM UTC 24
Finished Sep 09 11:40:53 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636213977 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_regwen.636213977
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_sec_cm.979052800
Short name T17
Test name
Test status
Simulation time 538045832 ps
CPU time 5.25 seconds
Started Sep 09 11:40:53 AM UTC 24
Finished Sep 09 11:41:00 AM UTC 24
Peak memory 260336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979052800 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.979052800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_smoke.3776757617
Short name T66
Test name
Test status
Simulation time 17530761 ps
CPU time 1.21 seconds
Started Sep 09 11:40:49 AM UTC 24
Finished Sep 09 11:40:52 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776757617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.3776757617
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_stress_all.1087107978
Short name T41
Test name
Test status
Simulation time 95782971 ps
CPU time 3.5 seconds
Started Sep 09 11:40:51 AM UTC 24
Finished Sep 09 11:40:56 AM UTC 24
Peak memory 227660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087107978 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1087107978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.405528247
Short name T37
Test name
Test status
Simulation time 15840326660 ps
CPU time 56.76 seconds
Started Sep 09 11:40:51 AM UTC 24
Finished Sep 09 11:41:50 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=405528247 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_w
ith_rand_reset.405528247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_alert.704674807
Short name T105
Test name
Test status
Simulation time 22403353 ps
CPU time 1.29 seconds
Started Sep 09 11:41:55 AM UTC 24
Finished Sep 09 11:41:57 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704674807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_alert.704674807
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_alert_test.3792052064
Short name T402
Test name
Test status
Simulation time 18899029 ps
CPU time 1.29 seconds
Started Sep 09 11:41:56 AM UTC 24
Finished Sep 09 11:41:58 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792052064 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3792052064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_disable.2805865167
Short name T85
Test name
Test status
Simulation time 19656907 ps
CPU time 1.16 seconds
Started Sep 09 11:41:55 AM UTC 24
Finished Sep 09 11:41:57 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805865167 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2805865167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.387739760
Short name T162
Test name
Test status
Simulation time 46527579 ps
CPU time 1.85 seconds
Started Sep 09 11:41:56 AM UTC 24
Finished Sep 09 11:41:59 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387739760 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.387739760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_err.2427572272
Short name T180
Test name
Test status
Simulation time 32609735 ps
CPU time 1.98 seconds
Started Sep 09 11:41:55 AM UTC 24
Finished Sep 09 11:41:58 AM UTC 24
Peak memory 242324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427572272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.2427572272
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_genbits.1426367454
Short name T400
Test name
Test status
Simulation time 72592664 ps
CPU time 1.65 seconds
Started Sep 09 11:41:55 AM UTC 24
Finished Sep 09 11:41:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426367454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1426367454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_intr.1202400968
Short name T399
Test name
Test status
Simulation time 42659444 ps
CPU time 1.27 seconds
Started Sep 09 11:41:55 AM UTC 24
Finished Sep 09 11:41:57 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202400968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.1202400968
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_smoke.395396996
Short name T397
Test name
Test status
Simulation time 34887592 ps
CPU time 1.26 seconds
Started Sep 09 11:41:54 AM UTC 24
Finished Sep 09 11:41:56 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395396996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_smoke.395396996
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/20.edn_stress_all.159875230
Short name T405
Test name
Test status
Simulation time 482762066 ps
CPU time 4.73 seconds
Started Sep 09 11:41:55 AM UTC 24
Finished Sep 09 11:42:01 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159875230 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.159875230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/200.edn_genbits.1675530711
Short name T877
Test name
Test status
Simulation time 72722911 ps
CPU time 1.47 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675530711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1675530711
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/201.edn_genbits.3975153041
Short name T870
Test name
Test status
Simulation time 95155860 ps
CPU time 1.11 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975153041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3975153041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/202.edn_genbits.3455372477
Short name T876
Test name
Test status
Simulation time 63451438 ps
CPU time 1.35 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455372477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3455372477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/203.edn_genbits.706144395
Short name T875
Test name
Test status
Simulation time 67078192 ps
CPU time 1.29 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706144395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 203.edn_genbits.706144395
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/204.edn_genbits.676244158
Short name T872
Test name
Test status
Simulation time 111409380 ps
CPU time 1.05 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676244158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 204.edn_genbits.676244158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/205.edn_genbits.3642255504
Short name T873
Test name
Test status
Simulation time 90646126 ps
CPU time 1.05 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642255504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3642255504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/206.edn_genbits.3576780679
Short name T894
Test name
Test status
Simulation time 58869704 ps
CPU time 1.17 seconds
Started Sep 09 11:44:56 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576780679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3576780679
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/207.edn_genbits.1323579505
Short name T878
Test name
Test status
Simulation time 43475713 ps
CPU time 1.87 seconds
Started Sep 09 11:44:58 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323579505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1323579505
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/208.edn_genbits.937486906
Short name T864
Test name
Test status
Simulation time 70761882 ps
CPU time 1.03 seconds
Started Sep 09 11:44:59 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 226156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937486906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 208.edn_genbits.937486906
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/209.edn_genbits.1445414613
Short name T914
Test name
Test status
Simulation time 71951060 ps
CPU time 2.29 seconds
Started Sep 09 11:44:59 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 231436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445414613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1445414613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_alert.920022123
Short name T186
Test name
Test status
Simulation time 26234489 ps
CPU time 1.83 seconds
Started Sep 09 11:41:58 AM UTC 24
Finished Sep 09 11:42:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920022123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_alert.920022123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_alert_test.919114967
Short name T407
Test name
Test status
Simulation time 59475957 ps
CPU time 0.92 seconds
Started Sep 09 11:41:59 AM UTC 24
Finished Sep 09 11:42:01 AM UTC 24
Peak memory 226528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919114967 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.919114967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_disable.3352286201
Short name T404
Test name
Test status
Simulation time 13167990 ps
CPU time 1.39 seconds
Started Sep 09 11:41:58 AM UTC 24
Finished Sep 09 11:42:00 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352286201 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3352286201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_err.2570336024
Short name T198
Test name
Test status
Simulation time 22406675 ps
CPU time 1.23 seconds
Started Sep 09 11:41:58 AM UTC 24
Finished Sep 09 11:42:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570336024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.2570336024
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_genbits.2388824411
Short name T344
Test name
Test status
Simulation time 50607909 ps
CPU time 2.15 seconds
Started Sep 09 11:41:58 AM UTC 24
Finished Sep 09 11:42:01 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388824411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2388824411
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_intr.2583547564
Short name T403
Test name
Test status
Simulation time 25329125 ps
CPU time 1.26 seconds
Started Sep 09 11:41:58 AM UTC 24
Finished Sep 09 11:42:00 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583547564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.2583547564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_smoke.3131428760
Short name T401
Test name
Test status
Simulation time 67092585 ps
CPU time 1.2 seconds
Started Sep 09 11:41:56 AM UTC 24
Finished Sep 09 11:41:58 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131428760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.3131428760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/21.edn_stress_all.3063908007
Short name T310
Test name
Test status
Simulation time 489312349 ps
CPU time 5.39 seconds
Started Sep 09 11:41:58 AM UTC 24
Finished Sep 09 11:42:04 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063908007 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3063908007
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/210.edn_genbits.2530202673
Short name T915
Test name
Test status
Simulation time 67791092 ps
CPU time 1.17 seconds
Started Sep 09 11:45:00 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 228132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530202673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2530202673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/211.edn_genbits.466831535
Short name T918
Test name
Test status
Simulation time 34331448 ps
CPU time 1.41 seconds
Started Sep 09 11:45:00 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 228140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466831535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 211.edn_genbits.466831535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/212.edn_genbits.3902887799
Short name T916
Test name
Test status
Simulation time 158908433 ps
CPU time 1.27 seconds
Started Sep 09 11:45:00 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902887799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3902887799
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/213.edn_genbits.1310398252
Short name T888
Test name
Test status
Simulation time 39749734 ps
CPU time 1.25 seconds
Started Sep 09 11:45:00 AM UTC 24
Finished Sep 09 11:45:05 AM UTC 24
Peak memory 228532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310398252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1310398252
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/214.edn_genbits.1602251233
Short name T885
Test name
Test status
Simulation time 46948102 ps
CPU time 1.02 seconds
Started Sep 09 11:45:00 AM UTC 24
Finished Sep 09 11:45:05 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602251233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1602251233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/215.edn_genbits.1515376882
Short name T901
Test name
Test status
Simulation time 71103626 ps
CPU time 1.14 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515376882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1515376882
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/216.edn_genbits.627347846
Short name T913
Test name
Test status
Simulation time 89669822 ps
CPU time 2.81 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627347846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.edn_genbits.627347846
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/217.edn_genbits.3442352102
Short name T903
Test name
Test status
Simulation time 80600117 ps
CPU time 1.1 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442352102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3442352102
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/218.edn_genbits.2385471532
Short name T880
Test name
Test status
Simulation time 23794683 ps
CPU time 1.03 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:04 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385471532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2385471532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/219.edn_genbits.734112642
Short name T879
Test name
Test status
Simulation time 85392822 ps
CPU time 0.93 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734112642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 219.edn_genbits.734112642
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_alert.1292224117
Short name T97
Test name
Test status
Simulation time 24958790 ps
CPU time 1.5 seconds
Started Sep 09 11:42:03 AM UTC 24
Finished Sep 09 11:42:05 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292224117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.1292224117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_alert_test.756479855
Short name T410
Test name
Test status
Simulation time 92014620 ps
CPU time 1.15 seconds
Started Sep 09 11:42:03 AM UTC 24
Finished Sep 09 11:42:05 AM UTC 24
Peak memory 226528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756479855 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.756479855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_disable.1193372343
Short name T411
Test name
Test status
Simulation time 33761081 ps
CPU time 1.26 seconds
Started Sep 09 11:42:03 AM UTC 24
Finished Sep 09 11:42:05 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193372343 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1193372343
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.3848594140
Short name T163
Test name
Test status
Simulation time 96650339 ps
CPU time 1.6 seconds
Started Sep 09 11:42:03 AM UTC 24
Finished Sep 09 11:42:06 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848594140 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.3848594140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_err.1318701208
Short name T181
Test name
Test status
Simulation time 33579010 ps
CPU time 1.7 seconds
Started Sep 09 11:42:03 AM UTC 24
Finished Sep 09 11:42:06 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318701208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.edn_err.1318701208
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_genbits.3496932769
Short name T92
Test name
Test status
Simulation time 58584504 ps
CPU time 2.27 seconds
Started Sep 09 11:41:59 AM UTC 24
Finished Sep 09 11:42:02 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496932769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3496932769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_intr.787824098
Short name T409
Test name
Test status
Simulation time 53366371 ps
CPU time 1.47 seconds
Started Sep 09 11:42:02 AM UTC 24
Finished Sep 09 11:42:04 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787824098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.787824098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_smoke.3745414090
Short name T408
Test name
Test status
Simulation time 200850274 ps
CPU time 1.42 seconds
Started Sep 09 11:41:59 AM UTC 24
Finished Sep 09 11:42:01 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745414090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_smoke.3745414090
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_stress_all.3926406238
Short name T413
Test name
Test status
Simulation time 723984316 ps
CPU time 6.14 seconds
Started Sep 09 11:41:59 AM UTC 24
Finished Sep 09 11:42:06 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926406238 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3926406238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.1347662421
Short name T249
Test name
Test status
Simulation time 6361719185 ps
CPU time 43.94 seconds
Started Sep 09 11:42:00 AM UTC 24
Finished Sep 09 11:42:45 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1347662421 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all
_with_rand_reset.1347662421
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/220.edn_genbits.22789293
Short name T883
Test name
Test status
Simulation time 43963146 ps
CPU time 1.08 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:04 AM UTC 24
Peak memory 230392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22789293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 220.edn_genbits.22789293
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/221.edn_genbits.2413021314
Short name T889
Test name
Test status
Simulation time 81894144 ps
CPU time 2.36 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:06 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413021314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2413021314
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/222.edn_genbits.493238673
Short name T887
Test name
Test status
Simulation time 105212279 ps
CPU time 1.81 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:05 AM UTC 24
Peak memory 230552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493238673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 222.edn_genbits.493238673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/223.edn_genbits.2068358596
Short name T884
Test name
Test status
Simulation time 64175940 ps
CPU time 1.14 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:04 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068358596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2068358596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/224.edn_genbits.120945848
Short name T342
Test name
Test status
Simulation time 56141253 ps
CPU time 1.59 seconds
Started Sep 09 11:45:01 AM UTC 24
Finished Sep 09 11:45:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120945848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 224.edn_genbits.120945848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/225.edn_genbits.1817827200
Short name T891
Test name
Test status
Simulation time 70166599 ps
CPU time 0.93 seconds
Started Sep 09 11:45:04 AM UTC 24
Finished Sep 09 11:45:09 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817827200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1817827200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/226.edn_genbits.4271207734
Short name T355
Test name
Test status
Simulation time 99753502 ps
CPU time 1.33 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271207734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.4271207734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/227.edn_genbits.3397427074
Short name T893
Test name
Test status
Simulation time 38318516 ps
CPU time 1.03 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397427074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3397427074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/228.edn_genbits.2549199459
Short name T917
Test name
Test status
Simulation time 65822468 ps
CPU time 2.66 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 229420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549199459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2549199459
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/229.edn_genbits.1171248459
Short name T904
Test name
Test status
Simulation time 81005112 ps
CPU time 1.27 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171248459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1171248459
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_alert.4287126372
Short name T106
Test name
Test status
Simulation time 23749981 ps
CPU time 1.74 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 230444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287126372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.4287126372
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_alert_test.3276756719
Short name T416
Test name
Test status
Simulation time 36781780 ps
CPU time 1.23 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276756719 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3276756719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_disable.1085058946
Short name T415
Test name
Test status
Simulation time 22831960 ps
CPU time 1.33 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 226288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085058946 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1085058946
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_err.1912717410
Short name T199
Test name
Test status
Simulation time 29454309 ps
CPU time 1.54 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912717410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.edn_err.1912717410
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_genbits.3789599216
Short name T356
Test name
Test status
Simulation time 33161802 ps
CPU time 1.73 seconds
Started Sep 09 11:42:04 AM UTC 24
Finished Sep 09 11:42:07 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789599216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3789599216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_intr.3888447168
Short name T417
Test name
Test status
Simulation time 20756313 ps
CPU time 1.55 seconds
Started Sep 09 11:42:06 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 226280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888447168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.3888447168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_smoke.3804620806
Short name T412
Test name
Test status
Simulation time 127861384 ps
CPU time 1.24 seconds
Started Sep 09 11:42:03 AM UTC 24
Finished Sep 09 11:42:05 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804620806 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.3804620806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/23.edn_stress_all.1830540649
Short name T414
Test name
Test status
Simulation time 525983098 ps
CPU time 3.23 seconds
Started Sep 09 11:42:04 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830540649 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1830540649
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/230.edn_genbits.4282576904
Short name T910
Test name
Test status
Simulation time 38728760 ps
CPU time 1.79 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282576904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4282576904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/231.edn_genbits.1296874615
Short name T907
Test name
Test status
Simulation time 128188913 ps
CPU time 1.33 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296874615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1296874615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/232.edn_genbits.3847424445
Short name T906
Test name
Test status
Simulation time 72377089 ps
CPU time 1.25 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847424445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3847424445
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/233.edn_genbits.4040895721
Short name T909
Test name
Test status
Simulation time 41202390 ps
CPU time 1.59 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040895721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.4040895721
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/234.edn_genbits.2940469669
Short name T919
Test name
Test status
Simulation time 401900383 ps
CPU time 2.73 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:13 AM UTC 24
Peak memory 231500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940469669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2940469669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/235.edn_genbits.3129935823
Short name T911
Test name
Test status
Simulation time 51591983 ps
CPU time 1.55 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129935823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3129935823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/236.edn_genbits.811016857
Short name T908
Test name
Test status
Simulation time 36370681 ps
CPU time 1.3 seconds
Started Sep 09 11:45:06 AM UTC 24
Finished Sep 09 11:45:11 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811016857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 236.edn_genbits.811016857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/237.edn_genbits.1086330962
Short name T899
Test name
Test status
Simulation time 106323218 ps
CPU time 1.13 seconds
Started Sep 09 11:45:07 AM UTC 24
Finished Sep 09 11:45:10 AM UTC 24
Peak memory 228288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086330962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1086330962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/238.edn_genbits.1518455027
Short name T912
Test name
Test status
Simulation time 97035482 ps
CPU time 1.73 seconds
Started Sep 09 11:45:09 AM UTC 24
Finished Sep 09 11:45:12 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518455027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1518455027
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/239.edn_genbits.3176170703
Short name T920
Test name
Test status
Simulation time 261778591 ps
CPU time 3.21 seconds
Started Sep 09 11:45:10 AM UTC 24
Finished Sep 09 11:45:14 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176170703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3176170703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_alert.291073689
Short name T201
Test name
Test status
Simulation time 40148420 ps
CPU time 1.62 seconds
Started Sep 09 11:42:09 AM UTC 24
Finished Sep 09 11:42:12 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291073689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.edn_alert.291073689
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_alert_test.1100173173
Short name T422
Test name
Test status
Simulation time 14229283 ps
CPU time 1.38 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:14 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100173173 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1100173173
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_disable.486883725
Short name T421
Test name
Test status
Simulation time 14202578 ps
CPU time 1.32 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:14 AM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486883725 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.486883725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2350460907
Short name T175
Test name
Test status
Simulation time 26594859 ps
CPU time 1.23 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350460907 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.2350460907
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_err.2592301295
Short name T425
Test name
Test status
Simulation time 29178375 ps
CPU time 1.89 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:14 AM UTC 24
Peak memory 230112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592301295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.2592301295
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_genbits.1992818430
Short name T98
Test name
Test status
Simulation time 45594138 ps
CPU time 1.8 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:10 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992818430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1992818430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_intr.4124847892
Short name T419
Test name
Test status
Simulation time 92680585 ps
CPU time 1.03 seconds
Started Sep 09 11:42:09 AM UTC 24
Finished Sep 09 11:42:11 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124847892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.4124847892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_smoke.89491137
Short name T418
Test name
Test status
Simulation time 65087325 ps
CPU time 1.34 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:09 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89491137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_smoke.89491137
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_stress_all.2739116074
Short name T420
Test name
Test status
Simulation time 1072770351 ps
CPU time 4.32 seconds
Started Sep 09 11:42:07 AM UTC 24
Finished Sep 09 11:42:12 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739116074 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2739116074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.851271004
Short name T255
Test name
Test status
Simulation time 8695610395 ps
CPU time 63.71 seconds
Started Sep 09 11:42:09 AM UTC 24
Finished Sep 09 11:43:14 AM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=851271004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_
with_rand_reset.851271004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/240.edn_genbits.1129999391
Short name T922
Test name
Test status
Simulation time 192255255 ps
CPU time 1.32 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:14 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129999391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1129999391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/241.edn_genbits.2964803756
Short name T923
Test name
Test status
Simulation time 139932600 ps
CPU time 1.21 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:14 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964803756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2964803756
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/242.edn_genbits.265368995
Short name T921
Test name
Test status
Simulation time 41018034 ps
CPU time 1.24 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:14 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265368995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 242.edn_genbits.265368995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/243.edn_genbits.1281324615
Short name T927
Test name
Test status
Simulation time 322505927 ps
CPU time 1.38 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281324615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1281324615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/244.edn_genbits.4046123820
Short name T925
Test name
Test status
Simulation time 61164585 ps
CPU time 1.24 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046123820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4046123820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/245.edn_genbits.3195217499
Short name T924
Test name
Test status
Simulation time 35831146 ps
CPU time 1.12 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195217499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3195217499
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/246.edn_genbits.405118541
Short name T928
Test name
Test status
Simulation time 104104353 ps
CPU time 1.4 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405118541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 246.edn_genbits.405118541
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/247.edn_genbits.3824926887
Short name T926
Test name
Test status
Simulation time 55835150 ps
CPU time 1.11 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824926887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3824926887
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/248.edn_genbits.1051320089
Short name T930
Test name
Test status
Simulation time 43550586 ps
CPU time 1.54 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051320089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1051320089
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/249.edn_genbits.1168286578
Short name T929
Test name
Test status
Simulation time 32106548 ps
CPU time 1.35 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168286578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1168286578
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_alert.3626032817
Short name T202
Test name
Test status
Simulation time 68116020 ps
CPU time 1.46 seconds
Started Sep 09 11:42:14 AM UTC 24
Finished Sep 09 11:42:16 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626032817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.3626032817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_alert_test.1736353197
Short name T428
Test name
Test status
Simulation time 61016274 ps
CPU time 1.31 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:42:18 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736353197 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1736353197
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_disable.3167899119
Short name T427
Test name
Test status
Simulation time 13813350 ps
CPU time 1.34 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:42:18 AM UTC 24
Peak memory 226216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167899119 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3167899119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.2777917729
Short name T176
Test name
Test status
Simulation time 29842653 ps
CPU time 1.71 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:42:19 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777917729 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2777917729
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_err.2765686396
Short name T167
Test name
Test status
Simulation time 52963933 ps
CPU time 1.67 seconds
Started Sep 09 11:42:14 AM UTC 24
Finished Sep 09 11:42:16 AM UTC 24
Peak memory 244336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765686396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.2765686396
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_genbits.397540826
Short name T424
Test name
Test status
Simulation time 44360860 ps
CPU time 1.62 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:14 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397540826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_genbits.397540826
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_intr.1950592800
Short name T112
Test name
Test status
Simulation time 24701822 ps
CPU time 1.48 seconds
Started Sep 09 11:42:14 AM UTC 24
Finished Sep 09 11:42:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950592800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.1950592800
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_smoke.1089273022
Short name T423
Test name
Test status
Simulation time 17934071 ps
CPU time 1.48 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089273022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.1089273022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_stress_all.3133199429
Short name T426
Test name
Test status
Simulation time 252338665 ps
CPU time 2.76 seconds
Started Sep 09 11:42:11 AM UTC 24
Finished Sep 09 11:42:15 AM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133199429 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3133199429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.1027624590
Short name T254
Test name
Test status
Simulation time 3624237434 ps
CPU time 53.69 seconds
Started Sep 09 11:42:12 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 233824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1027624590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.1027624590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/250.edn_genbits.4129476111
Short name T931
Test name
Test status
Simulation time 50561783 ps
CPU time 1.53 seconds
Started Sep 09 11:45:11 AM UTC 24
Finished Sep 09 11:45:15 AM UTC 24
Peak memory 228548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129476111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.4129476111
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/251.edn_genbits.3021429977
Short name T957
Test name
Test status
Simulation time 83551949 ps
CPU time 1.44 seconds
Started Sep 09 11:45:12 AM UTC 24
Finished Sep 09 11:45:26 AM UTC 24
Peak memory 227908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021429977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3021429977
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/252.edn_genbits.427481406
Short name T932
Test name
Test status
Simulation time 68829749 ps
CPU time 1.75 seconds
Started Sep 09 11:45:12 AM UTC 24
Finished Sep 09 11:45:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427481406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 252.edn_genbits.427481406
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/253.edn_genbits.3138096610
Short name T953
Test name
Test status
Simulation time 72760621 ps
CPU time 1.05 seconds
Started Sep 09 11:45:12 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 230024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138096610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3138096610
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/254.edn_genbits.4158906049
Short name T955
Test name
Test status
Simulation time 85908637 ps
CPU time 1.24 seconds
Started Sep 09 11:45:12 AM UTC 24
Finished Sep 09 11:45:26 AM UTC 24
Peak memory 228336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158906049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4158906049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/255.edn_genbits.4006880873
Short name T954
Test name
Test status
Simulation time 70319419 ps
CPU time 1.12 seconds
Started Sep 09 11:45:12 AM UTC 24
Finished Sep 09 11:45:26 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006880873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4006880873
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/256.edn_genbits.1907745984
Short name T958
Test name
Test status
Simulation time 48698087 ps
CPU time 1.53 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:26 AM UTC 24
Peak memory 228244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907745984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1907745984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/257.edn_genbits.3169566570
Short name T959
Test name
Test status
Simulation time 102744283 ps
CPU time 2.33 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:27 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169566570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3169566570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/258.edn_genbits.2147836420
Short name T975
Test name
Test status
Simulation time 97788671 ps
CPU time 1.52 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147836420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2147836420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/259.edn_genbits.3440781448
Short name T956
Test name
Test status
Simulation time 84002750 ps
CPU time 1.21 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:26 AM UTC 24
Peak memory 230236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440781448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3440781448
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_alert_test.3223293004
Short name T433
Test name
Test status
Simulation time 12007122 ps
CPU time 1.28 seconds
Started Sep 09 11:42:21 AM UTC 24
Finished Sep 09 11:42:23 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223293004 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3223293004
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_disable.1346365696
Short name T239
Test name
Test status
Simulation time 12338014 ps
CPU time 1.39 seconds
Started Sep 09 11:42:20 AM UTC 24
Finished Sep 09 11:42:23 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346365696 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1346365696
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.2308610252
Short name T434
Test name
Test status
Simulation time 136945700 ps
CPU time 1.75 seconds
Started Sep 09 11:42:21 AM UTC 24
Finished Sep 09 11:42:23 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308610252 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.2308610252
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_err.2075824614
Short name T431
Test name
Test status
Simulation time 31598550 ps
CPU time 1.26 seconds
Started Sep 09 11:42:18 AM UTC 24
Finished Sep 09 11:42:21 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075824614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.2075824614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_genbits.4046904550
Short name T107
Test name
Test status
Simulation time 60829968 ps
CPU time 1.82 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:42:19 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046904550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4046904550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_smoke.3069210566
Short name T429
Test name
Test status
Simulation time 43169878 ps
CPU time 1.36 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:42:18 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069210566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.3069210566
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_stress_all.2609387420
Short name T430
Test name
Test status
Simulation time 96312348 ps
CPU time 3.52 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:42:21 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609387420 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2609387420
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.586160072
Short name T796
Test name
Test status
Simulation time 20136567413 ps
CPU time 133.72 seconds
Started Sep 09 11:42:16 AM UTC 24
Finished Sep 09 11:44:32 AM UTC 24
Peak memory 230072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=586160072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_
with_rand_reset.586160072
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/260.edn_genbits.3999996309
Short name T973
Test name
Test status
Simulation time 28644761 ps
CPU time 1.38 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999996309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3999996309
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/261.edn_genbits.2512280604
Short name T977
Test name
Test status
Simulation time 101420786 ps
CPU time 1.7 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512280604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2512280604
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/262.edn_genbits.1788552268
Short name T972
Test name
Test status
Simulation time 90335372 ps
CPU time 1.34 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788552268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1788552268
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/263.edn_genbits.2921712478
Short name T974
Test name
Test status
Simulation time 47150151 ps
CPU time 1.31 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921712478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2921712478
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/264.edn_genbits.454669961
Short name T346
Test name
Test status
Simulation time 104367065 ps
CPU time 1.85 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454669961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 264.edn_genbits.454669961
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/265.edn_genbits.754511634
Short name T978
Test name
Test status
Simulation time 22162956 ps
CPU time 1.5 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754511634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 265.edn_genbits.754511634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/266.edn_genbits.1570425552
Short name T976
Test name
Test status
Simulation time 59305206 ps
CPU time 1.49 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570425552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1570425552
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/267.edn_genbits.1865296865
Short name T960
Test name
Test status
Simulation time 18966740 ps
CPU time 0.95 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865296865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1865296865
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/268.edn_genbits.1649565361
Short name T963
Test name
Test status
Simulation time 85623870 ps
CPU time 1.31 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:29 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649565361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1649565361
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/269.edn_genbits.1147713342
Short name T965
Test name
Test status
Simulation time 134877023 ps
CPU time 2.67 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:31 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147713342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1147713342
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_alert.362125327
Short name T436
Test name
Test status
Simulation time 76261652 ps
CPU time 1.69 seconds
Started Sep 09 11:42:23 AM UTC 24
Finished Sep 09 11:42:26 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362125327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.edn_alert.362125327
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_alert_test.3843946414
Short name T438
Test name
Test status
Simulation time 65303350 ps
CPU time 1.26 seconds
Started Sep 09 11:42:25 AM UTC 24
Finished Sep 09 11:42:28 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843946414 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3843946414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_disable.2413444438
Short name T99
Test name
Test status
Simulation time 18869189 ps
CPU time 1.27 seconds
Started Sep 09 11:42:23 AM UTC 24
Finished Sep 09 11:42:26 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413444438 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2413444438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_err.3603573511
Short name T193
Test name
Test status
Simulation time 29488204 ps
CPU time 1.95 seconds
Started Sep 09 11:42:23 AM UTC 24
Finished Sep 09 11:42:26 AM UTC 24
Peak memory 241964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603573511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.3603573511
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_genbits.1478549308
Short name T437
Test name
Test status
Simulation time 182413929 ps
CPU time 5.25 seconds
Started Sep 09 11:42:21 AM UTC 24
Finished Sep 09 11:42:27 AM UTC 24
Peak memory 231464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478549308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1478549308
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_intr.287985539
Short name T435
Test name
Test status
Simulation time 29902475 ps
CPU time 1.34 seconds
Started Sep 09 11:42:23 AM UTC 24
Finished Sep 09 11:42:26 AM UTC 24
Peak memory 228228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287985539 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.287985539
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_smoke.3576306312
Short name T432
Test name
Test status
Simulation time 29826198 ps
CPU time 1.14 seconds
Started Sep 09 11:42:21 AM UTC 24
Finished Sep 09 11:42:23 AM UTC 24
Peak memory 215712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576306312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.3576306312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/27.edn_stress_all.3503478103
Short name T324
Test name
Test status
Simulation time 3246046091 ps
CPU time 7.29 seconds
Started Sep 09 11:42:21 AM UTC 24
Finished Sep 09 11:42:29 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503478103 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3503478103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/270.edn_genbits.1502633244
Short name T961
Test name
Test status
Simulation time 23417218 ps
CPU time 1.17 seconds
Started Sep 09 11:45:13 AM UTC 24
Finished Sep 09 11:45:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502633244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1502633244
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/271.edn_genbits.2785303476
Short name T933
Test name
Test status
Simulation time 55783790 ps
CPU time 1.24 seconds
Started Sep 09 11:45:14 AM UTC 24
Finished Sep 09 11:45:20 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785303476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2785303476
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/272.edn_genbits.1226386414
Short name T941
Test name
Test status
Simulation time 45006663 ps
CPU time 1.72 seconds
Started Sep 09 11:45:15 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226386414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1226386414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/273.edn_genbits.3229799717
Short name T942
Test name
Test status
Simulation time 68800666 ps
CPU time 2.17 seconds
Started Sep 09 11:45:15 AM UTC 24
Finished Sep 09 11:45:22 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229799717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3229799717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/274.edn_genbits.3554338820
Short name T939
Test name
Test status
Simulation time 35718291 ps
CPU time 1.38 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554338820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3554338820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/275.edn_genbits.1338755276
Short name T940
Test name
Test status
Simulation time 57617455 ps
CPU time 1.62 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338755276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1338755276
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/276.edn_genbits.1187098728
Short name T936
Test name
Test status
Simulation time 43589473 ps
CPU time 1.18 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187098728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1187098728
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/277.edn_genbits.1458118123
Short name T938
Test name
Test status
Simulation time 85393945 ps
CPU time 1.26 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458118123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1458118123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/278.edn_genbits.3430637856
Short name T937
Test name
Test status
Simulation time 26446324 ps
CPU time 1.16 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430637856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3430637856
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/279.edn_genbits.3717645549
Short name T943
Test name
Test status
Simulation time 266395774 ps
CPU time 0.97 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:24 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717645549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3717645549
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_alert.2383262430
Short name T207
Test name
Test status
Simulation time 22264614 ps
CPU time 1.69 seconds
Started Sep 09 11:42:28 AM UTC 24
Finished Sep 09 11:42:31 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383262430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_alert.2383262430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_alert_test.2701775283
Short name T445
Test name
Test status
Simulation time 125987977 ps
CPU time 1.35 seconds
Started Sep 09 11:42:30 AM UTC 24
Finished Sep 09 11:42:33 AM UTC 24
Peak memory 217100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701775283 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2701775283
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_disable.4046727821
Short name T444
Test name
Test status
Simulation time 29839311 ps
CPU time 1.23 seconds
Started Sep 09 11:42:30 AM UTC 24
Finished Sep 09 11:42:32 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046727821 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4046727821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.63857922
Short name T447
Test name
Test status
Simulation time 39043312 ps
CPU time 1.93 seconds
Started Sep 09 11:42:30 AM UTC 24
Finished Sep 09 11:42:33 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63857922 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.63857922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_err.4012367200
Short name T442
Test name
Test status
Simulation time 24430380 ps
CPU time 1.68 seconds
Started Sep 09 11:42:28 AM UTC 24
Finished Sep 09 11:42:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012367200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.4012367200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_genbits.1639250991
Short name T440
Test name
Test status
Simulation time 60570037 ps
CPU time 2.22 seconds
Started Sep 09 11:42:25 AM UTC 24
Finished Sep 09 11:42:29 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639250991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1639250991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_intr.3648221332
Short name T441
Test name
Test status
Simulation time 27138434 ps
CPU time 1.61 seconds
Started Sep 09 11:42:28 AM UTC 24
Finished Sep 09 11:42:31 AM UTC 24
Peak memory 236168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648221332 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.3648221332
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_smoke.996264527
Short name T439
Test name
Test status
Simulation time 45720476 ps
CPU time 1.38 seconds
Started Sep 09 11:42:25 AM UTC 24
Finished Sep 09 11:42:28 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996264527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.edn_smoke.996264527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_stress_all.1431565006
Short name T443
Test name
Test status
Simulation time 178817781 ps
CPU time 3.37 seconds
Started Sep 09 11:42:27 AM UTC 24
Finished Sep 09 11:42:32 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431565006 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1431565006
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.1667747910
Short name T339
Test name
Test status
Simulation time 17327962098 ps
CPU time 78.59 seconds
Started Sep 09 11:42:27 AM UTC 24
Finished Sep 09 11:43:48 AM UTC 24
Peak memory 229756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1667747910 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all
_with_rand_reset.1667747910
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/280.edn_genbits.2882148992
Short name T944
Test name
Test status
Simulation time 47724902 ps
CPU time 1.02 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:24 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882148992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2882148992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/281.edn_genbits.391388850
Short name T946
Test name
Test status
Simulation time 52055163 ps
CPU time 1.18 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:24 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391388850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 281.edn_genbits.391388850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/282.edn_genbits.3154946497
Short name T945
Test name
Test status
Simulation time 84676096 ps
CPU time 1.14 seconds
Started Sep 09 11:45:16 AM UTC 24
Finished Sep 09 11:45:24 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154946497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3154946497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/283.edn_genbits.1126783777
Short name T934
Test name
Test status
Simulation time 109910989 ps
CPU time 1.25 seconds
Started Sep 09 11:45:17 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126783777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1126783777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/284.edn_genbits.1083833105
Short name T935
Test name
Test status
Simulation time 56084404 ps
CPU time 1.25 seconds
Started Sep 09 11:45:17 AM UTC 24
Finished Sep 09 11:45:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083833105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1083833105
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/285.edn_genbits.3810203645
Short name T971
Test name
Test status
Simulation time 89528182 ps
CPU time 1.07 seconds
Started Sep 09 11:45:21 AM UTC 24
Finished Sep 09 11:45:41 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810203645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3810203645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/286.edn_genbits.1944054224
Short name T970
Test name
Test status
Simulation time 82130920 ps
CPU time 1.24 seconds
Started Sep 09 11:45:21 AM UTC 24
Finished Sep 09 11:45:40 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944054224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1944054224
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/287.edn_genbits.4234977809
Short name T947
Test name
Test status
Simulation time 60370707 ps
CPU time 0.93 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 228156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234977809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4234977809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/288.edn_genbits.3994624897
Short name T336
Test name
Test status
Simulation time 84621272 ps
CPU time 1.26 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 228148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994624897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3994624897
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/289.edn_genbits.1603236582
Short name T950
Test name
Test status
Simulation time 30223812 ps
CPU time 1.23 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603236582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1603236582
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_alert.1423782047
Short name T108
Test name
Test status
Simulation time 83291745 ps
CPU time 1.6 seconds
Started Sep 09 11:42:34 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423782047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.1423782047
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_alert_test.3419360660
Short name T448
Test name
Test status
Simulation time 13154040 ps
CPU time 1.28 seconds
Started Sep 09 11:42:35 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419360660 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3419360660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_disable.1137312726
Short name T241
Test name
Test status
Simulation time 17171574 ps
CPU time 1.29 seconds
Started Sep 09 11:42:34 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137312726 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1137312726
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.921722316
Short name T236
Test name
Test status
Simulation time 32585391 ps
CPU time 1.77 seconds
Started Sep 09 11:42:34 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921722316 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.921722316
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_err.2904627001
Short name T209
Test name
Test status
Simulation time 22698241 ps
CPU time 1.32 seconds
Started Sep 09 11:42:34 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904627001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.2904627001
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_genbits.3710213356
Short name T357
Test name
Test status
Simulation time 51505379 ps
CPU time 1.63 seconds
Started Sep 09 11:42:30 AM UTC 24
Finished Sep 09 11:42:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710213356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3710213356
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_intr.2603167050
Short name T406
Test name
Test status
Simulation time 26135703 ps
CPU time 1.39 seconds
Started Sep 09 11:42:32 AM UTC 24
Finished Sep 09 11:42:35 AM UTC 24
Peak memory 226308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603167050 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.2603167050
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_smoke.1586372424
Short name T446
Test name
Test status
Simulation time 30869078 ps
CPU time 1.44 seconds
Started Sep 09 11:42:30 AM UTC 24
Finished Sep 09 11:42:33 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586372424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.1586372424
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_stress_all.2493901792
Short name T271
Test name
Test status
Simulation time 1008797161 ps
CPU time 7.57 seconds
Started Sep 09 11:42:32 AM UTC 24
Finished Sep 09 11:42:41 AM UTC 24
Peak memory 231532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493901792 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2493901792
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.3804121641
Short name T871
Test name
Test status
Simulation time 20033056136 ps
CPU time 144.59 seconds
Started Sep 09 11:42:32 AM UTC 24
Finished Sep 09 11:45:00 AM UTC 24
Peak memory 233852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3804121641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all
_with_rand_reset.3804121641
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/290.edn_genbits.2884420386
Short name T949
Test name
Test status
Simulation time 74517298 ps
CPU time 1.23 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 230660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884420386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2884420386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/291.edn_genbits.2980616351
Short name T951
Test name
Test status
Simulation time 59835740 ps
CPU time 1.37 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980616351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2980616351
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/292.edn_genbits.1962649362
Short name T952
Test name
Test status
Simulation time 106592521 ps
CPU time 1.71 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962649362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1962649362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/293.edn_genbits.245364309
Short name T948
Test name
Test status
Simulation time 129072130 ps
CPU time 0.91 seconds
Started Sep 09 11:45:22 AM UTC 24
Finished Sep 09 11:45:25 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245364309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 293.edn_genbits.245364309
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/294.edn_genbits.2504110976
Short name T962
Test name
Test status
Simulation time 42615829 ps
CPU time 1.29 seconds
Started Sep 09 11:45:23 AM UTC 24
Finished Sep 09 11:45:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504110976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2504110976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/295.edn_genbits.910025829
Short name T964
Test name
Test status
Simulation time 29726357 ps
CPU time 1.06 seconds
Started Sep 09 11:45:24 AM UTC 24
Finished Sep 09 11:45:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910025829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 295.edn_genbits.910025829
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/296.edn_genbits.2899271687
Short name T967
Test name
Test status
Simulation time 59078056 ps
CPU time 1.82 seconds
Started Sep 09 11:45:25 AM UTC 24
Finished Sep 09 11:45:35 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899271687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2899271687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/297.edn_genbits.141173456
Short name T966
Test name
Test status
Simulation time 38362953 ps
CPU time 1.23 seconds
Started Sep 09 11:45:25 AM UTC 24
Finished Sep 09 11:45:34 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141173456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 297.edn_genbits.141173456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/298.edn_genbits.1845789535
Short name T968
Test name
Test status
Simulation time 48518316 ps
CPU time 1.08 seconds
Started Sep 09 11:45:25 AM UTC 24
Finished Sep 09 11:45:35 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845789535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1845789535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/299.edn_genbits.1075970505
Short name T969
Test name
Test status
Simulation time 38820341 ps
CPU time 1.16 seconds
Started Sep 09 11:45:25 AM UTC 24
Finished Sep 09 11:45:35 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075970505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1075970505
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_alert.2395822634
Short name T141
Test name
Test status
Simulation time 41831733 ps
CPU time 1.71 seconds
Started Sep 09 11:40:57 AM UTC 24
Finished Sep 09 11:41:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395822634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.2395822634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_alert_test.4061795718
Short name T363
Test name
Test status
Simulation time 147147404 ps
CPU time 1.22 seconds
Started Sep 09 11:40:58 AM UTC 24
Finished Sep 09 11:41:01 AM UTC 24
Peak memory 215604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061795718 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4061795718
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.329258927
Short name T45
Test name
Test status
Simulation time 29228994 ps
CPU time 1.65 seconds
Started Sep 09 11:40:57 AM UTC 24
Finished Sep 09 11:41:00 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329258927 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.329258927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_err.1740838207
Short name T72
Test name
Test status
Simulation time 18785999 ps
CPU time 1.58 seconds
Started Sep 09 11:40:57 AM UTC 24
Finished Sep 09 11:41:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740838207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.1740838207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_genbits.3498088477
Short name T49
Test name
Test status
Simulation time 71506518 ps
CPU time 4.04 seconds
Started Sep 09 11:40:54 AM UTC 24
Finished Sep 09 11:41:00 AM UTC 24
Peak memory 231600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498088477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3498088477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_intr.2797123676
Short name T71
Test name
Test status
Simulation time 37368920 ps
CPU time 1.37 seconds
Started Sep 09 11:40:57 AM UTC 24
Finished Sep 09 11:40:59 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797123676 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.2797123676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_sec_cm.3055261160
Short name T63
Test name
Test status
Simulation time 1315056490 ps
CPU time 13.65 seconds
Started Sep 09 11:40:57 AM UTC 24
Finished Sep 09 11:41:12 AM UTC 24
Peak memory 262384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055261160 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3055261160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/3.edn_smoke.2456849954
Short name T88
Test name
Test status
Simulation time 18576004 ps
CPU time 1.37 seconds
Started Sep 09 11:40:54 AM UTC 24
Finished Sep 09 11:40:57 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456849954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.2456849954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_alert.171623331
Short name T300
Test name
Test status
Simulation time 48343413 ps
CPU time 1.73 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171623331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.edn_alert.171623331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_alert_test.2981977974
Short name T453
Test name
Test status
Simulation time 42914108 ps
CPU time 1.29 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 217032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981977974 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2981977974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_disable.3390224985
Short name T206
Test name
Test status
Simulation time 42617435 ps
CPU time 1.16 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390224985 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3390224985
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1107255797
Short name T455
Test name
Test status
Simulation time 32142680 ps
CPU time 1.64 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107255797 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1107255797
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_err.2104369429
Short name T204
Test name
Test status
Simulation time 19221995 ps
CPU time 1.68 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104369429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.2104369429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_genbits.3331531027
Short name T450
Test name
Test status
Simulation time 185571776 ps
CPU time 1.63 seconds
Started Sep 09 11:42:35 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331531027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3331531027
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_intr.163715202
Short name T452
Test name
Test status
Simulation time 37270905 ps
CPU time 1.38 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163715202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.163715202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_smoke.2560323832
Short name T449
Test name
Test status
Simulation time 48677069 ps
CPU time 1.36 seconds
Started Sep 09 11:42:35 AM UTC 24
Finished Sep 09 11:42:37 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560323832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_smoke.2560323832
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_stress_all.1979673215
Short name T456
Test name
Test status
Simulation time 1320179967 ps
CPU time 4.52 seconds
Started Sep 09 11:42:37 AM UTC 24
Finished Sep 09 11:42:43 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979673215 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1979673215
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.2281582224
Short name T491
Test name
Test status
Simulation time 1611133980 ps
CPU time 22.97 seconds
Started Sep 09 11:42:37 AM UTC 24
Finished Sep 09 11:43:01 AM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2281582224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all
_with_rand_reset.2281582224
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_alert.1794547019
Short name T177
Test name
Test status
Simulation time 30966525 ps
CPU time 1.72 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794547019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_alert.1794547019
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_alert_test.3997881320
Short name T459
Test name
Test status
Simulation time 18951340 ps
CPU time 1.19 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997881320 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3997881320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_disable.1590563941
Short name T233
Test name
Test status
Simulation time 17064896 ps
CPU time 1.27 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590563941 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1590563941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.1254692851
Short name T460
Test name
Test status
Simulation time 38029421 ps
CPU time 1.33 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254692851 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1254692851
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_err.1249298453
Short name T151
Test name
Test status
Simulation time 25804017 ps
CPU time 1.67 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 243736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249298453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.1249298453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_intr.3835401892
Short name T457
Test name
Test status
Simulation time 25427233 ps
CPU time 1.18 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 237600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835401892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.3835401892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_smoke.144607760
Short name T454
Test name
Test status
Simulation time 46888787 ps
CPU time 1.3 seconds
Started Sep 09 11:42:39 AM UTC 24
Finished Sep 09 11:42:42 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144607760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_smoke.144607760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_stress_all.356815758
Short name T458
Test name
Test status
Simulation time 91417669 ps
CPU time 1.52 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356815758 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.356815758
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.372049344
Short name T547
Test name
Test status
Simulation time 3029607686 ps
CPU time 40.65 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:43:25 AM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=372049344 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_
with_rand_reset.372049344
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_alert.3753194244
Short name T463
Test name
Test status
Simulation time 84800938 ps
CPU time 1.18 seconds
Started Sep 09 11:42:47 AM UTC 24
Finished Sep 09 11:42:50 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753194244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.3753194244
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_alert_test.862737855
Short name T464
Test name
Test status
Simulation time 22660229 ps
CPU time 1.25 seconds
Started Sep 09 11:42:47 AM UTC 24
Finished Sep 09 11:42:50 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862737855 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.862737855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_disable.286706989
Short name T234
Test name
Test status
Simulation time 21472946 ps
CPU time 1.27 seconds
Started Sep 09 11:42:47 AM UTC 24
Finished Sep 09 11:42:50 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286706989 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.286706989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.722370033
Short name T466
Test name
Test status
Simulation time 125085778 ps
CPU time 1.68 seconds
Started Sep 09 11:42:47 AM UTC 24
Finished Sep 09 11:42:50 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722370033 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.722370033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_err.3163359021
Short name T145
Test name
Test status
Simulation time 59385763 ps
CPU time 1.69 seconds
Started Sep 09 11:42:47 AM UTC 24
Finished Sep 09 11:42:50 AM UTC 24
Peak memory 244336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163359021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.3163359021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_genbits.2967505183
Short name T100
Test name
Test status
Simulation time 75959504 ps
CPU time 1.39 seconds
Started Sep 09 11:42:46 AM UTC 24
Finished Sep 09 11:42:49 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967505183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2967505183
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_intr.2565849798
Short name T462
Test name
Test status
Simulation time 39699401 ps
CPU time 1.36 seconds
Started Sep 09 11:42:46 AM UTC 24
Finished Sep 09 11:42:49 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565849798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.2565849798
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_smoke.3977100540
Short name T461
Test name
Test status
Simulation time 55086921 ps
CPU time 1.38 seconds
Started Sep 09 11:42:43 AM UTC 24
Finished Sep 09 11:42:46 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977100540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.3977100540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_stress_all.2272988516
Short name T326
Test name
Test status
Simulation time 22694378 ps
CPU time 1.52 seconds
Started Sep 09 11:42:46 AM UTC 24
Finished Sep 09 11:42:49 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272988516 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2272988516
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.3228427594
Short name T495
Test name
Test status
Simulation time 500577320 ps
CPU time 15.63 seconds
Started Sep 09 11:42:46 AM UTC 24
Finished Sep 09 11:43:03 AM UTC 24
Peak memory 231652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3228427594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all
_with_rand_reset.3228427594
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_alert.4047177919
Short name T470
Test name
Test status
Simulation time 28465797 ps
CPU time 1.9 seconds
Started Sep 09 11:42:50 AM UTC 24
Finished Sep 09 11:42:53 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047177919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_alert.4047177919
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_alert_test.1809941802
Short name T472
Test name
Test status
Simulation time 53529168 ps
CPU time 1.36 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:42:54 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809941802 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1809941802
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_disable.2190319853
Short name T468
Test name
Test status
Simulation time 119360138 ps
CPU time 1.28 seconds
Started Sep 09 11:42:50 AM UTC 24
Finished Sep 09 11:42:52 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190319853 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2190319853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.2164936970
Short name T475
Test name
Test status
Simulation time 29315984 ps
CPU time 1.69 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:42:54 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164936970 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.2164936970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_err.2372600150
Short name T469
Test name
Test status
Simulation time 30941701 ps
CPU time 1.43 seconds
Started Sep 09 11:42:50 AM UTC 24
Finished Sep 09 11:42:52 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372600150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.2372600150
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_genbits.2004107229
Short name T14
Test name
Test status
Simulation time 90429377 ps
CPU time 2.23 seconds
Started Sep 09 11:42:48 AM UTC 24
Finished Sep 09 11:42:51 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004107229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2004107229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_intr.1916739169
Short name T113
Test name
Test status
Simulation time 21069764 ps
CPU time 1.65 seconds
Started Sep 09 11:42:48 AM UTC 24
Finished Sep 09 11:42:51 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916739169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.1916739169
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_smoke.31709868
Short name T465
Test name
Test status
Simulation time 26929942 ps
CPU time 1.38 seconds
Started Sep 09 11:42:47 AM UTC 24
Finished Sep 09 11:42:50 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31709868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_smoke.31709868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_stress_all.4110441844
Short name T270
Test name
Test status
Simulation time 405551660 ps
CPU time 2.92 seconds
Started Sep 09 11:42:48 AM UTC 24
Finished Sep 09 11:42:52 AM UTC 24
Peak memory 229504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110441844 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4110441844
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.1102419828
Short name T658
Test name
Test status
Simulation time 9482203337 ps
CPU time 75.52 seconds
Started Sep 09 11:42:48 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 233816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1102419828 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all
_with_rand_reset.1102419828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_alert.3574816865
Short name T477
Test name
Test status
Simulation time 47473516 ps
CPU time 1.51 seconds
Started Sep 09 11:42:52 AM UTC 24
Finished Sep 09 11:42:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574816865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_alert.3574816865
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_alert_test.1964512863
Short name T478
Test name
Test status
Simulation time 44120411 ps
CPU time 1.07 seconds
Started Sep 09 11:42:54 AM UTC 24
Finished Sep 09 11:42:56 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964512863 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1964512863
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_disable.2362023048
Short name T479
Test name
Test status
Simulation time 10880373 ps
CPU time 1.35 seconds
Started Sep 09 11:42:54 AM UTC 24
Finished Sep 09 11:42:56 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362023048 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2362023048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.2250847124
Short name T481
Test name
Test status
Simulation time 46080049 ps
CPU time 1.6 seconds
Started Sep 09 11:42:54 AM UTC 24
Finished Sep 09 11:42:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250847124 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.2250847124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_err.83776302
Short name T188
Test name
Test status
Simulation time 63426118 ps
CPU time 1.47 seconds
Started Sep 09 11:42:52 AM UTC 24
Finished Sep 09 11:42:55 AM UTC 24
Peak memory 243856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83776302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 34.edn_err.83776302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_genbits.2175075177
Short name T474
Test name
Test status
Simulation time 116264754 ps
CPU time 1.49 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:42:54 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175075177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2175075177
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_intr.3845093131
Short name T471
Test name
Test status
Simulation time 88932250 ps
CPU time 1.09 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:42:54 AM UTC 24
Peak memory 237204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845093131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.3845093131
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_smoke.1901162578
Short name T473
Test name
Test status
Simulation time 14934119 ps
CPU time 1.42 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:42:54 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901162578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.1901162578
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_stress_all.582655876
Short name T476
Test name
Test status
Simulation time 229513261 ps
CPU time 2.31 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:42:55 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582655876 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.582655876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.2288288528
Short name T625
Test name
Test status
Simulation time 4599693600 ps
CPU time 59.49 seconds
Started Sep 09 11:42:51 AM UTC 24
Finished Sep 09 11:43:53 AM UTC 24
Peak memory 233904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2288288528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all
_with_rand_reset.2288288528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_alert.1777913761
Short name T178
Test name
Test status
Simulation time 34084953 ps
CPU time 1.98 seconds
Started Sep 09 11:42:55 AM UTC 24
Finished Sep 09 11:42:58 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777913761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.1777913761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_alert_test.437948619
Short name T486
Test name
Test status
Simulation time 17338907 ps
CPU time 1.44 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:42:59 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437948619 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.437948619
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_disable.3721428569
Short name T484
Test name
Test status
Simulation time 14600982 ps
CPU time 1.3 seconds
Started Sep 09 11:42:55 AM UTC 24
Finished Sep 09 11:42:58 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721428569 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3721428569
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.1861977237
Short name T487
Test name
Test status
Simulation time 82918345 ps
CPU time 1.59 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:42:59 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861977237 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.1861977237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_err.1859019454
Short name T482
Test name
Test status
Simulation time 18678972 ps
CPU time 1.15 seconds
Started Sep 09 11:42:55 AM UTC 24
Finished Sep 09 11:42:57 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859019454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.1859019454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_genbits.2498263674
Short name T331
Test name
Test status
Simulation time 140498990 ps
CPU time 2.46 seconds
Started Sep 09 11:42:55 AM UTC 24
Finished Sep 09 11:42:59 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498263674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2498263674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_intr.1931529138
Short name T483
Test name
Test status
Simulation time 36979789 ps
CPU time 1.45 seconds
Started Sep 09 11:42:55 AM UTC 24
Finished Sep 09 11:42:58 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931529138 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.1931529138
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_smoke.3097071282
Short name T480
Test name
Test status
Simulation time 18669622 ps
CPU time 1.44 seconds
Started Sep 09 11:42:54 AM UTC 24
Finished Sep 09 11:42:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097071282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_smoke.3097071282
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/35.edn_stress_all.1227035573
Short name T497
Test name
Test status
Simulation time 947345672 ps
CPU time 7.29 seconds
Started Sep 09 11:42:55 AM UTC 24
Finished Sep 09 11:43:03 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227035573 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1227035573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_alert.1992810483
Short name T157
Test name
Test status
Simulation time 108138985 ps
CPU time 1.79 seconds
Started Sep 09 11:42:58 AM UTC 24
Finished Sep 09 11:43:01 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992810483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.1992810483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_alert_test.2252559831
Short name T492
Test name
Test status
Simulation time 152153835 ps
CPU time 1.21 seconds
Started Sep 09 11:42:59 AM UTC 24
Finished Sep 09 11:43:02 AM UTC 24
Peak memory 216612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252559831 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2252559831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_disable.1950678397
Short name T490
Test name
Test status
Simulation time 12860768 ps
CPU time 1.35 seconds
Started Sep 09 11:42:58 AM UTC 24
Finished Sep 09 11:43:01 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950678397 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1950678397
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.4007310500
Short name T493
Test name
Test status
Simulation time 73654566 ps
CPU time 1.84 seconds
Started Sep 09 11:42:59 AM UTC 24
Finished Sep 09 11:43:02 AM UTC 24
Peak memory 225952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007310500 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.4007310500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_err.3380705277
Short name T229
Test name
Test status
Simulation time 41091476 ps
CPU time 1.63 seconds
Started Sep 09 11:42:58 AM UTC 24
Finished Sep 09 11:43:01 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380705277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.3380705277
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_genbits.1942148270
Short name T333
Test name
Test status
Simulation time 76237145 ps
CPU time 1.72 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:43:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942148270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1942148270
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_intr.1008204422
Short name T485
Test name
Test status
Simulation time 26197493 ps
CPU time 1.16 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:42:59 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008204422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.1008204422
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_smoke.1426167571
Short name T488
Test name
Test status
Simulation time 27449059 ps
CPU time 1.43 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:42:59 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426167571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.1426167571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_stress_all.206089043
Short name T489
Test name
Test status
Simulation time 228010272 ps
CPU time 1.94 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:43:00 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206089043 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.206089043
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.2217169345
Short name T604
Test name
Test status
Simulation time 2280847447 ps
CPU time 47.31 seconds
Started Sep 09 11:42:57 AM UTC 24
Finished Sep 09 11:43:46 AM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2217169345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all
_with_rand_reset.2217169345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_alert.484255075
Short name T210
Test name
Test status
Simulation time 28609552 ps
CPU time 1.72 seconds
Started Sep 09 11:43:01 AM UTC 24
Finished Sep 09 11:43:03 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484255075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.edn_alert.484255075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_alert_test.3469677855
Short name T500
Test name
Test status
Simulation time 25797860 ps
CPU time 1.32 seconds
Started Sep 09 11:43:02 AM UTC 24
Finished Sep 09 11:43:04 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469677855 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3469677855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_disable.744974333
Short name T498
Test name
Test status
Simulation time 14543131 ps
CPU time 1.08 seconds
Started Sep 09 11:43:02 AM UTC 24
Finished Sep 09 11:43:04 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744974333 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.744974333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.3758616057
Short name T499
Test name
Test status
Simulation time 65083025 ps
CPU time 1.34 seconds
Started Sep 09 11:43:02 AM UTC 24
Finished Sep 09 11:43:04 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758616057 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.3758616057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_err.3025934939
Short name T183
Test name
Test status
Simulation time 27700487 ps
CPU time 1.74 seconds
Started Sep 09 11:43:02 AM UTC 24
Finished Sep 09 11:43:05 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025934939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.3025934939
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_genbits.1591319146
Short name T340
Test name
Test status
Simulation time 135345024 ps
CPU time 2.21 seconds
Started Sep 09 11:43:01 AM UTC 24
Finished Sep 09 11:43:04 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591319146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1591319146
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_intr.3039621221
Short name T496
Test name
Test status
Simulation time 46983452 ps
CPU time 1.43 seconds
Started Sep 09 11:43:01 AM UTC 24
Finished Sep 09 11:43:03 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039621221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.3039621221
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_smoke.2868591860
Short name T494
Test name
Test status
Simulation time 16603842 ps
CPU time 1.42 seconds
Started Sep 09 11:43:00 AM UTC 24
Finished Sep 09 11:43:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868591860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.2868591860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_stress_all.3310745151
Short name T501
Test name
Test status
Simulation time 85915020 ps
CPU time 2.74 seconds
Started Sep 09 11:43:01 AM UTC 24
Finished Sep 09 11:43:04 AM UTC 24
Peak memory 227660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310745151 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3310745151
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.51239137
Short name T256
Test name
Test status
Simulation time 2948342144 ps
CPU time 31.66 seconds
Started Sep 09 11:43:01 AM UTC 24
Finished Sep 09 11:43:34 AM UTC 24
Peak memory 231752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=51239137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_w
ith_rand_reset.51239137
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_alert.1997501927
Short name T164
Test name
Test status
Simulation time 43205807 ps
CPU time 1.7 seconds
Started Sep 09 11:43:05 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997501927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_alert.1997501927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_alert_test.382770840
Short name T505
Test name
Test status
Simulation time 65225341 ps
CPU time 1.26 seconds
Started Sep 09 11:43:05 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382770840 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.382770840
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.3195442423
Short name T237
Test name
Test status
Simulation time 79027431 ps
CPU time 1.37 seconds
Started Sep 09 11:43:05 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195442423 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.3195442423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_err.4264185273
Short name T504
Test name
Test status
Simulation time 20325345 ps
CPU time 1.34 seconds
Started Sep 09 11:43:05 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264185273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.edn_err.4264185273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_genbits.278543457
Short name T503
Test name
Test status
Simulation time 43680503 ps
CPU time 1.86 seconds
Started Sep 09 11:43:03 AM UTC 24
Finished Sep 09 11:43:06 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278543457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.278543457
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_intr.4055387070
Short name T30
Test name
Test status
Simulation time 21486270 ps
CPU time 1.55 seconds
Started Sep 09 11:43:05 AM UTC 24
Finished Sep 09 11:43:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055387070 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.4055387070
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_smoke.1234542448
Short name T502
Test name
Test status
Simulation time 18072716 ps
CPU time 1.48 seconds
Started Sep 09 11:43:03 AM UTC 24
Finished Sep 09 11:43:06 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234542448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.1234542448
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_stress_all.3123730073
Short name T272
Test name
Test status
Simulation time 151807542 ps
CPU time 4.65 seconds
Started Sep 09 11:43:04 AM UTC 24
Finished Sep 09 11:43:10 AM UTC 24
Peak memory 227676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123730073 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3123730073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.1533721339
Short name T572
Test name
Test status
Simulation time 2644445407 ps
CPU time 28.13 seconds
Started Sep 09 11:43:04 AM UTC 24
Finished Sep 09 11:43:34 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1533721339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all
_with_rand_reset.1533721339
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_alert.2788642755
Short name T179
Test name
Test status
Simulation time 31819390 ps
CPU time 1.72 seconds
Started Sep 09 11:43:07 AM UTC 24
Finished Sep 09 11:43:10 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788642755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.2788642755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_alert_test.3725653056
Short name T511
Test name
Test status
Simulation time 59866620 ps
CPU time 1.34 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725653056 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3725653056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_disable.2139477995
Short name T508
Test name
Test status
Simulation time 16768360 ps
CPU time 1.26 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139477995 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2139477995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.3293010635
Short name T512
Test name
Test status
Simulation time 88486286 ps
CPU time 1.53 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293010635 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.3293010635
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_err.1771485050
Short name T509
Test name
Test status
Simulation time 21014607 ps
CPU time 1.39 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771485050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.1771485050
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_genbits.4053345138
Short name T507
Test name
Test status
Simulation time 74161193 ps
CPU time 1.62 seconds
Started Sep 09 11:43:06 AM UTC 24
Finished Sep 09 11:43:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053345138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4053345138
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_intr.3858403701
Short name T451
Test name
Test status
Simulation time 23228831 ps
CPU time 1.11 seconds
Started Sep 09 11:43:06 AM UTC 24
Finished Sep 09 11:43:08 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858403701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.3858403701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_smoke.3004655552
Short name T506
Test name
Test status
Simulation time 22564420 ps
CPU time 1.33 seconds
Started Sep 09 11:43:06 AM UTC 24
Finished Sep 09 11:43:08 AM UTC 24
Peak memory 225988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004655552 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.3004655552
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/39.edn_stress_all.336991630
Short name T516
Test name
Test status
Simulation time 821015009 ps
CPU time 4.64 seconds
Started Sep 09 11:43:06 AM UTC 24
Finished Sep 09 11:43:12 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336991630 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.336991630
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_alert_test.1139596490
Short name T364
Test name
Test status
Simulation time 25667351 ps
CPU time 1.37 seconds
Started Sep 09 11:41:03 AM UTC 24
Finished Sep 09 11:41:05 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139596490 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1139596490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_disable.2546585153
Short name T52
Test name
Test status
Simulation time 13121151 ps
CPU time 1.36 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:04 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546585153 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2546585153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.618421035
Short name T81
Test name
Test status
Simulation time 29581077 ps
CPU time 1.65 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:04 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618421035 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.618421035
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_err.4029286803
Short name T62
Test name
Test status
Simulation time 18481449 ps
CPU time 1.71 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:04 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029286803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.4029286803
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_genbits.3235943885
Short name T50
Test name
Test status
Simulation time 60465435 ps
CPU time 1.93 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235943885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3235943885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_intr.2907549907
Short name T61
Test name
Test status
Simulation time 37244324 ps
CPU time 1.5 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:04 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907549907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.2907549907
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_regwen.476966572
Short name T321
Test name
Test status
Simulation time 135298211 ps
CPU time 1.45 seconds
Started Sep 09 11:41:01 AM UTC 24
Finished Sep 09 11:41:03 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476966572 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_regwen.476966572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_sec_cm.3164974056
Short name T64
Test name
Test status
Simulation time 644529795 ps
CPU time 12.11 seconds
Started Sep 09 11:41:03 AM UTC 24
Finished Sep 09 11:41:16 AM UTC 24
Peak memory 260428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164974056 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3164974056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/4.edn_smoke.1467951074
Short name T136
Test name
Test status
Simulation time 18908440 ps
CPU time 1.52 seconds
Started Sep 09 11:40:58 AM UTC 24
Finished Sep 09 11:41:01 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467951074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.1467951074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_alert.2843877163
Short name T146
Test name
Test status
Simulation time 89463339 ps
CPU time 1.43 seconds
Started Sep 09 11:43:10 AM UTC 24
Finished Sep 09 11:43:12 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843877163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.2843877163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_alert_test.2672547896
Short name T520
Test name
Test status
Simulation time 32941049 ps
CPU time 1.27 seconds
Started Sep 09 11:43:11 AM UTC 24
Finished Sep 09 11:43:13 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672547896 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2672547896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_disable.3436022732
Short name T519
Test name
Test status
Simulation time 11993577 ps
CPU time 0.96 seconds
Started Sep 09 11:43:11 AM UTC 24
Finished Sep 09 11:43:13 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436022732 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3436022732
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.3490099967
Short name T523
Test name
Test status
Simulation time 40876190 ps
CPU time 1.91 seconds
Started Sep 09 11:43:11 AM UTC 24
Finished Sep 09 11:43:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490099967 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.3490099967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_err.381991849
Short name T518
Test name
Test status
Simulation time 45915173 ps
CPU time 1.44 seconds
Started Sep 09 11:43:10 AM UTC 24
Finished Sep 09 11:43:12 AM UTC 24
Peak memory 228324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381991849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.edn_err.381991849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_genbits.4098597177
Short name T513
Test name
Test status
Simulation time 44579382 ps
CPU time 1.53 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098597177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4098597177
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_intr.4043732852
Short name T517
Test name
Test status
Simulation time 34284411 ps
CPU time 1.19 seconds
Started Sep 09 11:43:10 AM UTC 24
Finished Sep 09 11:43:12 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043732852 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.4043732852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_smoke.3660243760
Short name T510
Test name
Test status
Simulation time 48750957 ps
CPU time 1.22 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660243760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.3660243760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_stress_all.619405397
Short name T515
Test name
Test status
Simulation time 426426661 ps
CPU time 1.96 seconds
Started Sep 09 11:43:08 AM UTC 24
Finished Sep 09 11:43:11 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619405397 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.619405397
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.234450587
Short name T257
Test name
Test status
Simulation time 6516953519 ps
CPU time 42.04 seconds
Started Sep 09 11:43:10 AM UTC 24
Finished Sep 09 11:43:53 AM UTC 24
Peak memory 231908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=234450587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_
with_rand_reset.234450587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_alert.3286069200
Short name T525
Test name
Test status
Simulation time 25156459 ps
CPU time 1.72 seconds
Started Sep 09 11:43:13 AM UTC 24
Finished Sep 09 11:43:15 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286069200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.3286069200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_alert_test.1843924945
Short name T528
Test name
Test status
Simulation time 44357131 ps
CPU time 1.26 seconds
Started Sep 09 11:43:14 AM UTC 24
Finished Sep 09 11:43:16 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843924945 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1843924945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_disable.3861697351
Short name T228
Test name
Test status
Simulation time 26130100 ps
CPU time 1.16 seconds
Started Sep 09 11:43:13 AM UTC 24
Finished Sep 09 11:43:15 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861697351 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3861697351
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.1994339260
Short name T526
Test name
Test status
Simulation time 54741207 ps
CPU time 1.64 seconds
Started Sep 09 11:43:13 AM UTC 24
Finished Sep 09 11:43:15 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994339260 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.1994339260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_genbits.187148278
Short name T522
Test name
Test status
Simulation time 41569185 ps
CPU time 1.75 seconds
Started Sep 09 11:43:11 AM UTC 24
Finished Sep 09 11:43:14 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187148278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_genbits.187148278
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_intr.1553334210
Short name T524
Test name
Test status
Simulation time 23689363 ps
CPU time 1.56 seconds
Started Sep 09 11:43:12 AM UTC 24
Finished Sep 09 11:43:15 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553334210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.1553334210
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_smoke.194133698
Short name T521
Test name
Test status
Simulation time 31248187 ps
CPU time 1.38 seconds
Started Sep 09 11:43:11 AM UTC 24
Finished Sep 09 11:43:13 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194133698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.edn_smoke.194133698
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/41.edn_stress_all.43262099
Short name T327
Test name
Test status
Simulation time 361105382 ps
CPU time 2.81 seconds
Started Sep 09 11:43:12 AM UTC 24
Finished Sep 09 11:43:16 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43262099 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.43262099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_alert.215095924
Short name T317
Test name
Test status
Simulation time 111967343 ps
CPU time 1.86 seconds
Started Sep 09 11:43:15 AM UTC 24
Finished Sep 09 11:43:18 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215095924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_alert.215095924
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_alert_test.244313914
Short name T530
Test name
Test status
Simulation time 11954913 ps
CPU time 1.23 seconds
Started Sep 09 11:43:17 AM UTC 24
Finished Sep 09 11:43:19 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244313914 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.244313914
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.4235801238
Short name T532
Test name
Test status
Simulation time 29727543 ps
CPU time 1.63 seconds
Started Sep 09 11:43:17 AM UTC 24
Finished Sep 09 11:43:19 AM UTC 24
Peak memory 228604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235801238 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.4235801238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_err.124957249
Short name T152
Test name
Test status
Simulation time 26366519 ps
CPU time 1.68 seconds
Started Sep 09 11:43:15 AM UTC 24
Finished Sep 09 11:43:18 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124957249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.edn_err.124957249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_genbits.2421489770
Short name T325
Test name
Test status
Simulation time 47981411 ps
CPU time 1.59 seconds
Started Sep 09 11:43:14 AM UTC 24
Finished Sep 09 11:43:16 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421489770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2421489770
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_intr.1412099340
Short name T529
Test name
Test status
Simulation time 22566300 ps
CPU time 1.64 seconds
Started Sep 09 11:43:15 AM UTC 24
Finished Sep 09 11:43:18 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412099340 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.1412099340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_smoke.523325851
Short name T527
Test name
Test status
Simulation time 39885929 ps
CPU time 1.32 seconds
Started Sep 09 11:43:14 AM UTC 24
Finished Sep 09 11:43:16 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523325851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_smoke.523325851
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_stress_all.1669313126
Short name T538
Test name
Test status
Simulation time 332455024 ps
CPU time 6.89 seconds
Started Sep 09 11:43:14 AM UTC 24
Finished Sep 09 11:43:22 AM UTC 24
Peak memory 229460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669313126 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1669313126
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.2418692155
Short name T258
Test name
Test status
Simulation time 1854052669 ps
CPU time 38.48 seconds
Started Sep 09 11:43:15 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 229664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2418692155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all
_with_rand_reset.2418692155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_alert.2273761116
Short name T219
Test name
Test status
Simulation time 113844740 ps
CPU time 1.6 seconds
Started Sep 09 11:43:18 AM UTC 24
Finished Sep 09 11:43:21 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273761116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.2273761116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_alert_test.2583215801
Short name T536
Test name
Test status
Simulation time 19042945 ps
CPU time 1.22 seconds
Started Sep 09 11:43:19 AM UTC 24
Finished Sep 09 11:43:22 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583215801 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2583215801
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.4022480665
Short name T301
Test name
Test status
Simulation time 85688818 ps
CPU time 1.67 seconds
Started Sep 09 11:43:19 AM UTC 24
Finished Sep 09 11:43:22 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022480665 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.4022480665
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_err.432646457
Short name T535
Test name
Test status
Simulation time 29191995 ps
CPU time 1.66 seconds
Started Sep 09 11:43:18 AM UTC 24
Finished Sep 09 11:43:21 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432646457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.edn_err.432646457
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_genbits.722696399
Short name T533
Test name
Test status
Simulation time 41503915 ps
CPU time 1.59 seconds
Started Sep 09 11:43:17 AM UTC 24
Finished Sep 09 11:43:19 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722696399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_genbits.722696399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_intr.4179456861
Short name T148
Test name
Test status
Simulation time 35870102 ps
CPU time 1.32 seconds
Started Sep 09 11:43:18 AM UTC 24
Finished Sep 09 11:43:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179456861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.4179456861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_smoke.1424256302
Short name T531
Test name
Test status
Simulation time 44397548 ps
CPU time 1.31 seconds
Started Sep 09 11:43:17 AM UTC 24
Finished Sep 09 11:43:19 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424256302 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.1424256302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/43.edn_stress_all.3783884881
Short name T349
Test name
Test status
Simulation time 64986368 ps
CPU time 1.87 seconds
Started Sep 09 11:43:17 AM UTC 24
Finished Sep 09 11:43:20 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783884881 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3783884881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_alert.3344946445
Short name T541
Test name
Test status
Simulation time 23764435 ps
CPU time 1.27 seconds
Started Sep 09 11:43:21 AM UTC 24
Finished Sep 09 11:43:23 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344946445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.3344946445
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_alert_test.4034310444
Short name T543
Test name
Test status
Simulation time 23873795 ps
CPU time 0.98 seconds
Started Sep 09 11:43:22 AM UTC 24
Finished Sep 09 11:43:24 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034310444 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4034310444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.2134825483
Short name T545
Test name
Test status
Simulation time 37731742 ps
CPU time 1.64 seconds
Started Sep 09 11:43:22 AM UTC 24
Finished Sep 09 11:43:25 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134825483 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.2134825483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_err.2807254219
Short name T194
Test name
Test status
Simulation time 31853018 ps
CPU time 1.46 seconds
Started Sep 09 11:43:21 AM UTC 24
Finished Sep 09 11:43:24 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807254219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.2807254219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_genbits.1141333288
Short name T539
Test name
Test status
Simulation time 38472111 ps
CPU time 1.47 seconds
Started Sep 09 11:43:19 AM UTC 24
Finished Sep 09 11:43:22 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141333288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1141333288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_intr.3797537659
Short name T542
Test name
Test status
Simulation time 41520940 ps
CPU time 1.51 seconds
Started Sep 09 11:43:21 AM UTC 24
Finished Sep 09 11:43:24 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797537659 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.3797537659
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_smoke.4108638637
Short name T537
Test name
Test status
Simulation time 82956718 ps
CPU time 1.31 seconds
Started Sep 09 11:43:19 AM UTC 24
Finished Sep 09 11:43:22 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108638637 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.4108638637
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_stress_all.1534572854
Short name T554
Test name
Test status
Simulation time 1102617154 ps
CPU time 4.71 seconds
Started Sep 09 11:43:21 AM UTC 24
Finished Sep 09 11:43:28 AM UTC 24
Peak memory 227400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534572854 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1534572854
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.181252043
Short name T860
Test name
Test status
Simulation time 3865170818 ps
CPU time 94.79 seconds
Started Sep 09 11:43:21 AM UTC 24
Finished Sep 09 11:44:58 AM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=181252043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_
with_rand_reset.181252043
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_alert.3613145835
Short name T220
Test name
Test status
Simulation time 41241296 ps
CPU time 1.47 seconds
Started Sep 09 11:43:24 AM UTC 24
Finished Sep 09 11:43:26 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613145835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.3613145835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_alert_test.2028711410
Short name T550
Test name
Test status
Simulation time 38017513 ps
CPU time 1.11 seconds
Started Sep 09 11:43:25 AM UTC 24
Finished Sep 09 11:43:27 AM UTC 24
Peak memory 226532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028711410 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2028711410
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_disable.135908431
Short name T549
Test name
Test status
Simulation time 20431754 ps
CPU time 1.05 seconds
Started Sep 09 11:43:25 AM UTC 24
Finished Sep 09 11:43:27 AM UTC 24
Peak memory 225988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135908431 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.135908431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.951570308
Short name T553
Test name
Test status
Simulation time 54126006 ps
CPU time 1.61 seconds
Started Sep 09 11:43:25 AM UTC 24
Finished Sep 09 11:43:27 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951570308 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.951570308
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_err.938336225
Short name T552
Test name
Test status
Simulation time 20614642 ps
CPU time 1.61 seconds
Started Sep 09 11:43:25 AM UTC 24
Finished Sep 09 11:43:27 AM UTC 24
Peak memory 236636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938336225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 45.edn_err.938336225
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_genbits.1707554759
Short name T546
Test name
Test status
Simulation time 38633453 ps
CPU time 2 seconds
Started Sep 09 11:43:22 AM UTC 24
Finished Sep 09 11:43:25 AM UTC 24
Peak memory 226516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707554759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1707554759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_intr.2858728987
Short name T548
Test name
Test status
Simulation time 41986075 ps
CPU time 1.18 seconds
Started Sep 09 11:43:24 AM UTC 24
Finished Sep 09 11:43:26 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858728987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.2858728987
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_smoke.1599199608
Short name T544
Test name
Test status
Simulation time 58185292 ps
CPU time 1.1 seconds
Started Sep 09 11:43:22 AM UTC 24
Finished Sep 09 11:43:24 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599199608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.1599199608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/45.edn_stress_all.1415576336
Short name T556
Test name
Test status
Simulation time 661936939 ps
CPU time 5.34 seconds
Started Sep 09 11:43:22 AM UTC 24
Finished Sep 09 11:43:29 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415576336 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1415576336
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_alert.4068801470
Short name T557
Test name
Test status
Simulation time 200680654 ps
CPU time 1.73 seconds
Started Sep 09 11:43:26 AM UTC 24
Finished Sep 09 11:43:29 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068801470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.4068801470
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_alert_test.2154820117
Short name T564
Test name
Test status
Simulation time 221670819 ps
CPU time 1.28 seconds
Started Sep 09 11:43:28 AM UTC 24
Finished Sep 09 11:43:31 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154820117 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2154820117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_disable.3492416470
Short name T561
Test name
Test status
Simulation time 44077574 ps
CPU time 1.38 seconds
Started Sep 09 11:43:27 AM UTC 24
Finished Sep 09 11:43:30 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492416470 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3492416470
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.4182878055
Short name T562
Test name
Test status
Simulation time 32369579 ps
CPU time 1.64 seconds
Started Sep 09 11:43:27 AM UTC 24
Finished Sep 09 11:43:30 AM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182878055 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.4182878055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_err.2854414243
Short name T560
Test name
Test status
Simulation time 27619162 ps
CPU time 1.22 seconds
Started Sep 09 11:43:27 AM UTC 24
Finished Sep 09 11:43:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854414243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.2854414243
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_genbits.887802772
Short name T559
Test name
Test status
Simulation time 44273166 ps
CPU time 1.82 seconds
Started Sep 09 11:43:26 AM UTC 24
Finished Sep 09 11:43:29 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887802772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_genbits.887802772
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_intr.512025520
Short name T111
Test name
Test status
Simulation time 44690240 ps
CPU time 1.25 seconds
Started Sep 09 11:43:26 AM UTC 24
Finished Sep 09 11:43:28 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512025520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.512025520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_smoke.2068678802
Short name T551
Test name
Test status
Simulation time 16081486 ps
CPU time 1.21 seconds
Started Sep 09 11:43:25 AM UTC 24
Finished Sep 09 11:43:27 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068678802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.2068678802
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/46.edn_stress_all.40372096
Short name T555
Test name
Test status
Simulation time 69269005 ps
CPU time 1.16 seconds
Started Sep 09 11:43:26 AM UTC 24
Finished Sep 09 11:43:28 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40372096 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.40372096
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_alert.2783537313
Short name T302
Test name
Test status
Simulation time 188999137 ps
CPU time 1.64 seconds
Started Sep 09 11:43:30 AM UTC 24
Finished Sep 09 11:43:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783537313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.2783537313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_alert_test.3293679593
Short name T571
Test name
Test status
Simulation time 18647673 ps
CPU time 1.48 seconds
Started Sep 09 11:43:31 AM UTC 24
Finished Sep 09 11:43:34 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293679593 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3293679593
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_disable.4124173593
Short name T568
Test name
Test status
Simulation time 22928548 ps
CPU time 1.35 seconds
Started Sep 09 11:43:30 AM UTC 24
Finished Sep 09 11:43:32 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124173593 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4124173593
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.1322396009
Short name T569
Test name
Test status
Simulation time 29633596 ps
CPU time 1.61 seconds
Started Sep 09 11:43:30 AM UTC 24
Finished Sep 09 11:43:32 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322396009 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.1322396009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_err.466734831
Short name T567
Test name
Test status
Simulation time 57488234 ps
CPU time 1.25 seconds
Started Sep 09 11:43:30 AM UTC 24
Finished Sep 09 11:43:32 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466734831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.edn_err.466734831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_genbits.14100962
Short name T566
Test name
Test status
Simulation time 74411718 ps
CPU time 2.18 seconds
Started Sep 09 11:43:29 AM UTC 24
Finished Sep 09 11:43:32 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14100962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.edn_genbits.14100962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_intr.980991973
Short name T149
Test name
Test status
Simulation time 50375443 ps
CPU time 1.21 seconds
Started Sep 09 11:43:30 AM UTC 24
Finished Sep 09 11:43:32 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980991973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.980991973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_smoke.2891830150
Short name T565
Test name
Test status
Simulation time 100291262 ps
CPU time 1.33 seconds
Started Sep 09 11:43:28 AM UTC 24
Finished Sep 09 11:43:31 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891830150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.2891830150
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_stress_all.591050628
Short name T573
Test name
Test status
Simulation time 769793932 ps
CPU time 4.14 seconds
Started Sep 09 11:43:29 AM UTC 24
Finished Sep 09 11:43:34 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591050628 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.591050628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.3086473034
Short name T861
Test name
Test status
Simulation time 3760831024 ps
CPU time 87.61 seconds
Started Sep 09 11:43:29 AM UTC 24
Finished Sep 09 11:44:58 AM UTC 24
Peak memory 232032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3086473034 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all
_with_rand_reset.3086473034
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_alert.1350401461
Short name T575
Test name
Test status
Simulation time 25414705 ps
CPU time 1.76 seconds
Started Sep 09 11:43:32 AM UTC 24
Finished Sep 09 11:43:35 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350401461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.1350401461
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_alert_test.1130380028
Short name T577
Test name
Test status
Simulation time 27027929 ps
CPU time 1.24 seconds
Started Sep 09 11:43:34 AM UTC 24
Finished Sep 09 11:43:36 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130380028 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1130380028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_disable.574931448
Short name T576
Test name
Test status
Simulation time 39573042 ps
CPU time 1.22 seconds
Started Sep 09 11:43:34 AM UTC 24
Finished Sep 09 11:43:36 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574931448 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.574931448
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.3120357954
Short name T579
Test name
Test status
Simulation time 42484604 ps
CPU time 1.66 seconds
Started Sep 09 11:43:34 AM UTC 24
Finished Sep 09 11:43:36 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120357954 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.3120357954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_err.3567802071
Short name T235
Test name
Test status
Simulation time 19241948 ps
CPU time 1.32 seconds
Started Sep 09 11:43:32 AM UTC 24
Finished Sep 09 11:43:35 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567802071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.3567802071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_genbits.2563646518
Short name T361
Test name
Test status
Simulation time 64699276 ps
CPU time 1.61 seconds
Started Sep 09 11:43:31 AM UTC 24
Finished Sep 09 11:43:34 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563646518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2563646518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_intr.473250231
Short name T574
Test name
Test status
Simulation time 32254257 ps
CPU time 1.43 seconds
Started Sep 09 11:43:32 AM UTC 24
Finished Sep 09 11:43:35 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473250231 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.473250231
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_smoke.2695420775
Short name T570
Test name
Test status
Simulation time 22676089 ps
CPU time 1.32 seconds
Started Sep 09 11:43:31 AM UTC 24
Finished Sep 09 11:43:33 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695420775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.2695420775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/48.edn_stress_all.2190986356
Short name T585
Test name
Test status
Simulation time 312169644 ps
CPU time 6.43 seconds
Started Sep 09 11:43:31 AM UTC 24
Finished Sep 09 11:43:39 AM UTC 24
Peak memory 227676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190986356 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2190986356
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_alert.3284146306
Short name T318
Test name
Test status
Simulation time 34037987 ps
CPU time 1.83 seconds
Started Sep 09 11:43:35 AM UTC 24
Finished Sep 09 11:43:38 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284146306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.3284146306
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_alert_test.3920360399
Short name T583
Test name
Test status
Simulation time 33502246 ps
CPU time 1.03 seconds
Started Sep 09 11:43:36 AM UTC 24
Finished Sep 09 11:43:38 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920360399 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3920360399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_disable.2251702314
Short name T584
Test name
Test status
Simulation time 18011861 ps
CPU time 1.23 seconds
Started Sep 09 11:43:36 AM UTC 24
Finished Sep 09 11:43:38 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251702314 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2251702314
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.331885357
Short name T586
Test name
Test status
Simulation time 27593346 ps
CPU time 1.67 seconds
Started Sep 09 11:43:36 AM UTC 24
Finished Sep 09 11:43:39 AM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331885357 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.331885357
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_err.3703019188
Short name T154
Test name
Test status
Simulation time 20570063 ps
CPU time 1.27 seconds
Started Sep 09 11:43:35 AM UTC 24
Finished Sep 09 11:43:37 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703019188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.3703019188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_genbits.173259725
Short name T580
Test name
Test status
Simulation time 92207841 ps
CPU time 1.39 seconds
Started Sep 09 11:43:35 AM UTC 24
Finished Sep 09 11:43:37 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173259725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_genbits.173259725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_intr.626941703
Short name T581
Test name
Test status
Simulation time 22161387 ps
CPU time 1.54 seconds
Started Sep 09 11:43:35 AM UTC 24
Finished Sep 09 11:43:38 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626941703 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.626941703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_smoke.4030751396
Short name T558
Test name
Test status
Simulation time 32376834 ps
CPU time 1.29 seconds
Started Sep 09 11:43:34 AM UTC 24
Finished Sep 09 11:43:36 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030751396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.4030751396
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_stress_all.3707273923
Short name T578
Test name
Test status
Simulation time 68037276 ps
CPU time 1.19 seconds
Started Sep 09 11:43:35 AM UTC 24
Finished Sep 09 11:43:37 AM UTC 24
Peak memory 216124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707273923 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3707273923
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.1825216813
Short name T890
Test name
Test status
Simulation time 8513285750 ps
CPU time 91.67 seconds
Started Sep 09 11:43:35 AM UTC 24
Finished Sep 09 11:45:09 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1825216813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all
_with_rand_reset.1825216813
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_alert_test.2060850953
Short name T298
Test name
Test status
Simulation time 23899334 ps
CPU time 1.3 seconds
Started Sep 09 11:41:06 AM UTC 24
Finished Sep 09 11:41:09 AM UTC 24
Peak memory 226532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060850953 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2060850953
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_disable.11497702
Short name T43
Test name
Test status
Simulation time 10852971 ps
CPU time 1.29 seconds
Started Sep 09 11:41:05 AM UTC 24
Finished Sep 09 11:41:08 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11497702 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.11497702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_err.2258076702
Short name T8
Test name
Test status
Simulation time 22204577 ps
CPU time 1.67 seconds
Started Sep 09 11:41:05 AM UTC 24
Finished Sep 09 11:41:08 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258076702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.2258076702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_genbits.3018249272
Short name T143
Test name
Test status
Simulation time 49602669 ps
CPU time 2.68 seconds
Started Sep 09 11:41:04 AM UTC 24
Finished Sep 09 11:41:07 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018249272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3018249272
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_intr.3257496232
Short name T42
Test name
Test status
Simulation time 26786536 ps
CPU time 1.29 seconds
Started Sep 09 11:41:05 AM UTC 24
Finished Sep 09 11:41:08 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257496232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.3257496232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_regwen.2697462497
Short name T132
Test name
Test status
Simulation time 47472576 ps
CPU time 1.43 seconds
Started Sep 09 11:41:03 AM UTC 24
Finished Sep 09 11:41:05 AM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697462497 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2697462497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_smoke.3560093565
Short name T120
Test name
Test status
Simulation time 28669286 ps
CPU time 1.48 seconds
Started Sep 09 11:41:03 AM UTC 24
Finished Sep 09 11:41:05 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560093565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.3560093565
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/5.edn_stress_all.3289310219
Short name T225
Test name
Test status
Simulation time 18249731 ps
CPU time 1.49 seconds
Started Sep 09 11:41:05 AM UTC 24
Finished Sep 09 11:41:08 AM UTC 24
Peak memory 216224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289310219 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3289310219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/50.edn_alert.239132911
Short name T589
Test name
Test status
Simulation time 45378859 ps
CPU time 1.66 seconds
Started Sep 09 11:43:37 AM UTC 24
Finished Sep 09 11:43:40 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239132911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 50.edn_alert.239132911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/50.edn_err.491624553
Short name T222
Test name
Test status
Simulation time 19042486 ps
CPU time 1.65 seconds
Started Sep 09 11:43:37 AM UTC 24
Finished Sep 09 11:43:40 AM UTC 24
Peak memory 245788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491624553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 50.edn_err.491624553
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/50.edn_genbits.3508884950
Short name T587
Test name
Test status
Simulation time 45264641 ps
CPU time 1.64 seconds
Started Sep 09 11:43:36 AM UTC 24
Finished Sep 09 11:43:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508884950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3508884950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/51.edn_alert.88740977
Short name T590
Test name
Test status
Simulation time 30588703 ps
CPU time 1.79 seconds
Started Sep 09 11:43:38 AM UTC 24
Finished Sep 09 11:43:40 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88740977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 51.edn_alert.88740977
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/51.edn_err.2435497505
Short name T189
Test name
Test status
Simulation time 23337030 ps
CPU time 1.3 seconds
Started Sep 09 11:43:39 AM UTC 24
Finished Sep 09 11:43:41 AM UTC 24
Peak memory 230388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435497505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.2435497505
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/51.edn_genbits.3598372140
Short name T588
Test name
Test status
Simulation time 77926209 ps
CPU time 1.52 seconds
Started Sep 09 11:43:38 AM UTC 24
Finished Sep 09 11:43:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598372140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3598372140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/52.edn_alert.2206419134
Short name T591
Test name
Test status
Simulation time 27974268 ps
CPU time 1.6 seconds
Started Sep 09 11:43:39 AM UTC 24
Finished Sep 09 11:43:41 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206419134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 52.edn_alert.2206419134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/52.edn_err.1895427368
Short name T593
Test name
Test status
Simulation time 25917189 ps
CPU time 1.73 seconds
Started Sep 09 11:43:39 AM UTC 24
Finished Sep 09 11:43:42 AM UTC 24
Peak memory 244336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895427368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.1895427368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/52.edn_genbits.3465305446
Short name T592
Test name
Test status
Simulation time 180941380 ps
CPU time 1.75 seconds
Started Sep 09 11:43:39 AM UTC 24
Finished Sep 09 11:43:42 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465305446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3465305446
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/53.edn_alert.4062519089
Short name T187
Test name
Test status
Simulation time 81926441 ps
CPU time 1.75 seconds
Started Sep 09 11:43:40 AM UTC 24
Finished Sep 09 11:43:43 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062519089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.4062519089
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/53.edn_err.1363158675
Short name T595
Test name
Test status
Simulation time 29797518 ps
CPU time 1.54 seconds
Started Sep 09 11:43:40 AM UTC 24
Finished Sep 09 11:43:42 AM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363158675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.1363158675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/53.edn_genbits.1029925838
Short name T594
Test name
Test status
Simulation time 46598562 ps
CPU time 1.72 seconds
Started Sep 09 11:43:39 AM UTC 24
Finished Sep 09 11:43:42 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029925838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1029925838
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/54.edn_alert.918223139
Short name T319
Test name
Test status
Simulation time 26939727 ps
CPU time 1.78 seconds
Started Sep 09 11:43:40 AM UTC 24
Finished Sep 09 11:43:43 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918223139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 54.edn_alert.918223139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/54.edn_err.2899007624
Short name T598
Test name
Test status
Simulation time 91404339 ps
CPU time 1.54 seconds
Started Sep 09 11:43:41 AM UTC 24
Finished Sep 09 11:43:44 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899007624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.2899007624
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/54.edn_genbits.1806136740
Short name T596
Test name
Test status
Simulation time 175301754 ps
CPU time 2.06 seconds
Started Sep 09 11:43:40 AM UTC 24
Finished Sep 09 11:43:43 AM UTC 24
Peak memory 231424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806136740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1806136740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/55.edn_alert.3446008984
Short name T599
Test name
Test status
Simulation time 151540011 ps
CPU time 1.65 seconds
Started Sep 09 11:43:41 AM UTC 24
Finished Sep 09 11:43:44 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446008984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.3446008984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/55.edn_err.1536815674
Short name T597
Test name
Test status
Simulation time 127646280 ps
CPU time 1.12 seconds
Started Sep 09 11:43:41 AM UTC 24
Finished Sep 09 11:43:43 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536815674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.1536815674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/55.edn_genbits.4227549349
Short name T600
Test name
Test status
Simulation time 91358808 ps
CPU time 1.85 seconds
Started Sep 09 11:43:41 AM UTC 24
Finished Sep 09 11:43:44 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227549349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4227549349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/56.edn_alert.1320830725
Short name T601
Test name
Test status
Simulation time 79771575 ps
CPU time 1.64 seconds
Started Sep 09 11:43:42 AM UTC 24
Finished Sep 09 11:43:45 AM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320830725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.1320830725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/56.edn_err.968158118
Short name T168
Test name
Test status
Simulation time 26861894 ps
CPU time 1.69 seconds
Started Sep 09 11:43:42 AM UTC 24
Finished Sep 09 11:43:45 AM UTC 24
Peak memory 230392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968158118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 56.edn_err.968158118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/56.edn_genbits.1860496535
Short name T605
Test name
Test status
Simulation time 46696803 ps
CPU time 2.39 seconds
Started Sep 09 11:43:42 AM UTC 24
Finished Sep 09 11:43:46 AM UTC 24
Peak memory 229336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860496535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1860496535
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/57.edn_alert.4145095164
Short name T603
Test name
Test status
Simulation time 38171560 ps
CPU time 1.86 seconds
Started Sep 09 11:43:43 AM UTC 24
Finished Sep 09 11:43:45 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145095164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.4145095164
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/57.edn_err.487897564
Short name T606
Test name
Test status
Simulation time 18623564 ps
CPU time 1.55 seconds
Started Sep 09 11:43:44 AM UTC 24
Finished Sep 09 11:43:46 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487897564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 57.edn_err.487897564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/57.edn_genbits.2383875642
Short name T602
Test name
Test status
Simulation time 92872914 ps
CPU time 1.52 seconds
Started Sep 09 11:43:43 AM UTC 24
Finished Sep 09 11:43:45 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383875642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2383875642
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/58.edn_alert.2152470380
Short name T607
Test name
Test status
Simulation time 132173175 ps
CPU time 1.73 seconds
Started Sep 09 11:43:44 AM UTC 24
Finished Sep 09 11:43:47 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152470380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.2152470380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/58.edn_err.3787108861
Short name T227
Test name
Test status
Simulation time 20638996 ps
CPU time 1.34 seconds
Started Sep 09 11:43:44 AM UTC 24
Finished Sep 09 11:43:46 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787108861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.3787108861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/58.edn_genbits.2018661833
Short name T359
Test name
Test status
Simulation time 41777909 ps
CPU time 2.06 seconds
Started Sep 09 11:43:44 AM UTC 24
Finished Sep 09 11:43:47 AM UTC 24
Peak memory 231652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018661833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2018661833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/59.edn_alert.4201547119
Short name T609
Test name
Test status
Simulation time 56594357 ps
CPU time 1.65 seconds
Started Sep 09 11:43:45 AM UTC 24
Finished Sep 09 11:43:48 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201547119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.4201547119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/59.edn_err.2805514479
Short name T608
Test name
Test status
Simulation time 20379179 ps
CPU time 1.62 seconds
Started Sep 09 11:43:45 AM UTC 24
Finished Sep 09 11:43:48 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805514479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.2805514479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/59.edn_genbits.2675894909
Short name T337
Test name
Test status
Simulation time 81257988 ps
CPU time 2.63 seconds
Started Sep 09 11:43:45 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675894909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2675894909
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_alert.2713597540
Short name T137
Test name
Test status
Simulation time 25168226 ps
CPU time 1.31 seconds
Started Sep 09 11:41:09 AM UTC 24
Finished Sep 09 11:41:13 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713597540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.2713597540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_alert_test.3731767373
Short name T365
Test name
Test status
Simulation time 23453253 ps
CPU time 1.32 seconds
Started Sep 09 11:41:10 AM UTC 24
Finished Sep 09 11:41:13 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731767373 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3731767373
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_disable.2046145127
Short name T82
Test name
Test status
Simulation time 13981944 ps
CPU time 1.42 seconds
Started Sep 09 11:41:10 AM UTC 24
Finished Sep 09 11:41:13 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046145127 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2046145127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2464062596
Short name T87
Test name
Test status
Simulation time 156238886 ps
CPU time 1.43 seconds
Started Sep 09 11:41:10 AM UTC 24
Finished Sep 09 11:41:13 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464062596 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2464062596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_err.1435728684
Short name T144
Test name
Test status
Simulation time 21567075 ps
CPU time 1.46 seconds
Started Sep 09 11:41:09 AM UTC 24
Finished Sep 09 11:41:12 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435728684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.1435728684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_genbits.3682777381
Short name T125
Test name
Test status
Simulation time 71339707 ps
CPU time 1.23 seconds
Started Sep 09 11:41:09 AM UTC 24
Finished Sep 09 11:41:11 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682777381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3682777381
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_intr.1670670920
Short name T121
Test name
Test status
Simulation time 38161747 ps
CPU time 1.36 seconds
Started Sep 09 11:41:09 AM UTC 24
Finished Sep 09 11:41:11 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670670920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.1670670920
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_regwen.2771924465
Short name T299
Test name
Test status
Simulation time 17117326 ps
CPU time 1.53 seconds
Started Sep 09 11:41:08 AM UTC 24
Finished Sep 09 11:41:10 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771924465 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.2771924465
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_smoke.168349329
Short name T123
Test name
Test status
Simulation time 34277926 ps
CPU time 1.32 seconds
Started Sep 09 11:41:06 AM UTC 24
Finished Sep 09 11:41:09 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168349329 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.edn_smoke.168349329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_stress_all.605159555
Short name T119
Test name
Test status
Simulation time 185814731 ps
CPU time 4.39 seconds
Started Sep 09 11:41:09 AM UTC 24
Finished Sep 09 11:41:14 AM UTC 24
Peak memory 229372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605159555 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.605159555
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.4132715502
Short name T248
Test name
Test status
Simulation time 15432791452 ps
CPU time 93.4 seconds
Started Sep 09 11:41:09 AM UTC 24
Finished Sep 09 11:42:44 AM UTC 24
Peak memory 233888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4132715502 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_
with_rand_reset.4132715502
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/60.edn_alert.3326383244
Short name T242
Test name
Test status
Simulation time 25359154 ps
CPU time 1.65 seconds
Started Sep 09 11:43:46 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326383244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.3326383244
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/60.edn_err.1187069861
Short name T612
Test name
Test status
Simulation time 24305079 ps
CPU time 1.35 seconds
Started Sep 09 11:43:46 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187069861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.1187069861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/60.edn_genbits.3840277498
Short name T610
Test name
Test status
Simulation time 90986014 ps
CPU time 2.08 seconds
Started Sep 09 11:43:45 AM UTC 24
Finished Sep 09 11:43:48 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840277498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3840277498
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/61.edn_alert.4003308203
Short name T613
Test name
Test status
Simulation time 145304925 ps
CPU time 1.49 seconds
Started Sep 09 11:43:46 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003308203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.4003308203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/61.edn_err.619279529
Short name T611
Test name
Test status
Simulation time 36967593 ps
CPU time 1.23 seconds
Started Sep 09 11:43:46 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619279529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 61.edn_err.619279529
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/61.edn_genbits.725741104
Short name T614
Test name
Test status
Simulation time 49079741 ps
CPU time 1.74 seconds
Started Sep 09 11:43:46 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725741104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 61.edn_genbits.725741104
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/62.edn_alert.3380161891
Short name T616
Test name
Test status
Simulation time 61218840 ps
CPU time 1.58 seconds
Started Sep 09 11:43:48 AM UTC 24
Finished Sep 09 11:43:50 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380161891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 62.edn_alert.3380161891
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/62.edn_err.2104370098
Short name T617
Test name
Test status
Simulation time 19105047 ps
CPU time 1.67 seconds
Started Sep 09 11:43:48 AM UTC 24
Finished Sep 09 11:43:50 AM UTC 24
Peak memory 236848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104370098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.2104370098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/62.edn_genbits.1693572153
Short name T615
Test name
Test status
Simulation time 37688292 ps
CPU time 1.95 seconds
Started Sep 09 11:43:46 AM UTC 24
Finished Sep 09 11:43:49 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693572153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1693572153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/63.edn_alert.1969644001
Short name T165
Test name
Test status
Simulation time 26812081 ps
CPU time 1.81 seconds
Started Sep 09 11:43:48 AM UTC 24
Finished Sep 09 11:43:51 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969644001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.1969644001
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/63.edn_err.1692186947
Short name T619
Test name
Test status
Simulation time 34118226 ps
CPU time 1.27 seconds
Started Sep 09 11:43:49 AM UTC 24
Finished Sep 09 11:43:51 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692186947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.1692186947
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/63.edn_genbits.2578181181
Short name T618
Test name
Test status
Simulation time 101985610 ps
CPU time 1.83 seconds
Started Sep 09 11:43:48 AM UTC 24
Finished Sep 09 11:43:50 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578181181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2578181181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/64.edn_alert.144517106
Short name T622
Test name
Test status
Simulation time 83601798 ps
CPU time 1.75 seconds
Started Sep 09 11:43:49 AM UTC 24
Finished Sep 09 11:43:52 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144517106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 64.edn_alert.144517106
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/64.edn_err.2283790095
Short name T621
Test name
Test status
Simulation time 33229485 ps
CPU time 1.39 seconds
Started Sep 09 11:43:49 AM UTC 24
Finished Sep 09 11:43:51 AM UTC 24
Peak memory 245784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283790095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.2283790095
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/64.edn_genbits.1327165595
Short name T620
Test name
Test status
Simulation time 49590448 ps
CPU time 1.37 seconds
Started Sep 09 11:43:49 AM UTC 24
Finished Sep 09 11:43:51 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327165595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1327165595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/65.edn_alert.4146513489
Short name T623
Test name
Test status
Simulation time 81202330 ps
CPU time 1.19 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:52 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146513489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.4146513489
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/65.edn_err.3492445454
Short name T624
Test name
Test status
Simulation time 25374177 ps
CPU time 1.29 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:52 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492445454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.3492445454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/65.edn_genbits.1263152291
Short name T628
Test name
Test status
Simulation time 83020223 ps
CPU time 1.91 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:53 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263152291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1263152291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/66.edn_alert.1130916227
Short name T627
Test name
Test status
Simulation time 80405910 ps
CPU time 1.68 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:53 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130916227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.1130916227
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/66.edn_err.3378757423
Short name T626
Test name
Test status
Simulation time 25675391 ps
CPU time 1.37 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:53 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378757423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.3378757423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/67.edn_alert.1821180725
Short name T191
Test name
Test status
Simulation time 47075266 ps
CPU time 1.85 seconds
Started Sep 09 11:43:52 AM UTC 24
Finished Sep 09 11:43:54 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821180725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.1821180725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/67.edn_err.1612285558
Short name T631
Test name
Test status
Simulation time 17982571 ps
CPU time 1.57 seconds
Started Sep 09 11:43:52 AM UTC 24
Finished Sep 09 11:43:54 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612285558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.1612285558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/67.edn_genbits.2285001557
Short name T629
Test name
Test status
Simulation time 67337686 ps
CPU time 2.54 seconds
Started Sep 09 11:43:50 AM UTC 24
Finished Sep 09 11:43:54 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285001557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2285001557
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/68.edn_alert.383146527
Short name T240
Test name
Test status
Simulation time 71505136 ps
CPU time 1.57 seconds
Started Sep 09 11:43:52 AM UTC 24
Finished Sep 09 11:43:54 AM UTC 24
Peak memory 228244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383146527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 68.edn_alert.383146527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/68.edn_err.1096522755
Short name T630
Test name
Test status
Simulation time 21454030 ps
CPU time 1.3 seconds
Started Sep 09 11:43:52 AM UTC 24
Finished Sep 09 11:43:54 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096522755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 68.edn_err.1096522755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/68.edn_genbits.3542518654
Short name T632
Test name
Test status
Simulation time 43707346 ps
CPU time 2.29 seconds
Started Sep 09 11:43:52 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 229296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542518654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3542518654
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/69.edn_alert.3159352975
Short name T634
Test name
Test status
Simulation time 41208458 ps
CPU time 1.42 seconds
Started Sep 09 11:43:53 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159352975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.3159352975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/69.edn_err.3201940250
Short name T635
Test name
Test status
Simulation time 37239445 ps
CPU time 1.53 seconds
Started Sep 09 11:43:53 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201940250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.3201940250
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/69.edn_genbits.4266270124
Short name T633
Test name
Test status
Simulation time 43279531 ps
CPU time 2.4 seconds
Started Sep 09 11:43:52 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266270124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4266270124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_alert.1560783254
Short name T53
Test name
Test status
Simulation time 65592486 ps
CPU time 1.89 seconds
Started Sep 09 11:41:14 AM UTC 24
Finished Sep 09 11:41:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560783254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.1560783254
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_alert_test.1035145065
Short name T367
Test name
Test status
Simulation time 148610843 ps
CPU time 0.96 seconds
Started Sep 09 11:41:14 AM UTC 24
Finished Sep 09 11:41:16 AM UTC 24
Peak memory 217168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035145065 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1035145065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_disable.3572478613
Short name T47
Test name
Test status
Simulation time 21839727 ps
CPU time 1.21 seconds
Started Sep 09 11:41:14 AM UTC 24
Finished Sep 09 11:41:16 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572478613 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3572478613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_err.2858755112
Short name T138
Test name
Test status
Simulation time 63847572 ps
CPU time 1.26 seconds
Started Sep 09 11:41:14 AM UTC 24
Finished Sep 09 11:41:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858755112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.2858755112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_intr.1157551349
Short name T46
Test name
Test status
Simulation time 20276465 ps
CPU time 1.66 seconds
Started Sep 09 11:41:13 AM UTC 24
Finished Sep 09 11:41:16 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157551349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.1157551349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_regwen.120985020
Short name T323
Test name
Test status
Simulation time 24595022 ps
CPU time 1.34 seconds
Started Sep 09 11:41:11 AM UTC 24
Finished Sep 09 11:41:14 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120985020 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_regwen.120985020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_smoke.3124982929
Short name T366
Test name
Test status
Simulation time 50093386 ps
CPU time 1.43 seconds
Started Sep 09 11:41:10 AM UTC 24
Finished Sep 09 11:41:13 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124982929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.3124982929
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/7.edn_stress_all.2052217003
Short name T122
Test name
Test status
Simulation time 163933944 ps
CPU time 3.22 seconds
Started Sep 09 11:41:13 AM UTC 24
Finished Sep 09 11:41:17 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052217003 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2052217003
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/70.edn_alert.1394325158
Short name T636
Test name
Test status
Simulation time 85431787 ps
CPU time 1.41 seconds
Started Sep 09 11:43:53 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394325158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 70.edn_alert.1394325158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/70.edn_err.1509593994
Short name T197
Test name
Test status
Simulation time 18580343 ps
CPU time 1.17 seconds
Started Sep 09 11:43:54 AM UTC 24
Finished Sep 09 11:43:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509593994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.1509593994
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/70.edn_genbits.3439881929
Short name T332
Test name
Test status
Simulation time 42013522 ps
CPU time 1.29 seconds
Started Sep 09 11:43:53 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439881929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3439881929
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/71.edn_alert.1659854006
Short name T637
Test name
Test status
Simulation time 71066392 ps
CPU time 1.35 seconds
Started Sep 09 11:43:54 AM UTC 24
Finished Sep 09 11:43:57 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659854006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.1659854006
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/71.edn_err.1882665852
Short name T639
Test name
Test status
Simulation time 30101253 ps
CPU time 1.44 seconds
Started Sep 09 11:43:54 AM UTC 24
Finished Sep 09 11:43:57 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882665852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.1882665852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/71.edn_genbits.3704700029
Short name T638
Test name
Test status
Simulation time 54295405 ps
CPU time 1.43 seconds
Started Sep 09 11:43:54 AM UTC 24
Finished Sep 09 11:43:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704700029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3704700029
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/72.edn_alert.1474928605
Short name T642
Test name
Test status
Simulation time 24733431 ps
CPU time 1.65 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474928605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.1474928605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/72.edn_err.3727898130
Short name T205
Test name
Test status
Simulation time 41131589 ps
CPU time 1.46 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:58 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727898130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.3727898130
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/72.edn_genbits.2060808675
Short name T640
Test name
Test status
Simulation time 53671611 ps
CPU time 1.54 seconds
Started Sep 09 11:43:54 AM UTC 24
Finished Sep 09 11:43:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060808675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2060808675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/73.edn_alert.389624041
Short name T303
Test name
Test status
Simulation time 27700591 ps
CPU time 1.42 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389624041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 73.edn_alert.389624041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/73.edn_err.1864770972
Short name T641
Test name
Test status
Simulation time 20801855 ps
CPU time 1.3 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:58 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864770972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.1864770972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/73.edn_genbits.2376568673
Short name T334
Test name
Test status
Simulation time 43386701 ps
CPU time 2.24 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376568673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2376568673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/74.edn_alert.1339480215
Short name T644
Test name
Test status
Simulation time 31297191 ps
CPU time 1.54 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339480215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.1339480215
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/74.edn_err.1725115849
Short name T217
Test name
Test status
Simulation time 18744467 ps
CPU time 1.55 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725115849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.1725115849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/74.edn_genbits.4029408538
Short name T643
Test name
Test status
Simulation time 69166261 ps
CPU time 1.48 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029408538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4029408538
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/75.edn_alert.1758645995
Short name T645
Test name
Test status
Simulation time 27354035 ps
CPU time 1.56 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758645995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 75.edn_alert.1758645995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/75.edn_err.2023459573
Short name T153
Test name
Test status
Simulation time 30350535 ps
CPU time 0.89 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:58 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023459573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.2023459573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/75.edn_genbits.3648258739
Short name T646
Test name
Test status
Simulation time 40667490 ps
CPU time 1.9 seconds
Started Sep 09 11:43:56 AM UTC 24
Finished Sep 09 11:43:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648258739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3648258739
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/76.edn_alert.1260651709
Short name T582
Test name
Test status
Simulation time 147160279 ps
CPU time 1.57 seconds
Started Sep 09 11:43:57 AM UTC 24
Finished Sep 09 11:44:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260651709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.1260651709
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/76.edn_err.1288318652
Short name T160
Test name
Test status
Simulation time 29413460 ps
CPU time 1.27 seconds
Started Sep 09 11:43:57 AM UTC 24
Finished Sep 09 11:44:00 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288318652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.1288318652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/76.edn_genbits.116616553
Short name T647
Test name
Test status
Simulation time 25514750 ps
CPU time 1.4 seconds
Started Sep 09 11:43:57 AM UTC 24
Finished Sep 09 11:44:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116616553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 76.edn_genbits.116616553
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/77.edn_err.3508102821
Short name T155
Test name
Test status
Simulation time 34071937 ps
CPU time 1.14 seconds
Started Sep 09 11:43:58 AM UTC 24
Finished Sep 09 11:44:00 AM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508102821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.3508102821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/77.edn_genbits.2805962765
Short name T648
Test name
Test status
Simulation time 37263151 ps
CPU time 1.83 seconds
Started Sep 09 11:43:58 AM UTC 24
Finished Sep 09 11:44:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805962765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2805962765
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/78.edn_alert.2691734804
Short name T275
Test name
Test status
Simulation time 30199666 ps
CPU time 1.23 seconds
Started Sep 09 11:43:58 AM UTC 24
Finished Sep 09 11:44:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691734804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 78.edn_alert.2691734804
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/78.edn_err.1398504639
Short name T649
Test name
Test status
Simulation time 49361902 ps
CPU time 1.44 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:02 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398504639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.1398504639
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/78.edn_genbits.1932241034
Short name T348
Test name
Test status
Simulation time 346261860 ps
CPU time 3.53 seconds
Started Sep 09 11:43:58 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932241034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1932241034
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/79.edn_alert.915329430
Short name T192
Test name
Test status
Simulation time 31655864 ps
CPU time 2.03 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915329430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 79.edn_alert.915329430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/79.edn_err.2223451785
Short name T651
Test name
Test status
Simulation time 22640171 ps
CPU time 1.6 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223451785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.2223451785
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/79.edn_genbits.2416816733
Short name T654
Test name
Test status
Simulation time 251165924 ps
CPU time 3.71 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416816733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2416816733
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_alert_test.2128477431
Short name T368
Test name
Test status
Simulation time 66670534 ps
CPU time 1.25 seconds
Started Sep 09 11:41:18 AM UTC 24
Finished Sep 09 11:41:20 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128477431 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2128477431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_disable.3419470794
Short name T48
Test name
Test status
Simulation time 12690711 ps
CPU time 1.39 seconds
Started Sep 09 11:41:18 AM UTC 24
Finished Sep 09 11:41:20 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419470794 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3419470794
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.3039733568
Short name T73
Test name
Test status
Simulation time 111613417 ps
CPU time 1.51 seconds
Started Sep 09 11:41:18 AM UTC 24
Finished Sep 09 11:41:20 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039733568 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.3039733568
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_err.3166743145
Short name T130
Test name
Test status
Simulation time 20435068 ps
CPU time 1.46 seconds
Started Sep 09 11:41:18 AM UTC 24
Finished Sep 09 11:41:20 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166743145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.3166743145
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_regwen.3983996407
Short name T322
Test name
Test status
Simulation time 22910788 ps
CPU time 1.44 seconds
Started Sep 09 11:41:15 AM UTC 24
Finished Sep 09 11:41:18 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983996407 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.3983996407
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_smoke.2940833743
Short name T127
Test name
Test status
Simulation time 76302820 ps
CPU time 1.38 seconds
Started Sep 09 11:41:14 AM UTC 24
Finished Sep 09 11:41:17 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940833743 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.2940833743
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/8.edn_stress_all.2464267714
Short name T131
Test name
Test status
Simulation time 325634146 ps
CPU time 6.42 seconds
Started Sep 09 11:41:16 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 231772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464267714 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2464267714
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/80.edn_alert.756594571
Short name T304
Test name
Test status
Simulation time 70069981 ps
CPU time 1.21 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:02 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756594571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 80.edn_alert.756594571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/80.edn_err.1211359809
Short name T213
Test name
Test status
Simulation time 54295526 ps
CPU time 1.22 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:02 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211359809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.1211359809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/80.edn_genbits.1402408036
Short name T350
Test name
Test status
Simulation time 35043243 ps
CPU time 1.93 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402408036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1402408036
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/81.edn_alert.1107313856
Short name T276
Test name
Test status
Simulation time 51036107 ps
CPU time 1.51 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107313856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 81.edn_alert.1107313856
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/81.edn_err.1743668095
Short name T169
Test name
Test status
Simulation time 24638840 ps
CPU time 1.49 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743668095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.1743668095
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/81.edn_genbits.1366563505
Short name T650
Test name
Test status
Simulation time 65531964 ps
CPU time 1.42 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366563505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1366563505
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/82.edn_alert.2578015836
Short name T208
Test name
Test status
Simulation time 39961349 ps
CPU time 1.14 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578015836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.2578015836
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/82.edn_err.552751257
Short name T200
Test name
Test status
Simulation time 21201648 ps
CPU time 1.53 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552751257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 82.edn_err.552751257
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/82.edn_genbits.3559823776
Short name T652
Test name
Test status
Simulation time 78907356 ps
CPU time 1.59 seconds
Started Sep 09 11:44:00 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559823776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3559823776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/83.edn_alert.436268830
Short name T657
Test name
Test status
Simulation time 25623706 ps
CPU time 1.62 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436268830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 83.edn_alert.436268830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/83.edn_err.3509187098
Short name T653
Test name
Test status
Simulation time 26483936 ps
CPU time 1.04 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509187098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.3509187098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/83.edn_genbits.1067822778
Short name T656
Test name
Test status
Simulation time 46597453 ps
CPU time 1.59 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067822778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1067822778
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/84.edn_alert.3198354137
Short name T212
Test name
Test status
Simulation time 26259514 ps
CPU time 1.49 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198354137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.3198354137
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/84.edn_err.401867082
Short name T659
Test name
Test status
Simulation time 29205189 ps
CPU time 1.2 seconds
Started Sep 09 11:44:03 AM UTC 24
Finished Sep 09 11:44:06 AM UTC 24
Peak memory 246088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401867082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 84.edn_err.401867082
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/84.edn_genbits.741361824
Short name T655
Test name
Test status
Simulation time 50264612 ps
CPU time 1.43 seconds
Started Sep 09 11:44:02 AM UTC 24
Finished Sep 09 11:44:05 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741361824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 84.edn_genbits.741361824
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/85.edn_alert.2006422731
Short name T661
Test name
Test status
Simulation time 116704599 ps
CPU time 1.21 seconds
Started Sep 09 11:44:03 AM UTC 24
Finished Sep 09 11:44:06 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006422731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.2006422731
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/85.edn_err.2730492167
Short name T662
Test name
Test status
Simulation time 21415210 ps
CPU time 1.27 seconds
Started Sep 09 11:44:04 AM UTC 24
Finished Sep 09 11:44:07 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730492167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.2730492167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/85.edn_genbits.2921758837
Short name T660
Test name
Test status
Simulation time 58226478 ps
CPU time 1.22 seconds
Started Sep 09 11:44:03 AM UTC 24
Finished Sep 09 11:44:06 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921758837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2921758837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/86.edn_alert.781278860
Short name T170
Test name
Test status
Simulation time 154360730 ps
CPU time 1.79 seconds
Started Sep 09 11:44:04 AM UTC 24
Finished Sep 09 11:44:08 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781278860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 86.edn_alert.781278860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/86.edn_err.1113090257
Short name T663
Test name
Test status
Simulation time 24121065 ps
CPU time 1.19 seconds
Started Sep 09 11:44:04 AM UTC 24
Finished Sep 09 11:44:07 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113090257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.1113090257
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/86.edn_genbits.3534741120
Short name T694
Test name
Test status
Simulation time 1160880465 ps
CPU time 7.63 seconds
Started Sep 09 11:44:04 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 231928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534741120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3534741120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/87.edn_alert.1600931946
Short name T665
Test name
Test status
Simulation time 27908921 ps
CPU time 1.41 seconds
Started Sep 09 11:44:05 AM UTC 24
Finished Sep 09 11:44:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600931946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.1600931946
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/87.edn_err.507093824
Short name T214
Test name
Test status
Simulation time 26250898 ps
CPU time 0.98 seconds
Started Sep 09 11:44:05 AM UTC 24
Finished Sep 09 11:44:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507093824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 87.edn_err.507093824
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/87.edn_genbits.3983215010
Short name T362
Test name
Test status
Simulation time 426921213 ps
CPU time 4.64 seconds
Started Sep 09 11:44:05 AM UTC 24
Finished Sep 09 11:44:11 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983215010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3983215010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/88.edn_alert.4146313051
Short name T666
Test name
Test status
Simulation time 116039619 ps
CPU time 1.47 seconds
Started Sep 09 11:44:05 AM UTC 24
Finished Sep 09 11:44:08 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146313051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.4146313051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/88.edn_err.4253916877
Short name T669
Test name
Test status
Simulation time 28587836 ps
CPU time 1.2 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:08 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253916877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.4253916877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/88.edn_genbits.2352072871
Short name T664
Test name
Test status
Simulation time 159956936 ps
CPU time 1.33 seconds
Started Sep 09 11:44:05 AM UTC 24
Finished Sep 09 11:44:07 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352072871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2352072871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/89.edn_alert.1778616849
Short name T670
Test name
Test status
Simulation time 30940903 ps
CPU time 1.34 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:08 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778616849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.1778616849
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/89.edn_err.2253688644
Short name T667
Test name
Test status
Simulation time 62024646 ps
CPU time 1.07 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:08 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253688644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 89.edn_err.2253688644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/89.edn_genbits.917385074
Short name T672
Test name
Test status
Simulation time 185823232 ps
CPU time 1.59 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917385074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 89.edn_genbits.917385074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_alert.1132241852
Short name T60
Test name
Test status
Simulation time 49986354 ps
CPU time 1.68 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132241852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.1132241852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_alert_test.1294053739
Short name T370
Test name
Test status
Simulation time 30317366 ps
CPU time 1.43 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294053739 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1294053739
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_disable.631286462
Short name T74
Test name
Test status
Simulation time 64575979 ps
CPU time 1.36 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631286462 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.631286462
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.2171554810
Short name T184
Test name
Test status
Simulation time 66357197 ps
CPU time 1.59 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171554810 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.2171554810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_err.2444014235
Short name T320
Test name
Test status
Simulation time 33252066 ps
CPU time 1.36 seconds
Started Sep 09 11:41:22 AM UTC 24
Finished Sep 09 11:41:24 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444014235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.2444014235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_genbits.4008116408
Short name T12
Test name
Test status
Simulation time 118193871 ps
CPU time 1.8 seconds
Started Sep 09 11:41:19 AM UTC 24
Finished Sep 09 11:41:22 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008116408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4008116408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_intr.4097475841
Short name T65
Test name
Test status
Simulation time 22527902 ps
CPU time 1.6 seconds
Started Sep 09 11:41:20 AM UTC 24
Finished Sep 09 11:41:23 AM UTC 24
Peak memory 236696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097475841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.4097475841
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_regwen.1941750414
Short name T269
Test name
Test status
Simulation time 18549770 ps
CPU time 1.54 seconds
Started Sep 09 11:41:18 AM UTC 24
Finished Sep 09 11:41:21 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941750414 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.1941750414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_smoke.1429322980
Short name T369
Test name
Test status
Simulation time 27888214 ps
CPU time 1.42 seconds
Started Sep 09 11:41:18 AM UTC 24
Finished Sep 09 11:41:20 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429322980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.1429322980
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_stress_all.3914204184
Short name T126
Test name
Test status
Simulation time 239245406 ps
CPU time 2.33 seconds
Started Sep 09 11:41:19 AM UTC 24
Finished Sep 09 11:41:22 AM UTC 24
Peak memory 231640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914204184 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3914204184
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.3663936892
Short name T243
Test name
Test status
Simulation time 2225748830 ps
CPU time 29.7 seconds
Started Sep 09 11:41:20 AM UTC 24
Finished Sep 09 11:41:51 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3663936892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.3663936892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/90.edn_alert.3572397359
Short name T671
Test name
Test status
Simulation time 47687381 ps
CPU time 1.32 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:09 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572397359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.3572397359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/90.edn_err.933073884
Short name T668
Test name
Test status
Simulation time 30718061 ps
CPU time 0.97 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:08 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933073884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 90.edn_err.933073884
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/90.edn_genbits.3886397291
Short name T674
Test name
Test status
Simulation time 39376004 ps
CPU time 1.71 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:09 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886397291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3886397291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/91.edn_alert.2241098671
Short name T675
Test name
Test status
Simulation time 250071663 ps
CPU time 1.58 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241098671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.2241098671
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/91.edn_err.2003069635
Short name T676
Test name
Test status
Simulation time 35182537 ps
CPU time 1.2 seconds
Started Sep 09 11:44:07 AM UTC 24
Finished Sep 09 11:44:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003069635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 91.edn_err.2003069635
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/91.edn_genbits.100462868
Short name T673
Test name
Test status
Simulation time 34579909 ps
CPU time 1.64 seconds
Started Sep 09 11:44:06 AM UTC 24
Finished Sep 09 11:44:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100462868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 91.edn_genbits.100462868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/92.edn_alert.304065122
Short name T677
Test name
Test status
Simulation time 28938967 ps
CPU time 1.33 seconds
Started Sep 09 11:44:07 AM UTC 24
Finished Sep 09 11:44:10 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304065122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 92.edn_alert.304065122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/92.edn_err.3269318368
Short name T679
Test name
Test status
Simulation time 29366772 ps
CPU time 1.31 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:11 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269318368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.3269318368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/92.edn_genbits.3674975802
Short name T360
Test name
Test status
Simulation time 101857596 ps
CPU time 1.67 seconds
Started Sep 09 11:44:07 AM UTC 24
Finished Sep 09 11:44:10 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674975802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3674975802
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/93.edn_alert.2768442734
Short name T166
Test name
Test status
Simulation time 35841114 ps
CPU time 1.65 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:11 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768442734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.2768442734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/93.edn_err.1078524269
Short name T678
Test name
Test status
Simulation time 28580476 ps
CPU time 1.1 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:11 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078524269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.1078524269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/93.edn_genbits.711582629
Short name T684
Test name
Test status
Simulation time 49036519 ps
CPU time 2.16 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:12 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711582629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 93.edn_genbits.711582629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/94.edn_alert.1627043219
Short name T682
Test name
Test status
Simulation time 45676273 ps
CPU time 1.58 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:12 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627043219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.1627043219
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/94.edn_err.1474028987
Short name T680
Test name
Test status
Simulation time 30904764 ps
CPU time 1.23 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474028987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.1474028987
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/94.edn_genbits.3745416875
Short name T681
Test name
Test status
Simulation time 79228229 ps
CPU time 1.58 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:11 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745416875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3745416875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/95.edn_alert.3381025265
Short name T683
Test name
Test status
Simulation time 61524200 ps
CPU time 1.75 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:12 AM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381025265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.3381025265
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/95.edn_genbits.2549153289
Short name T686
Test name
Test status
Simulation time 37256248 ps
CPU time 1.9 seconds
Started Sep 09 11:44:09 AM UTC 24
Finished Sep 09 11:44:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549153289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2549153289
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/96.edn_alert.183756638
Short name T690
Test name
Test status
Simulation time 23538314 ps
CPU time 1.42 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183756638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 96.edn_alert.183756638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/96.edn_err.674037388
Short name T687
Test name
Test status
Simulation time 27953778 ps
CPU time 1.17 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:12 AM UTC 24
Peak memory 230172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674037388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 96.edn_err.674037388
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/96.edn_genbits.2456995572
Short name T692
Test name
Test status
Simulation time 51625584 ps
CPU time 1.89 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 228060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456995572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2456995572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/97.edn_alert.793533149
Short name T688
Test name
Test status
Simulation time 47799840 ps
CPU time 1.19 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793533149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 97.edn_alert.793533149
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/97.edn_err.464309295
Short name T173
Test name
Test status
Simulation time 31888772 ps
CPU time 1.32 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464309295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 97.edn_err.464309295
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/97.edn_genbits.1173037037
Short name T689
Test name
Test status
Simulation time 231974260 ps
CPU time 1.32 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173037037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1173037037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/98.edn_alert.4220647900
Short name T691
Test name
Test status
Simulation time 111583524 ps
CPU time 1.5 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220647900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.4220647900
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/98.edn_err.3430125419
Short name T174
Test name
Test status
Simulation time 30955678 ps
CPU time 1.34 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:13 AM UTC 24
Peak memory 244036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430125419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.3430125419
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/98.edn_genbits.973480262
Short name T338
Test name
Test status
Simulation time 102901019 ps
CPU time 2.73 seconds
Started Sep 09 11:44:10 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973480262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 98.edn_genbits.973480262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/99.edn_alert.3897789454
Short name T695
Test name
Test status
Simulation time 81146955 ps
CPU time 1.31 seconds
Started Sep 09 11:44:12 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897789454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 99.edn_alert.3897789454
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/99.edn_err.3006358930
Short name T698
Test name
Test status
Simulation time 58446267 ps
CPU time 1.48 seconds
Started Sep 09 11:44:12 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006358930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.3006358930
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/default/99.edn_genbits.769701066
Short name T693
Test name
Test status
Simulation time 54981553 ps
CPU time 1.06 seconds
Started Sep 09 11:44:12 AM UTC 24
Finished Sep 09 11:44:14 AM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769701066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 99.edn_genbits.769701066
Directory /workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/99.edn_genbits/latest
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