Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3698 1 T6 27 T60 8 T61 36
all_values[1] 3698 1 T6 27 T60 8 T61 36



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3837 1 T6 31 T60 11 T61 41
auto[1] 3559 1 T6 23 T60 5 T61 31



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2900 1 T6 17 T60 6 T61 28
auto[1] 4496 1 T6 37 T60 10 T61 44



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4376 1 T6 29 T60 10 T61 45
auto[1] 3020 1 T6 25 T60 6 T61 27



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 703 1 T6 5 T60 3 T61 3
all_values[0] auto[0] auto[0] auto[1] 394 1 T6 3 T61 7 T112 2
all_values[0] auto[0] auto[1] auto[0] 722 1 T6 6 T61 5 T112 1
all_values[0] auto[0] auto[1] auto[1] 347 1 T6 2 T60 2 T61 5
all_values[0] auto[1] auto[0] auto[1] 806 1 T6 4 T60 2 T61 11
all_values[0] auto[1] auto[1] auto[1] 726 1 T6 7 T60 1 T61 5
all_values[1] auto[0] auto[0] auto[0] 758 1 T6 4 T60 2 T61 10
all_values[1] auto[0] auto[0] auto[1] 376 1 T6 3 T60 2 T61 3
all_values[1] auto[0] auto[1] auto[0] 717 1 T6 2 T60 1 T61 10
all_values[1] auto[0] auto[1] auto[1] 359 1 T6 4 T61 2 T112 2
all_values[1] auto[1] auto[0] auto[1] 800 1 T6 12 T60 2 T61 7
all_values[1] auto[1] auto[1] auto[1] 688 1 T6 2 T60 1 T61 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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