Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

3698

1

T6

27

T60

8

T61

36

all_values[1]

3698

1

T6

27

T60

8

T61

36

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3837

1

T6

31

T60

11

T61

41

auto[1]

3559

1

T6

23

T60

5

T61

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2900

1

T6

17

T60

6

T61

28

auto[1]

4496

1

T6

37

T60

10

T61

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4376

1

T6

29

T60

10

T61

45

auto[1]

3020

1

T6

25

T60

6

T61

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

703

1

T6

5

T60

3

T61

3

all_values[0]

auto[0]

auto[0]

auto[1]

394

1

T6

3

T61

7

T112

2

all_values[0]

auto[0]

auto[1]

auto[0]

722

1

T6

6

T61

5

T112

1

all_values[0]

auto[0]

auto[1]

auto[1]

347

1

T6

2

T60

2

T61

5

all_values[0]

auto[1]

auto[0]

auto[1]

806

1

T6

4

T60

2

T61

11

all_values[0]

auto[1]

auto[1]

auto[1]

726

1

T6

7

T60

1

T61

5

all_values[1]

auto[0]

auto[0]

auto[0]

758

1

T6

4

T60

2

T61

10

all_values[1]

auto[0]

auto[0]

auto[1]

376

1

T6

3

T60

2

T61

3

all_values[1]

auto[0]

auto[1]

auto[0]

717

1

T6

2

T60

1

T61

10

all_values[1]

auto[0]

auto[1]

auto[1]

359

1

T6

4

T61

2

T112

2

all_values[1]

auto[1]

auto[0]

auto[1]

800

1

T6

12

T60

2

T61

7

all_values[1]

auto[1]

auto[1]

auto[1]

688

1

T6

2

T60

1

T61

4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal