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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.78 98.25 93.97 97.07 91.86 96.37 99.77 93.18


Total test records in report: 1105
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T1007 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1629400902 Sep 11 09:59:18 AM UTC 24 Sep 11 09:59:20 AM UTC 24 156868147 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2895793268 Sep 11 09:59:18 AM UTC 24 Sep 11 09:59:21 AM UTC 24 56435471 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2025663214 Sep 11 09:59:17 AM UTC 24 Sep 11 09:59:21 AM UTC 24 123300090 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.3009878393 Sep 11 09:59:15 AM UTC 24 Sep 11 09:59:21 AM UTC 24 251736171 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1296907811 Sep 11 09:59:19 AM UTC 24 Sep 11 09:59:22 AM UTC 24 20675925 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3794407386 Sep 11 09:59:20 AM UTC 24 Sep 11 09:59:22 AM UTC 24 12639939 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3335656242 Sep 11 09:59:20 AM UTC 24 Sep 11 09:59:22 AM UTC 24 33151617 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3753098861 Sep 11 09:59:19 AM UTC 24 Sep 11 09:59:22 AM UTC 24 38752311 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3086934877 Sep 11 09:59:18 AM UTC 24 Sep 11 09:59:22 AM UTC 24 59032578 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2726815540 Sep 11 09:59:18 AM UTC 24 Sep 11 09:59:22 AM UTC 24 263367621 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3164201943 Sep 11 09:59:20 AM UTC 24 Sep 11 09:59:22 AM UTC 24 78354507 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.355355888 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:23 AM UTC 24 51118954 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.367059423 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:23 AM UTC 24 50968360 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2696400861 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:23 AM UTC 24 61480287 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3343107397 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:23 AM UTC 24 85294469 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1940072130 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:24 AM UTC 24 80076656 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3547094516 Sep 11 09:59:20 AM UTC 24 Sep 11 09:59:24 AM UTC 24 46680104 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3117580083 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:24 AM UTC 24 103785215 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1658431446 Sep 11 09:59:22 AM UTC 24 Sep 11 09:59:24 AM UTC 24 27969588 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1254292271 Sep 11 09:59:22 AM UTC 24 Sep 11 09:59:24 AM UTC 24 20086059 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.65769454 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:26 AM UTC 24 24019248 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3437734932 Sep 11 09:59:22 AM UTC 24 Sep 11 09:59:25 AM UTC 24 80079001 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.391861116 Sep 11 09:59:21 AM UTC 24 Sep 11 09:59:25 AM UTC 24 90878693 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1862506843 Sep 11 09:59:22 AM UTC 24 Sep 11 09:59:25 AM UTC 24 20294929 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1707271396 Sep 11 09:59:23 AM UTC 24 Sep 11 09:59:26 AM UTC 24 45587356 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3917782787 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:26 AM UTC 24 17822305 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3834570190 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:26 AM UTC 24 34805311 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.929386845 Sep 11 09:59:23 AM UTC 24 Sep 11 09:59:26 AM UTC 24 24182771 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2379442161 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:26 AM UTC 24 73191759 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.717486764 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:27 AM UTC 24 89485499 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.419096725 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:27 AM UTC 24 80365184 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.1767426395 Sep 11 09:59:22 AM UTC 24 Sep 11 09:59:28 AM UTC 24 402186643 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.428775480 Sep 11 09:59:24 AM UTC 24 Sep 11 09:59:29 AM UTC 24 280429985 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.211023445 Sep 11 09:59:26 AM UTC 24 Sep 11 09:59:29 AM UTC 24 45714406 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.2356613723 Sep 11 09:59:26 AM UTC 24 Sep 11 09:59:29 AM UTC 24 21855226 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.2334791051 Sep 11 09:59:26 AM UTC 24 Sep 11 09:59:30 AM UTC 24 44129402 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1862404623 Sep 11 09:59:26 AM UTC 24 Sep 11 09:59:30 AM UTC 24 57054022 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.739031107 Sep 11 09:59:27 AM UTC 24 Sep 11 09:59:31 AM UTC 24 88042959 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2224453690 Sep 11 09:59:27 AM UTC 24 Sep 11 09:59:31 AM UTC 24 250608532 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4131130046 Sep 11 09:59:16 AM UTC 24 Sep 11 09:59:31 AM UTC 24 1244583781 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.4048735845 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:34 AM UTC 24 32231160 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2913574625 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:34 AM UTC 24 216313524 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.2360096778 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:34 AM UTC 24 19922664 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3210679025 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:35 AM UTC 24 42863462 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3584538141 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:35 AM UTC 24 187036682 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.2854968024 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:36 AM UTC 24 81470115 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2204313858 Sep 11 09:59:25 AM UTC 24 Sep 11 09:59:37 AM UTC 24 365148617 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2358615371 Sep 11 09:59:27 AM UTC 24 Sep 11 09:59:40 AM UTC 24 16463982 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3839292636 Sep 11 09:59:35 AM UTC 24 Sep 11 09:59:40 AM UTC 24 25945462 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3201213786 Sep 11 09:59:38 AM UTC 24 Sep 11 09:59:40 AM UTC 24 45244905 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1712290456 Sep 11 09:59:28 AM UTC 24 Sep 11 09:59:40 AM UTC 24 42216843 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.555489387 Sep 11 09:59:28 AM UTC 24 Sep 11 09:59:40 AM UTC 24 77993388 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.163703531 Sep 11 09:59:37 AM UTC 24 Sep 11 09:59:40 AM UTC 24 32131386 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1248144715 Sep 11 09:59:34 AM UTC 24 Sep 11 09:59:40 AM UTC 24 86409438 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2514553568 Sep 11 09:59:28 AM UTC 24 Sep 11 09:59:40 AM UTC 24 35086607 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3215167740 Sep 11 09:59:31 AM UTC 24 Sep 11 09:59:40 AM UTC 24 14829412 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.3568956151 Sep 11 09:59:28 AM UTC 24 Sep 11 09:59:41 AM UTC 24 290311984 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1537284021 Sep 11 09:59:31 AM UTC 24 Sep 11 09:59:42 AM UTC 24 315893894 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3624519410 Sep 11 09:59:35 AM UTC 24 Sep 11 09:59:43 AM UTC 24 414222550 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2776245350 Sep 11 09:59:36 AM UTC 24 Sep 11 09:59:44 AM UTC 24 40632234 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.2431462914 Sep 11 09:59:31 AM UTC 24 Sep 11 09:59:44 AM UTC 24 241306608 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1777378066 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:44 AM UTC 24 15451288 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.4081153606 Sep 11 09:59:42 AM UTC 24 Sep 11 09:59:44 AM UTC 24 20854548 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4086921483 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:44 AM UTC 24 16718038 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.4127307113 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:44 AM UTC 24 40524007 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3531915085 Sep 11 09:59:42 AM UTC 24 Sep 11 09:59:44 AM UTC 24 37855590 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3638453556 Sep 11 09:59:30 AM UTC 24 Sep 11 09:59:45 AM UTC 24 36043621 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.297223821 Sep 11 09:59:30 AM UTC 24 Sep 11 09:59:45 AM UTC 24 13409128 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2161817918 Sep 11 09:59:32 AM UTC 24 Sep 11 09:59:45 AM UTC 24 47953376 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.1449941238 Sep 11 09:59:30 AM UTC 24 Sep 11 09:59:45 AM UTC 24 20557759 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2562993076 Sep 11 09:59:43 AM UTC 24 Sep 11 09:59:45 AM UTC 24 15012472 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2157175657 Sep 11 09:59:30 AM UTC 24 Sep 11 09:59:46 AM UTC 24 65228263 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.3554223532 Sep 11 09:59:36 AM UTC 24 Sep 11 09:59:46 AM UTC 24 137301027 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3004115312 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:49 AM UTC 24 22056807 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1947781980 Sep 11 09:59:45 AM UTC 24 Sep 11 09:59:50 AM UTC 24 13247494 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.1220189256 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:50 AM UTC 24 82260110 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.3809578796 Sep 11 09:59:45 AM UTC 24 Sep 11 09:59:50 AM UTC 24 73446098 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3733470593 Sep 11 09:59:45 AM UTC 24 Sep 11 09:59:50 AM UTC 24 87598700 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3097801479 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:50 AM UTC 24 78813379 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3103471771 Sep 11 09:59:45 AM UTC 24 Sep 11 09:59:50 AM UTC 24 261877503 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.310689188 Sep 11 09:59:45 AM UTC 24 Sep 11 09:59:50 AM UTC 24 48681053 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2997521297 Sep 11 09:59:47 AM UTC 24 Sep 11 09:59:50 AM UTC 24 37445473 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.669914169 Sep 11 09:59:47 AM UTC 24 Sep 11 09:59:50 AM UTC 24 42580100 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.182202051 Sep 11 09:59:36 AM UTC 24 Sep 11 09:59:54 AM UTC 24 22364484 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.764288403 Sep 11 09:59:52 AM UTC 24 Sep 11 09:59:54 AM UTC 24 20338861 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3742942552 Sep 11 09:59:51 AM UTC 24 Sep 11 09:59:54 AM UTC 24 13530610 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3623490253 Sep 11 09:59:51 AM UTC 24 Sep 11 09:59:54 AM UTC 24 33917701 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3777089276 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 27286614 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3543085781 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 62768001 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3746621455 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 18510119 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.429078155 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 22259322 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.831085660 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 24416982 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3341295098 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:55 AM UTC 24 59100685 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1352159584 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 34020066 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.4061860430 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:55 AM UTC 24 30994056 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.558294087 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:55 AM UTC 24 15751342 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1785109671 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:55 AM UTC 24 16426125 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.2622325161 Sep 11 09:59:46 AM UTC 24 Sep 11 09:59:55 AM UTC 24 17712149 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1724303816 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:55 AM UTC 24 24916398 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.1521277600 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:56 AM UTC 24 15330666 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.54568495 Sep 11 09:59:50 AM UTC 24 Sep 11 09:59:56 AM UTC 24 37500976 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1911481078 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:57 AM UTC 24 17302571 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3299112290 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:58 AM UTC 24 22924713 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.756086648 Sep 11 09:59:41 AM UTC 24 Sep 11 09:59:58 AM UTC 24 72928340 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1430909154 Sep 11 09:59:29 AM UTC 24 Sep 11 10:00:00 AM UTC 24 829018926 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_alert.3652885341
Short name T18
Test name
Test status
Simulation time 253126078 ps
CPU time 2.2 seconds
Started Sep 11 09:50:52 AM UTC 24
Finished Sep 11 09:50:56 AM UTC 24
Peak memory 232244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652885341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.3652885341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_sec_cm.2956801531
Short name T21
Test name
Test status
Simulation time 2017290569 ps
CPU time 10.61 seconds
Started Sep 11 09:51:07 AM UTC 24
Finished Sep 11 09:51:18 AM UTC 24
Peak memory 262432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956801531 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2956801531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_genbits.2115767847
Short name T3
Test name
Test status
Simulation time 49282196 ps
CPU time 2.07 seconds
Started Sep 11 09:50:50 AM UTC 24
Finished Sep 11 09:50:53 AM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115767847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2115767847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_alert.3944657482
Short name T11
Test name
Test status
Simulation time 25934816 ps
CPU time 1.82 seconds
Started Sep 11 09:50:58 AM UTC 24
Finished Sep 11 09:51:00 AM UTC 24
Peak memory 230436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944657482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.3944657482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.1261509708
Short name T37
Test name
Test status
Simulation time 29888727828 ps
CPU time 46.28 seconds
Started Sep 11 09:51:19 AM UTC 24
Finished Sep 11 09:52:07 AM UTC 24
Peak memory 233808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1261509708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_
with_rand_reset.1261509708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_err.2150060328
Short name T5
Test name
Test status
Simulation time 42781458 ps
CPU time 1.81 seconds
Started Sep 11 09:50:54 AM UTC 24
Finished Sep 11 09:50:57 AM UTC 24
Peak memory 226276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150060328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.2150060328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_stress_all.56266946
Short name T122
Test name
Test status
Simulation time 307388904 ps
CPU time 4.77 seconds
Started Sep 11 09:51:28 AM UTC 24
Finished Sep 11 09:51:34 AM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56266946 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.56266946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.2323846497
Short name T53
Test name
Test status
Simulation time 73731979 ps
CPU time 1.41 seconds
Started Sep 11 09:51:06 AM UTC 24
Finished Sep 11 09:51:08 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323846497 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.2323846497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_alert.3246759953
Short name T90
Test name
Test status
Simulation time 25978910 ps
CPU time 1.8 seconds
Started Sep 11 09:51:54 AM UTC 24
Finished Sep 11 09:51:57 AM UTC 24
Peak memory 228420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246759953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.3246759953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_genbits.2952700250
Short name T72
Test name
Test status
Simulation time 150361114 ps
CPU time 3.76 seconds
Started Sep 11 09:51:52 AM UTC 24
Finished Sep 11 09:51:57 AM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952700250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2952700250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_alert.2365774427
Short name T83
Test name
Test status
Simulation time 27563625 ps
CPU time 1.95 seconds
Started Sep 11 09:52:48 AM UTC 24
Finished Sep 11 09:52:51 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365774427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.2365774427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.3248671029
Short name T15
Test name
Test status
Simulation time 58814274 ps
CPU time 1.63 seconds
Started Sep 11 09:50:59 AM UTC 24
Finished Sep 11 09:51:01 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248671029 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3248671029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.179464709
Short name T231
Test name
Test status
Simulation time 6368129542 ps
CPU time 80.09 seconds
Started Sep 11 09:52:11 AM UTC 24
Finished Sep 11 09:53:33 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=179464709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_
with_rand_reset.179464709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_alert.3531461165
Short name T179
Test name
Test status
Simulation time 293145276 ps
CPU time 1.9 seconds
Started Sep 11 09:53:15 AM UTC 24
Finished Sep 11 09:53:18 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531461165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.3531461165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.1838450672
Short name T262
Test name
Test status
Simulation time 124279453 ps
CPU time 1.14 seconds
Started Sep 11 09:59:09 AM UTC 24
Finished Sep 11 09:59:11 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838450672 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1838450672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_intr.3049414809
Short name T34
Test name
Test status
Simulation time 32651429 ps
CPU time 1.24 seconds
Started Sep 11 09:51:20 AM UTC 24
Finished Sep 11 09:51:22 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049414809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.3049414809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_err.303514639
Short name T16
Test name
Test status
Simulation time 19440770 ps
CPU time 1.56 seconds
Started Sep 11 09:50:58 AM UTC 24
Finished Sep 11 09:51:00 AM UTC 24
Peak memory 236956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303514639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.edn_err.303514639
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.4156187324
Short name T295
Test name
Test status
Simulation time 52618167 ps
CPU time 2.13 seconds
Started Sep 11 09:59:09 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 217480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156187324 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4156187324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_disable.1413824018
Short name T91
Test name
Test status
Simulation time 13702962 ps
CPU time 1.24 seconds
Started Sep 11 09:51:58 AM UTC 24
Finished Sep 11 09:52:00 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413824018 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1413824018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_regwen.2239692875
Short name T2
Test name
Test status
Simulation time 22996834 ps
CPU time 1.43 seconds
Started Sep 11 09:50:50 AM UTC 24
Finished Sep 11 09:50:52 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239692875 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.2239692875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_disable.3948041710
Short name T217
Test name
Test status
Simulation time 34242732 ps
CPU time 1.14 seconds
Started Sep 11 09:56:07 AM UTC 24
Finished Sep 11 09:56:09 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948041710 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3948041710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_disable.1043795490
Short name T392
Test name
Test status
Simulation time 34222696 ps
CPU time 1.28 seconds
Started Sep 11 09:53:40 AM UTC 24
Finished Sep 11 09:53:43 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043795490 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1043795490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.3834956373
Short name T413
Test name
Test status
Simulation time 32795173 ps
CPU time 1.69 seconds
Started Sep 11 09:54:06 AM UTC 24
Finished Sep 11 09:54:09 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834956373 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.3834956373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_alert.1717756561
Short name T203
Test name
Test status
Simulation time 41451062 ps
CPU time 1.42 seconds
Started Sep 11 09:53:58 AM UTC 24
Finished Sep 11 09:54:00 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717756561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.1717756561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.1100391094
Short name T10
Test name
Test status
Simulation time 39344126 ps
CPU time 1.62 seconds
Started Sep 11 09:50:54 AM UTC 24
Finished Sep 11 09:50:57 AM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100391094 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.1100391094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_alert.191672632
Short name T126
Test name
Test status
Simulation time 83579420 ps
CPU time 1.62 seconds
Started Sep 11 09:52:29 AM UTC 24
Finished Sep 11 09:52:32 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191672632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_alert.191672632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/57.edn_genbits.2028821964
Short name T338
Test name
Test status
Simulation time 41056291 ps
CPU time 2.65 seconds
Started Sep 11 09:57:07 AM UTC 24
Finished Sep 11 09:57:12 AM UTC 24
Peak memory 231696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028821964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2028821964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/132.edn_alert.2101692923
Short name T302
Test name
Test status
Simulation time 26525069 ps
CPU time 1.58 seconds
Started Sep 11 09:58:20 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101692923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.2101692923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_disable.1489683081
Short name T52
Test name
Test status
Simulation time 62362084 ps
CPU time 1.31 seconds
Started Sep 11 09:51:14 AM UTC 24
Finished Sep 11 09:51:17 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489683081 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1489683081
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_alert.4200172205
Short name T127
Test name
Test status
Simulation time 91033526 ps
CPU time 1.77 seconds
Started Sep 11 09:52:16 AM UTC 24
Finished Sep 11 09:52:19 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200172205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.4200172205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.117937449
Short name T167
Test name
Test status
Simulation time 103673537 ps
CPU time 1.55 seconds
Started Sep 11 09:52:31 AM UTC 24
Finished Sep 11 09:52:33 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117937449 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.117937449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_genbits.1669649345
Short name T45
Test name
Test status
Simulation time 86988193 ps
CPU time 1.66 seconds
Started Sep 11 09:51:42 AM UTC 24
Finished Sep 11 09:51:45 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669649345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1669649345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_alert.2292572331
Short name T77
Test name
Test status
Simulation time 180914939 ps
CPU time 1.4 seconds
Started Sep 11 09:53:46 AM UTC 24
Finished Sep 11 09:53:49 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292572331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.2292572331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_alert.3506064501
Short name T50
Test name
Test status
Simulation time 28366223 ps
CPU time 1.61 seconds
Started Sep 11 09:51:11 AM UTC 24
Finished Sep 11 09:51:14 AM UTC 24
Peak memory 226372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506064501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.3506064501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_intr.742369251
Short name T558
Test name
Test status
Simulation time 28177846 ps
CPU time 1.21 seconds
Started Sep 11 09:56:17 AM UTC 24
Finished Sep 11 09:56:19 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742369251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.742369251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_disable.2659594225
Short name T73
Test name
Test status
Simulation time 15254206 ps
CPU time 1.23 seconds
Started Sep 11 09:52:11 AM UTC 24
Finished Sep 11 09:52:14 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659594225 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2659594225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/112.edn_alert.1696645859
Short name T711
Test name
Test status
Simulation time 78913828 ps
CPU time 1.35 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696645859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.1696645859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/117.edn_alert.2399603162
Short name T154
Test name
Test status
Simulation time 42137838 ps
CPU time 1.51 seconds
Started Sep 11 09:58:13 AM UTC 24
Finished Sep 11 09:58:15 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399603162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.2399603162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.2364201432
Short name T81
Test name
Test status
Simulation time 92524513 ps
CPU time 1.51 seconds
Started Sep 11 09:52:26 AM UTC 24
Finished Sep 11 09:52:28 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364201432 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.2364201432
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/120.edn_alert.2969686606
Short name T193
Test name
Test status
Simulation time 34715113 ps
CPU time 1.35 seconds
Started Sep 11 09:58:14 AM UTC 24
Finished Sep 11 09:58:16 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969686606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.2969686606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/143.edn_alert.2225676202
Short name T189
Test name
Test status
Simulation time 27654827 ps
CPU time 1.23 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:27 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225676202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.2225676202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/154.edn_alert.598171057
Short name T151
Test name
Test status
Simulation time 28794116 ps
CPU time 1.28 seconds
Started Sep 11 09:58:29 AM UTC 24
Finished Sep 11 09:58:31 AM UTC 24
Peak memory 230452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598171057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 154.edn_alert.598171057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/156.edn_alert.1600007067
Short name T794
Test name
Test status
Simulation time 93286657 ps
CPU time 1.28 seconds
Started Sep 11 09:58:30 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600007067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.1600007067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_err.714008399
Short name T58
Test name
Test status
Simulation time 77756411 ps
CPU time 1.34 seconds
Started Sep 11 09:51:13 AM UTC 24
Finished Sep 11 09:51:16 AM UTC 24
Peak memory 246080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714008399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.edn_err.714008399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_disable.3430983784
Short name T208
Test name
Test status
Simulation time 155756257 ps
CPU time 1.14 seconds
Started Sep 11 09:56:13 AM UTC 24
Finished Sep 11 09:56:15 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430983784 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3430983784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.532664308
Short name T221
Test name
Test status
Simulation time 83006763 ps
CPU time 1.51 seconds
Started Sep 11 09:56:46 AM UTC 24
Finished Sep 11 09:56:49 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532664308 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.532664308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/53.edn_err.3076357496
Short name T202
Test name
Test status
Simulation time 29474131 ps
CPU time 1.31 seconds
Started Sep 11 09:57:00 AM UTC 24
Finished Sep 11 09:57:03 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076357496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.3076357496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_stress_all.1813230886
Short name T299
Test name
Test status
Simulation time 1400225527 ps
CPU time 6.74 seconds
Started Sep 11 09:53:13 AM UTC 24
Finished Sep 11 09:53:21 AM UTC 24
Peak memory 227488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813230886 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1813230886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_genbits.1752087246
Short name T341
Test name
Test status
Simulation time 47584502 ps
CPU time 2.68 seconds
Started Sep 11 09:54:17 AM UTC 24
Finished Sep 11 09:54:21 AM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752087246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1752087246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_genbits.873785636
Short name T322
Test name
Test status
Simulation time 144323927 ps
CPU time 1.9 seconds
Started Sep 11 09:55:01 AM UTC 24
Finished Sep 11 09:55:04 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873785636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_genbits.873785636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_alert_test.3744147100
Short name T29
Test name
Test status
Simulation time 16942025 ps
CPU time 1.36 seconds
Started Sep 11 09:50:54 AM UTC 24
Finished Sep 11 09:50:57 AM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744147100 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3744147100
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_regwen.329437390
Short name T312
Test name
Test status
Simulation time 16697101 ps
CPU time 1.57 seconds
Started Sep 11 09:51:08 AM UTC 24
Finished Sep 11 09:51:10 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329437390 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_regwen.329437390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_genbits.2613529405
Short name T303
Test name
Test status
Simulation time 134158461 ps
CPU time 2.88 seconds
Started Sep 11 09:56:28 AM UTC 24
Finished Sep 11 09:56:32 AM UTC 24
Peak memory 231500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613529405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2613529405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/56.edn_err.2845851358
Short name T102
Test name
Test status
Simulation time 89578257 ps
CPU time 1.84 seconds
Started Sep 11 09:57:07 AM UTC 24
Finished Sep 11 09:57:11 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845851358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.2845851358
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_genbits.2388965084
Short name T14
Test name
Test status
Simulation time 126193936 ps
CPU time 1.88 seconds
Started Sep 11 09:56:50 AM UTC 24
Finished Sep 11 09:56:53 AM UTC 24
Peak memory 230604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388965084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2388965084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_genbits.1519367409
Short name T84
Test name
Test status
Simulation time 128382568 ps
CPU time 2.13 seconds
Started Sep 11 09:54:08 AM UTC 24
Finished Sep 11 09:54:11 AM UTC 24
Peak memory 231488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519367409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1519367409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.419096725
Short name T1033
Test name
Test status
Simulation time 80365184 ps
CPU time 2.54 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:27 AM UTC 24
Peak memory 217484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419096725 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.419096725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/105.edn_genbits.1290441235
Short name T318
Test name
Test status
Simulation time 32916160 ps
CPU time 1.6 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290441235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1290441235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/107.edn_genbits.1192458839
Short name T334
Test name
Test status
Simulation time 102833076 ps
CPU time 2.01 seconds
Started Sep 11 09:58:05 AM UTC 24
Finished Sep 11 09:58:09 AM UTC 24
Peak memory 231732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192458839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1192458839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/115.edn_genbits.1920423984
Short name T328
Test name
Test status
Simulation time 47127552 ps
CPU time 1.82 seconds
Started Sep 11 09:58:11 AM UTC 24
Finished Sep 11 09:58:14 AM UTC 24
Peak memory 228344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920423984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1920423984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/137.edn_genbits.3002984306
Short name T759
Test name
Test status
Simulation time 75252740 ps
CPU time 1.34 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002984306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3002984306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/139.edn_genbits.1802100451
Short name T325
Test name
Test status
Simulation time 41068126 ps
CPU time 1.97 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802100451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1802100451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_stress_all.1948901766
Short name T316
Test name
Test status
Simulation time 287487426 ps
CPU time 8.03 seconds
Started Sep 11 09:52:33 AM UTC 24
Finished Sep 11 09:52:42 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948901766 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1948901766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/181.edn_genbits.2748505038
Short name T839
Test name
Test status
Simulation time 70540728 ps
CPU time 1.56 seconds
Started Sep 11 09:58:40 AM UTC 24
Finished Sep 11 09:58:42 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748505038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2748505038
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_genbits.3488819003
Short name T85
Test name
Test status
Simulation time 112218838 ps
CPU time 3.14 seconds
Started Sep 11 09:54:30 AM UTC 24
Finished Sep 11 09:54:34 AM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488819003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3488819003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_intr.466225825
Short name T4
Test name
Test status
Simulation time 22676364 ps
CPU time 1.29 seconds
Started Sep 11 09:50:51 AM UTC 24
Finished Sep 11 09:50:54 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466225825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.466225825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_intr.3255904763
Short name T135
Test name
Test status
Simulation time 22432511 ps
CPU time 1.2 seconds
Started Sep 11 09:52:16 AM UTC 24
Finished Sep 11 09:52:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255904763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.3255904763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_intr.2313443950
Short name T19
Test name
Test status
Simulation time 23246637 ps
CPU time 1.49 seconds
Started Sep 11 09:50:58 AM UTC 24
Finished Sep 11 09:51:00 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313443950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.2313443950
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_alert.3081568168
Short name T137
Test name
Test status
Simulation time 23721793 ps
CPU time 1.86 seconds
Started Sep 11 09:55:57 AM UTC 24
Finished Sep 11 09:56:00 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081568168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_alert.3081568168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/116.edn_genbits.3746021820
Short name T722
Test name
Test status
Simulation time 75775185 ps
CPU time 1.95 seconds
Started Sep 11 09:58:11 AM UTC 24
Finished Sep 11 09:58:14 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746021820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3746021820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_err.1465718697
Short name T211
Test name
Test status
Simulation time 33001536 ps
CPU time 1.45 seconds
Started Sep 11 09:52:29 AM UTC 24
Finished Sep 11 09:52:32 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465718697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.1465718697
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/63.edn_genbits.1641092561
Short name T613
Test name
Test status
Simulation time 57536660 ps
CPU time 2.5 seconds
Started Sep 11 09:57:19 AM UTC 24
Finished Sep 11 09:57:23 AM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641092561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1641092561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.501668798
Short name T263
Test name
Test status
Simulation time 18869490 ps
CPU time 1.62 seconds
Started Sep 11 09:59:08 AM UTC 24
Finished Sep 11 09:59:11 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501668798 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.501668798
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.4020367684
Short name T987
Test name
Test status
Simulation time 508255895 ps
CPU time 6.51 seconds
Started Sep 11 09:59:07 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 217632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020367684 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4020367684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.1447432593
Short name T972
Test name
Test status
Simulation time 75426915 ps
CPU time 0.97 seconds
Started Sep 11 09:59:07 AM UTC 24
Finished Sep 11 09:59:09 AM UTC 24
Peak memory 216572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447432593 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1447432593
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1559087260
Short name T977
Test name
Test status
Simulation time 119586685 ps
CPU time 1.41 seconds
Started Sep 11 09:59:08 AM UTC 24
Finished Sep 11 09:59:11 AM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1559087260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1559087260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.460093522
Short name T261
Test name
Test status
Simulation time 12658767 ps
CPU time 1.2 seconds
Started Sep 11 09:59:07 AM UTC 24
Finished Sep 11 09:59:09 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460093522 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.460093522
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.2170851531
Short name T973
Test name
Test status
Simulation time 21028582 ps
CPU time 1.07 seconds
Started Sep 11 09:59:07 AM UTC 24
Finished Sep 11 09:59:09 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170851531 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2170851531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.2231986370
Short name T276
Test name
Test status
Simulation time 65292030 ps
CPU time 1.98 seconds
Started Sep 11 09:59:08 AM UTC 24
Finished Sep 11 09:59:11 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231986370 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2231986370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.3605939389
Short name T975
Test name
Test status
Simulation time 52128637 ps
CPU time 2.45 seconds
Started Sep 11 09:59:07 AM UTC 24
Finished Sep 11 09:59:11 AM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605939389 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3605939389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.3866615654
Short name T294
Test name
Test status
Simulation time 146117795 ps
CPU time 1.73 seconds
Started Sep 11 09:59:07 AM UTC 24
Finished Sep 11 09:59:10 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866615654 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3866615654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.303351532
Short name T265
Test name
Test status
Simulation time 53056625 ps
CPU time 1.53 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303351532 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.303351532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.563738817
Short name T266
Test name
Test status
Simulation time 232846622 ps
CPU time 4.07 seconds
Started Sep 11 09:59:09 AM UTC 24
Finished Sep 11 09:59:14 AM UTC 24
Peak memory 217624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563738817 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.563738817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.93092505
Short name T976
Test name
Test status
Simulation time 33286523 ps
CPU time 1.18 seconds
Started Sep 11 09:59:09 AM UTC 24
Finished Sep 11 09:59:11 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93092505 -assert nopostproc +UVM_TESTNAME=edn_
base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.93092505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1761344763
Short name T978
Test name
Test status
Simulation time 192514318 ps
CPU time 1.3 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1761344763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1761344763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.2931649133
Short name T974
Test name
Test status
Simulation time 12278214 ps
CPU time 0.89 seconds
Started Sep 11 09:59:09 AM UTC 24
Finished Sep 11 09:59:10 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931649133 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2931649133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.1200509733
Short name T277
Test name
Test status
Simulation time 43428862 ps
CPU time 1.1 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200509733 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.1200509733
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3434236015
Short name T981
Test name
Test status
Simulation time 390608200 ps
CPU time 3.37 seconds
Started Sep 11 09:59:09 AM UTC 24
Finished Sep 11 09:59:13 AM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434236015 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3434236015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1862506843
Short name T1026
Test name
Test status
Simulation time 20294929 ps
CPU time 1.24 seconds
Started Sep 11 09:59:22 AM UTC 24
Finished Sep 11 09:59:25 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1862506843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1862506843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2696400861
Short name T1017
Test name
Test status
Simulation time 61480287 ps
CPU time 1.07 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:23 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696400861 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2696400861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.355355888
Short name T1016
Test name
Test status
Simulation time 51118954 ps
CPU time 0.94 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:23 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355355888 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.355355888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.198926093
Short name T283
Test name
Test status
Simulation time 43135704 ps
CPU time 1.15 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:23 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198926093 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.198926093
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1940072130
Short name T1019
Test name
Test status
Simulation time 80076656 ps
CPU time 1.56 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:24 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940072130 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1940072130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.391861116
Short name T1025
Test name
Test status
Simulation time 90878693 ps
CPU time 3.11 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:25 AM UTC 24
Peak memory 217820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391861116 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.391861116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1707271396
Short name T1027
Test name
Test status
Simulation time 45587356 ps
CPU time 1.31 seconds
Started Sep 11 09:59:23 AM UTC 24
Finished Sep 11 09:59:26 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1707271396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1707271396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1658431446
Short name T272
Test name
Test status
Simulation time 27969588 ps
CPU time 1.09 seconds
Started Sep 11 09:59:22 AM UTC 24
Finished Sep 11 09:59:24 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658431446 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1658431446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1254292271
Short name T1022
Test name
Test status
Simulation time 20086059 ps
CPU time 1.12 seconds
Started Sep 11 09:59:22 AM UTC 24
Finished Sep 11 09:59:24 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254292271 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1254292271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.929386845
Short name T1030
Test name
Test status
Simulation time 24182771 ps
CPU time 1.72 seconds
Started Sep 11 09:59:23 AM UTC 24
Finished Sep 11 09:59:26 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929386845 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.929386845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.1767426395
Short name T1034
Test name
Test status
Simulation time 402186643 ps
CPU time 3.62 seconds
Started Sep 11 09:59:22 AM UTC 24
Finished Sep 11 09:59:28 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767426395 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1767426395
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3437734932
Short name T1024
Test name
Test status
Simulation time 80079001 ps
CPU time 1.85 seconds
Started Sep 11 09:59:22 AM UTC 24
Finished Sep 11 09:59:25 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437734932 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3437734932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2379442161
Short name T1031
Test name
Test status
Simulation time 73191759 ps
CPU time 1.53 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:26 AM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2379442161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2379442161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3834570190
Short name T1029
Test name
Test status
Simulation time 34805311 ps
CPU time 1.23 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:26 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834570190 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3834570190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3917782787
Short name T1028
Test name
Test status
Simulation time 17822305 ps
CPU time 1.18 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:26 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917782787 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3917782787
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.65769454
Short name T1023
Test name
Test status
Simulation time 24019248 ps
CPU time 1.19 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:26 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65769454 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.65769454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.717486764
Short name T1032
Test name
Test status
Simulation time 89485499 ps
CPU time 2.25 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:27 AM UTC 24
Peak memory 227840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717486764 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.717486764
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3210679025
Short name T1046
Test name
Test status
Simulation time 42863462 ps
CPU time 1.34 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:35 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3210679025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3210679025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.2360096778
Short name T1045
Test name
Test status
Simulation time 19922664 ps
CPU time 1.15 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:34 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360096778 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2360096778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.4048735845
Short name T1043
Test name
Test status
Simulation time 32231160 ps
CPU time 0.84 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:34 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048735845 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4048735845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2913574625
Short name T1044
Test name
Test status
Simulation time 216313524 ps
CPU time 1.04 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:34 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913574625 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.2913574625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.428775480
Short name T1035
Test name
Test status
Simulation time 280429985 ps
CPU time 4.22 seconds
Started Sep 11 09:59:24 AM UTC 24
Finished Sep 11 09:59:29 AM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428775480 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.428775480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.2854968024
Short name T1048
Test name
Test status
Simulation time 81470115 ps
CPU time 2.49 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:36 AM UTC 24
Peak memory 217512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854968024 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2854968024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1862404623
Short name T1039
Test name
Test status
Simulation time 57054022 ps
CPU time 1.86 seconds
Started Sep 11 09:59:26 AM UTC 24
Finished Sep 11 09:59:30 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1862404623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1862404623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.2356613723
Short name T1037
Test name
Test status
Simulation time 21855226 ps
CPU time 1.04 seconds
Started Sep 11 09:59:26 AM UTC 24
Finished Sep 11 09:59:29 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356613723 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2356613723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.211023445
Short name T1036
Test name
Test status
Simulation time 45714406 ps
CPU time 0.99 seconds
Started Sep 11 09:59:26 AM UTC 24
Finished Sep 11 09:59:29 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211023445 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.211023445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.2334791051
Short name T1038
Test name
Test status
Simulation time 44129402 ps
CPU time 1.09 seconds
Started Sep 11 09:59:26 AM UTC 24
Finished Sep 11 09:59:30 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334791051 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.2334791051
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2204313858
Short name T1049
Test name
Test status
Simulation time 365148617 ps
CPU time 3.82 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:37 AM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204313858 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2204313858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3584538141
Short name T1047
Test name
Test status
Simulation time 187036682 ps
CPU time 1.82 seconds
Started Sep 11 09:59:25 AM UTC 24
Finished Sep 11 09:59:35 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584538141 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3584538141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.555489387
Short name T1054
Test name
Test status
Simulation time 77993388 ps
CPU time 1.29 seconds
Started Sep 11 09:59:28 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=555489387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.555489387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1712290456
Short name T1053
Test name
Test status
Simulation time 42216843 ps
CPU time 1.24 seconds
Started Sep 11 09:59:28 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 215420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712290456 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1712290456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2358615371
Short name T1050
Test name
Test status
Simulation time 16463982 ps
CPU time 1.08 seconds
Started Sep 11 09:59:27 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358615371 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2358615371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2514553568
Short name T1057
Test name
Test status
Simulation time 35086607 ps
CPU time 1.58 seconds
Started Sep 11 09:59:28 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514553568 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.2514553568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2224453690
Short name T1041
Test name
Test status
Simulation time 250608532 ps
CPU time 2.25 seconds
Started Sep 11 09:59:27 AM UTC 24
Finished Sep 11 09:59:31 AM UTC 24
Peak memory 227868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224453690 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2224453690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.739031107
Short name T1040
Test name
Test status
Simulation time 88042959 ps
CPU time 2.21 seconds
Started Sep 11 09:59:27 AM UTC 24
Finished Sep 11 09:59:31 AM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739031107 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.739031107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2157175657
Short name T1073
Test name
Test status
Simulation time 65228263 ps
CPU time 1.49 seconds
Started Sep 11 09:59:30 AM UTC 24
Finished Sep 11 09:59:46 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2157175657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2157175657
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.297223821
Short name T1070
Test name
Test status
Simulation time 13409128 ps
CPU time 1.03 seconds
Started Sep 11 09:59:30 AM UTC 24
Finished Sep 11 09:59:45 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297223821 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.297223821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3638453556
Short name T1069
Test name
Test status
Simulation time 36043621 ps
CPU time 0.93 seconds
Started Sep 11 09:59:30 AM UTC 24
Finished Sep 11 09:59:45 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638453556 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3638453556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.1449941238
Short name T1071
Test name
Test status
Simulation time 20557759 ps
CPU time 1.29 seconds
Started Sep 11 09:59:30 AM UTC 24
Finished Sep 11 09:59:45 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449941238 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.1449941238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.3568956151
Short name T1059
Test name
Test status
Simulation time 290311984 ps
CPU time 2.69 seconds
Started Sep 11 09:59:28 AM UTC 24
Finished Sep 11 09:59:41 AM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568956151 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3568956151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1430909154
Short name T1105
Test name
Test status
Simulation time 829018926 ps
CPU time 2.28 seconds
Started Sep 11 09:59:29 AM UTC 24
Finished Sep 11 10:00:00 AM UTC 24
Peak memory 217740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430909154 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1430909154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3839292636
Short name T1051
Test name
Test status
Simulation time 25945462 ps
CPU time 1.21 seconds
Started Sep 11 09:59:35 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3839292636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3839292636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2161817918
Short name T273
Test name
Test status
Simulation time 47953376 ps
CPU time 1.03 seconds
Started Sep 11 09:59:32 AM UTC 24
Finished Sep 11 09:59:45 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161817918 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2161817918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3215167740
Short name T1058
Test name
Test status
Simulation time 14829412 ps
CPU time 1.15 seconds
Started Sep 11 09:59:31 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215167740 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3215167740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1248144715
Short name T1056
Test name
Test status
Simulation time 86409438 ps
CPU time 1.55 seconds
Started Sep 11 09:59:34 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248144715 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.1248144715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.2431462914
Short name T1063
Test name
Test status
Simulation time 241306608 ps
CPU time 4.6 seconds
Started Sep 11 09:59:31 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431462914 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2431462914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1537284021
Short name T1060
Test name
Test status
Simulation time 315893894 ps
CPU time 2.4 seconds
Started Sep 11 09:59:31 AM UTC 24
Finished Sep 11 09:59:42 AM UTC 24
Peak memory 217556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537284021 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1537284021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3201213786
Short name T1052
Test name
Test status
Simulation time 45244905 ps
CPU time 1.09 seconds
Started Sep 11 09:59:38 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3201213786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3201213786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.182202051
Short name T1085
Test name
Test status
Simulation time 22364484 ps
CPU time 0.91 seconds
Started Sep 11 09:59:36 AM UTC 24
Finished Sep 11 09:59:54 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182202051 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.182202051
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2776245350
Short name T1062
Test name
Test status
Simulation time 40632234 ps
CPU time 0.76 seconds
Started Sep 11 09:59:36 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776245350 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2776245350
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.163703531
Short name T1055
Test name
Test status
Simulation time 32131386 ps
CPU time 1.17 seconds
Started Sep 11 09:59:37 AM UTC 24
Finished Sep 11 09:59:40 AM UTC 24
Peak memory 215436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163703531 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.163703531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3624519410
Short name T1061
Test name
Test status
Simulation time 414222550 ps
CPU time 3.88 seconds
Started Sep 11 09:59:35 AM UTC 24
Finished Sep 11 09:59:43 AM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624519410 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3624519410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.3554223532
Short name T1074
Test name
Test status
Simulation time 137301027 ps
CPU time 2.11 seconds
Started Sep 11 09:59:36 AM UTC 24
Finished Sep 11 09:59:46 AM UTC 24
Peak memory 217484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554223532 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3554223532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3299112290
Short name T1103
Test name
Test status
Simulation time 22924713 ps
CPU time 1.21 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:58 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3299112290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3299112290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1911481078
Short name T275
Test name
Test status
Simulation time 17302571 ps
CPU time 1.02 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:57 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911481078 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1911481078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3004115312
Short name T1075
Test name
Test status
Simulation time 22056807 ps
CPU time 0.88 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:49 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004115312 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3004115312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.756086648
Short name T1104
Test name
Test status
Simulation time 72928340 ps
CPU time 1.34 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:58 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756086648 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.756086648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3097801479
Short name T1080
Test name
Test status
Simulation time 78813379 ps
CPU time 1.69 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097801479 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3097801479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.1220189256
Short name T1077
Test name
Test status
Simulation time 82260110 ps
CPU time 1.54 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220189256 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1220189256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.454863925
Short name T985
Test name
Test status
Simulation time 21913679 ps
CPU time 1.73 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:14 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454863925 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.454863925
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.335335237
Short name T1002
Test name
Test status
Simulation time 523893246 ps
CPU time 7.82 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 217432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335335237 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.335335237
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2813260343
Short name T264
Test name
Test status
Simulation time 35579128 ps
CPU time 1.07 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813260343 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2813260343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2823927099
Short name T983
Test name
Test status
Simulation time 22566639 ps
CPU time 1.14 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:13 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2823927099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2823927099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.2559646215
Short name T979
Test name
Test status
Simulation time 48999513 ps
CPU time 1.11 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559646215 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2559646215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.4097340031
Short name T980
Test name
Test status
Simulation time 15211971 ps
CPU time 1.22 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:12 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097340031 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4097340031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.1782410808
Short name T278
Test name
Test status
Simulation time 26665130 ps
CPU time 1.51 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:14 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782410808 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.1782410808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.3127488797
Short name T982
Test name
Test status
Simulation time 29387707 ps
CPU time 2.2 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:13 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127488797 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3127488797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.2019933285
Short name T296
Test name
Test status
Simulation time 212134716 ps
CPU time 2.35 seconds
Started Sep 11 09:59:10 AM UTC 24
Finished Sep 11 09:59:13 AM UTC 24
Peak memory 217496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019933285 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2019933285
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1777378066
Short name T1064
Test name
Test status
Simulation time 15451288 ps
CPU time 0.98 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777378066 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1777378066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4086921483
Short name T1066
Test name
Test status
Simulation time 16718038 ps
CPU time 1.01 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086921483 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4086921483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.4127307113
Short name T1067
Test name
Test status
Simulation time 40524007 ps
CPU time 0.96 seconds
Started Sep 11 09:59:41 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127307113 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4127307113
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.4081153606
Short name T1065
Test name
Test status
Simulation time 20854548 ps
CPU time 0.82 seconds
Started Sep 11 09:59:42 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081153606 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4081153606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3531915085
Short name T1068
Test name
Test status
Simulation time 37855590 ps
CPU time 0.94 seconds
Started Sep 11 09:59:42 AM UTC 24
Finished Sep 11 09:59:44 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531915085 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3531915085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2562993076
Short name T1072
Test name
Test status
Simulation time 15012472 ps
CPU time 1.02 seconds
Started Sep 11 09:59:43 AM UTC 24
Finished Sep 11 09:59:45 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562993076 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2562993076
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.3809578796
Short name T1078
Test name
Test status
Simulation time 73446098 ps
CPU time 1.05 seconds
Started Sep 11 09:59:45 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809578796 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3809578796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3103471771
Short name T1081
Test name
Test status
Simulation time 261877503 ps
CPU time 1.17 seconds
Started Sep 11 09:59:45 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103471771 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3103471771
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1947781980
Short name T1076
Test name
Test status
Simulation time 13247494 ps
CPU time 0.96 seconds
Started Sep 11 09:59:45 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947781980 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1947781980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3733470593
Short name T1079
Test name
Test status
Simulation time 87598700 ps
CPU time 1.04 seconds
Started Sep 11 09:59:45 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733470593 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3733470593
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.1758191896
Short name T988
Test name
Test status
Simulation time 37114855 ps
CPU time 1.27 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758191896 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1758191896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.1488730613
Short name T269
Test name
Test status
Simulation time 132077584 ps
CPU time 3.91 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:18 AM UTC 24
Peak memory 217404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488730613 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1488730613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.1649042261
Short name T268
Test name
Test status
Simulation time 28274375 ps
CPU time 1.41 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649042261 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1649042261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.751439402
Short name T989
Test name
Test status
Simulation time 94185124 ps
CPU time 1.47 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=751439402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.751439402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2180242726
Short name T267
Test name
Test status
Simulation time 23000381 ps
CPU time 1.09 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 215364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180242726 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2180242726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.3643039938
Short name T984
Test name
Test status
Simulation time 39158032 ps
CPU time 1.14 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:14 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643039938 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3643039938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1995464223
Short name T279
Test name
Test status
Simulation time 40210586 ps
CPU time 1.72 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995464223 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1995464223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.657037377
Short name T986
Test name
Test status
Simulation time 48551965 ps
CPU time 2.19 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:15 AM UTC 24
Peak memory 227792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657037377 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.657037377
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.140678377
Short name T305
Test name
Test status
Simulation time 107212941 ps
CPU time 1.93 seconds
Started Sep 11 09:59:11 AM UTC 24
Finished Sep 11 09:59:14 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140678377 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.140678377
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.310689188
Short name T1082
Test name
Test status
Simulation time 48681053 ps
CPU time 1.12 seconds
Started Sep 11 09:59:45 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310689188 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.310689188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3777089276
Short name T1089
Test name
Test status
Simulation time 27286614 ps
CPU time 0.88 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777089276 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3777089276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.429078155
Short name T1092
Test name
Test status
Simulation time 22259322 ps
CPU time 1.1 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429078155 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.429078155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3746621455
Short name T1091
Test name
Test status
Simulation time 18510119 ps
CPU time 0.89 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746621455 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3746621455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1352159584
Short name T1095
Test name
Test status
Simulation time 34020066 ps
CPU time 1.2 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352159584 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1352159584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3543085781
Short name T1090
Test name
Test status
Simulation time 62768001 ps
CPU time 0.86 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543085781 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3543085781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.2622325161
Short name T1099
Test name
Test status
Simulation time 17712149 ps
CPU time 1.3 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622325161 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2622325161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.831085660
Short name T1093
Test name
Test status
Simulation time 24416982 ps
CPU time 0.87 seconds
Started Sep 11 09:59:46 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831085660 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.831085660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2997521297
Short name T1083
Test name
Test status
Simulation time 37445473 ps
CPU time 0.86 seconds
Started Sep 11 09:59:47 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997521297 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2997521297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.669914169
Short name T1084
Test name
Test status
Simulation time 42580100 ps
CPU time 1.05 seconds
Started Sep 11 09:59:47 AM UTC 24
Finished Sep 11 09:59:50 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669914169 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.669914169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.1816952577
Short name T994
Test name
Test status
Simulation time 184102781 ps
CPU time 1.66 seconds
Started Sep 11 09:59:14 AM UTC 24
Finished Sep 11 09:59:17 AM UTC 24
Peak memory 214664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816952577 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1816952577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.1222469202
Short name T998
Test name
Test status
Simulation time 471225183 ps
CPU time 3.53 seconds
Started Sep 11 09:59:14 AM UTC 24
Finished Sep 11 09:59:19 AM UTC 24
Peak memory 216584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222469202 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1222469202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.2155493331
Short name T992
Test name
Test status
Simulation time 30057598 ps
CPU time 1.35 seconds
Started Sep 11 09:59:14 AM UTC 24
Finished Sep 11 09:59:16 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155493331 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2155493331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3283150470
Short name T996
Test name
Test status
Simulation time 53891050 ps
CPU time 1.41 seconds
Started Sep 11 09:59:15 AM UTC 24
Finished Sep 11 09:59:18 AM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3283150470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3283150470
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.1310967788
Short name T991
Test name
Test status
Simulation time 42823167 ps
CPU time 1.19 seconds
Started Sep 11 09:59:14 AM UTC 24
Finished Sep 11 09:59:16 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310967788 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1310967788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.3500415388
Short name T990
Test name
Test status
Simulation time 32946778 ps
CPU time 0.93 seconds
Started Sep 11 09:59:14 AM UTC 24
Finished Sep 11 09:59:16 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500415388 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3500415388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3020012582
Short name T280
Test name
Test status
Simulation time 217597479 ps
CPU time 1.39 seconds
Started Sep 11 09:59:14 AM UTC 24
Finished Sep 11 09:59:17 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020012582 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3020012582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.1928802144
Short name T993
Test name
Test status
Simulation time 51418520 ps
CPU time 2.61 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:16 AM UTC 24
Peak memory 227868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928802144 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1928802144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.613836813
Short name T306
Test name
Test status
Simulation time 99037205 ps
CPU time 3.63 seconds
Started Sep 11 09:59:13 AM UTC 24
Finished Sep 11 09:59:18 AM UTC 24
Peak memory 217560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613836813 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.613836813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1785109671
Short name T1098
Test name
Test status
Simulation time 16426125 ps
CPU time 1.05 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785109671 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1785109671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3341295098
Short name T1094
Test name
Test status
Simulation time 59100685 ps
CPU time 0.84 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341295098 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3341295098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1724303816
Short name T1100
Test name
Test status
Simulation time 24916398 ps
CPU time 1.09 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724303816 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1724303816
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.558294087
Short name T1097
Test name
Test status
Simulation time 15751342 ps
CPU time 0.91 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558294087 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.558294087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.4061860430
Short name T1096
Test name
Test status
Simulation time 30994056 ps
CPU time 0.87 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:55 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061860430 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4061860430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.1521277600
Short name T1101
Test name
Test status
Simulation time 15330666 ps
CPU time 1.04 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:56 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521277600 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1521277600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.54568495
Short name T1102
Test name
Test status
Simulation time 37500976 ps
CPU time 0.99 seconds
Started Sep 11 09:59:50 AM UTC 24
Finished Sep 11 09:59:56 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54568495 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.54568495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3623490253
Short name T1088
Test name
Test status
Simulation time 33917701 ps
CPU time 0.9 seconds
Started Sep 11 09:59:51 AM UTC 24
Finished Sep 11 09:59:54 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623490253 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3623490253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3742942552
Short name T1087
Test name
Test status
Simulation time 13530610 ps
CPU time 0.79 seconds
Started Sep 11 09:59:51 AM UTC 24
Finished Sep 11 09:59:54 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742942552 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3742942552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.764288403
Short name T1086
Test name
Test status
Simulation time 20338861 ps
CPU time 0.82 seconds
Started Sep 11 09:59:52 AM UTC 24
Finished Sep 11 09:59:54 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764288403 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.764288403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2596696886
Short name T997
Test name
Test status
Simulation time 48624203 ps
CPU time 1.91 seconds
Started Sep 11 09:59:16 AM UTC 24
Finished Sep 11 09:59:19 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2596696886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2596696886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.2860114272
Short name T281
Test name
Test status
Simulation time 154322527 ps
CPU time 1.18 seconds
Started Sep 11 09:59:15 AM UTC 24
Finished Sep 11 09:59:18 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860114272 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2860114272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3114696050
Short name T995
Test name
Test status
Simulation time 12242270 ps
CPU time 0.97 seconds
Started Sep 11 09:59:15 AM UTC 24
Finished Sep 11 09:59:17 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114696050 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3114696050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.3628605245
Short name T282
Test name
Test status
Simulation time 80539640 ps
CPU time 1.47 seconds
Started Sep 11 09:59:16 AM UTC 24
Finished Sep 11 09:59:18 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628605245 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.3628605245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.3009878393
Short name T1010
Test name
Test status
Simulation time 251736171 ps
CPU time 4.69 seconds
Started Sep 11 09:59:15 AM UTC 24
Finished Sep 11 09:59:21 AM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009878393 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3009878393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.452616183
Short name T307
Test name
Test status
Simulation time 239860222 ps
CPU time 3.86 seconds
Started Sep 11 09:59:15 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452616183 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.452616183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3095359224
Short name T1000
Test name
Test status
Simulation time 32421819 ps
CPU time 1.74 seconds
Started Sep 11 09:59:17 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3095359224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3095359224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.2891654259
Short name T270
Test name
Test status
Simulation time 19524111 ps
CPU time 1.11 seconds
Started Sep 11 09:59:17 AM UTC 24
Finished Sep 11 09:59:19 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891654259 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2891654259
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.3392213827
Short name T999
Test name
Test status
Simulation time 18897724 ps
CPU time 1.25 seconds
Started Sep 11 09:59:17 AM UTC 24
Finished Sep 11 09:59:19 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392213827 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3392213827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3148881986
Short name T284
Test name
Test status
Simulation time 16169616 ps
CPU time 1.17 seconds
Started Sep 11 09:59:17 AM UTC 24
Finished Sep 11 09:59:19 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148881986 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.3148881986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.1978764389
Short name T1001
Test name
Test status
Simulation time 88187225 ps
CPU time 3.2 seconds
Started Sep 11 09:59:16 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978764389 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1978764389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4131130046
Short name T1042
Test name
Test status
Simulation time 1244583781 ps
CPU time 14.47 seconds
Started Sep 11 09:59:16 AM UTC 24
Finished Sep 11 09:59:31 AM UTC 24
Peak memory 217676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131130046 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4131130046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2895793268
Short name T1008
Test name
Test status
Simulation time 56435471 ps
CPU time 1.4 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:21 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2895793268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2895793268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.2306081515
Short name T1003
Test name
Test status
Simulation time 37175205 ps
CPU time 1.22 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306081515 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2306081515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1088463934
Short name T1004
Test name
Test status
Simulation time 41706492 ps
CPU time 1.24 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088463934 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1088463934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1629400902
Short name T1007
Test name
Test status
Simulation time 156868147 ps
CPU time 1.39 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629400902 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.1629400902
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2025663214
Short name T1009
Test name
Test status
Simulation time 123300090 ps
CPU time 2.83 seconds
Started Sep 11 09:59:17 AM UTC 24
Finished Sep 11 09:59:21 AM UTC 24
Peak memory 227792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025663214 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2025663214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1498040938
Short name T1005
Test name
Test status
Simulation time 553167776 ps
CPU time 2.36 seconds
Started Sep 11 09:59:17 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 217480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498040938 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1498040938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3335656242
Short name T1012
Test name
Test status
Simulation time 33151617 ps
CPU time 1.5 seconds
Started Sep 11 09:59:20 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3335656242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3335656242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1296907811
Short name T271
Test name
Test status
Simulation time 20675925 ps
CPU time 1.13 seconds
Started Sep 11 09:59:19 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296907811 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1296907811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1123103264
Short name T1006
Test name
Test status
Simulation time 36649987 ps
CPU time 0.99 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:20 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123103264 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1123103264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3753098861
Short name T1013
Test name
Test status
Simulation time 38752311 ps
CPU time 1.53 seconds
Started Sep 11 09:59:19 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753098861 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.3753098861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2726815540
Short name T1014
Test name
Test status
Simulation time 263367621 ps
CPU time 2.86 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726815540 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2726815540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3086934877
Short name T308
Test name
Test status
Simulation time 59032578 ps
CPU time 2.74 seconds
Started Sep 11 09:59:18 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 217480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086934877 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3086934877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3117580083
Short name T1021
Test name
Test status
Simulation time 103785215 ps
CPU time 2.28 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:24 AM UTC 24
Peak memory 227652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3117580083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3117580083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.367059423
Short name T274
Test name
Test status
Simulation time 50968360 ps
CPU time 1.3 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:23 AM UTC 24
Peak memory 214312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367059423 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.367059423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3794407386
Short name T1011
Test name
Test status
Simulation time 12639939 ps
CPU time 1.3 seconds
Started Sep 11 09:59:20 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794407386 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3794407386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3343107397
Short name T1018
Test name
Test status
Simulation time 85294469 ps
CPU time 1.65 seconds
Started Sep 11 09:59:21 AM UTC 24
Finished Sep 11 09:59:23 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343107397 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.3343107397
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3547094516
Short name T1020
Test name
Test status
Simulation time 46680104 ps
CPU time 3.27 seconds
Started Sep 11 09:59:20 AM UTC 24
Finished Sep 11 09:59:24 AM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547094516 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3547094516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3164201943
Short name T1015
Test name
Test status
Simulation time 78354507 ps
CPU time 1.59 seconds
Started Sep 11 09:59:20 AM UTC 24
Finished Sep 11 09:59:22 AM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164201943 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3164201943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_disable.2659504632
Short name T28
Test name
Test status
Simulation time 30047983 ps
CPU time 1.2 seconds
Started Sep 11 09:50:54 AM UTC 24
Finished Sep 11 09:50:56 AM UTC 24
Peak memory 226360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659504632 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2659504632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_sec_cm.857570101
Short name T17
Test name
Test status
Simulation time 550654103 ps
CPU time 5.46 seconds
Started Sep 11 09:50:54 AM UTC 24
Finished Sep 11 09:51:01 AM UTC 24
Peak memory 259928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857570101 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.857570101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_smoke.2947466506
Short name T1
Test name
Test status
Simulation time 28795685 ps
CPU time 1.29 seconds
Started Sep 11 09:50:50 AM UTC 24
Finished Sep 11 09:50:52 AM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947466506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_smoke.2947466506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/0.edn_stress_all.2396777726
Short name T6
Test name
Test status
Simulation time 1281444432 ps
CPU time 5.61 seconds
Started Sep 11 09:50:51 AM UTC 24
Finished Sep 11 09:50:58 AM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396777726 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2396777726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_alert_test.2151540020
Short name T67
Test name
Test status
Simulation time 22303401 ps
CPU time 1.51 seconds
Started Sep 11 09:51:01 AM UTC 24
Finished Sep 11 09:51:03 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151540020 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2151540020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_disable.2825049855
Short name T56
Test name
Test status
Simulation time 18952591 ps
CPU time 1.36 seconds
Started Sep 11 09:50:59 AM UTC 24
Finished Sep 11 09:51:01 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825049855 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2825049855
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_genbits.2074455948
Short name T40
Test name
Test status
Simulation time 40948309 ps
CPU time 1.84 seconds
Started Sep 11 09:50:56 AM UTC 24
Finished Sep 11 09:50:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074455948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2074455948
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_regwen.3391976311
Short name T31
Test name
Test status
Simulation time 15809081 ps
CPU time 1.19 seconds
Started Sep 11 09:50:55 AM UTC 24
Finished Sep 11 09:50:58 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391976311 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.3391976311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_sec_cm.1223702483
Short name T20
Test name
Test status
Simulation time 1049494071 ps
CPU time 14.14 seconds
Started Sep 11 09:51:00 AM UTC 24
Finished Sep 11 09:51:15 AM UTC 24
Peak memory 262296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223702483 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1223702483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_smoke.2453385837
Short name T30
Test name
Test status
Simulation time 18185322 ps
CPU time 1.47 seconds
Started Sep 11 09:50:54 AM UTC 24
Finished Sep 11 09:50:57 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453385837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.2453385837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_stress_all.1126975650
Short name T60
Test name
Test status
Simulation time 467599690 ps
CPU time 2.8 seconds
Started Sep 11 09:50:57 AM UTC 24
Finished Sep 11 09:51:01 AM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126975650 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1126975650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.183223336
Short name T233
Test name
Test status
Simulation time 6168258697 ps
CPU time 165.54 seconds
Started Sep 11 09:50:57 AM UTC 24
Finished Sep 11 09:53:46 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=183223336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_w
ith_rand_reset.183223336
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_alert.406450735
Short name T227
Test name
Test status
Simulation time 27179113 ps
CPU time 1.94 seconds
Started Sep 11 09:52:11 AM UTC 24
Finished Sep 11 09:52:14 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406450735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.edn_alert.406450735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_alert_test.1919651821
Short name T354
Test name
Test status
Simulation time 27112514 ps
CPU time 1.16 seconds
Started Sep 11 09:52:12 AM UTC 24
Finished Sep 11 09:52:15 AM UTC 24
Peak memory 216232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919651821 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1919651821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.3865302154
Short name T119
Test name
Test status
Simulation time 89462089 ps
CPU time 1.66 seconds
Started Sep 11 09:52:12 AM UTC 24
Finished Sep 11 09:52:15 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865302154 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.3865302154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_err.1806167397
Short name T353
Test name
Test status
Simulation time 18381178 ps
CPU time 1.54 seconds
Started Sep 11 09:52:11 AM UTC 24
Finished Sep 11 09:52:14 AM UTC 24
Peak memory 237328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806167397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.1806167397
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_genbits.39753449
Short name T80
Test name
Test status
Simulation time 92485174 ps
CPU time 1.72 seconds
Started Sep 11 09:52:09 AM UTC 24
Finished Sep 11 09:52:12 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39753449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.edn_genbits.39753449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_intr.3541518751
Short name T352
Test name
Test status
Simulation time 30088926 ps
CPU time 1.32 seconds
Started Sep 11 09:52:11 AM UTC 24
Finished Sep 11 09:52:13 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541518751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.3541518751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_smoke.2148925024
Short name T239
Test name
Test status
Simulation time 16558895 ps
CPU time 1.28 seconds
Started Sep 11 09:52:08 AM UTC 24
Finished Sep 11 09:52:10 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148925024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.2148925024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/10.edn_stress_all.2874661410
Short name T242
Test name
Test status
Simulation time 161349266 ps
CPU time 1.35 seconds
Started Sep 11 09:52:09 AM UTC 24
Finished Sep 11 09:52:11 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874661410 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2874661410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/100.edn_alert.317114778
Short name T694
Test name
Test status
Simulation time 23761653 ps
CPU time 1.63 seconds
Started Sep 11 09:58:00 AM UTC 24
Finished Sep 11 09:58:03 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317114778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 100.edn_alert.317114778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/100.edn_genbits.1347710506
Short name T692
Test name
Test status
Simulation time 66199826 ps
CPU time 1.5 seconds
Started Sep 11 09:58:00 AM UTC 24
Finished Sep 11 09:58:03 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347710506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1347710506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/101.edn_alert.37445825
Short name T695
Test name
Test status
Simulation time 52531614 ps
CPU time 1.52 seconds
Started Sep 11 09:58:02 AM UTC 24
Finished Sep 11 09:58:05 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37445825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 101.edn_alert.37445825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/101.edn_genbits.1167404544
Short name T697
Test name
Test status
Simulation time 43249551 ps
CPU time 2.28 seconds
Started Sep 11 09:58:02 AM UTC 24
Finished Sep 11 09:58:05 AM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167404544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1167404544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/102.edn_alert.3465009218
Short name T698
Test name
Test status
Simulation time 25167576 ps
CPU time 1.79 seconds
Started Sep 11 09:58:03 AM UTC 24
Finished Sep 11 09:58:06 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465009218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.3465009218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/102.edn_genbits.2823387362
Short name T696
Test name
Test status
Simulation time 39590171 ps
CPU time 2.13 seconds
Started Sep 11 09:58:02 AM UTC 24
Finished Sep 11 09:58:05 AM UTC 24
Peak memory 231648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823387362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2823387362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/103.edn_alert.3103253151
Short name T704
Test name
Test status
Simulation time 39532652 ps
CPU time 1.66 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103253151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.3103253151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/103.edn_genbits.606825608
Short name T699
Test name
Test status
Simulation time 45775540 ps
CPU time 2.63 seconds
Started Sep 11 09:58:03 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 229508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606825608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 103.edn_genbits.606825608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/104.edn_alert.2653384430
Short name T702
Test name
Test status
Simulation time 74945678 ps
CPU time 1.59 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653384430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 104.edn_alert.2653384430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/104.edn_genbits.2719234336
Short name T705
Test name
Test status
Simulation time 50332872 ps
CPU time 2.04 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 229716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719234336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2719234336
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/105.edn_alert.314921822
Short name T701
Test name
Test status
Simulation time 57459153 ps
CPU time 1.57 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314921822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 105.edn_alert.314921822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/106.edn_alert.869561112
Short name T703
Test name
Test status
Simulation time 38049558 ps
CPU time 1.6 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869561112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 106.edn_alert.869561112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/106.edn_genbits.1344668391
Short name T700
Test name
Test status
Simulation time 63262175 ps
CPU time 1.41 seconds
Started Sep 11 09:58:04 AM UTC 24
Finished Sep 11 09:58:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344668391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1344668391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/107.edn_alert.4145963246
Short name T707
Test name
Test status
Simulation time 37104287 ps
CPU time 1.57 seconds
Started Sep 11 09:58:06 AM UTC 24
Finished Sep 11 09:58:09 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145963246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.4145963246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/108.edn_alert.3104024393
Short name T708
Test name
Test status
Simulation time 24409768 ps
CPU time 1.73 seconds
Started Sep 11 09:58:07 AM UTC 24
Finished Sep 11 09:58:09 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104024393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.edn_alert.3104024393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/108.edn_genbits.4046568603
Short name T709
Test name
Test status
Simulation time 55969354 ps
CPU time 2.99 seconds
Started Sep 11 09:58:06 AM UTC 24
Finished Sep 11 09:58:10 AM UTC 24
Peak memory 229448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046568603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4046568603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/109.edn_alert.2796419867
Short name T259
Test name
Test status
Simulation time 61303997 ps
CPU time 1.64 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 230360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796419867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.2796419867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/109.edn_genbits.3239116833
Short name T712
Test name
Test status
Simulation time 39686773 ps
CPU time 1.86 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 228316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239116833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3239116833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_alert_test.3475641935
Short name T356
Test name
Test status
Simulation time 26745144 ps
CPU time 1.27 seconds
Started Sep 11 09:52:20 AM UTC 24
Finished Sep 11 09:52:23 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475641935 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3475641935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_disable.1451107499
Short name T92
Test name
Test status
Simulation time 11434657 ps
CPU time 1.15 seconds
Started Sep 11 09:52:19 AM UTC 24
Finished Sep 11 09:52:21 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451107499 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1451107499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.2839663320
Short name T123
Test name
Test status
Simulation time 36172371 ps
CPU time 1.98 seconds
Started Sep 11 09:52:19 AM UTC 24
Finished Sep 11 09:52:22 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839663320 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.2839663320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_err.1342712027
Short name T195
Test name
Test status
Simulation time 35632577 ps
CPU time 1.17 seconds
Started Sep 11 09:52:18 AM UTC 24
Finished Sep 11 09:52:20 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342712027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.1342712027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_genbits.266136846
Short name T342
Test name
Test status
Simulation time 45978854 ps
CPU time 2.17 seconds
Started Sep 11 09:52:15 AM UTC 24
Finished Sep 11 09:52:18 AM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266136846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_genbits.266136846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_smoke.248634939
Short name T313
Test name
Test status
Simulation time 17610399 ps
CPU time 1.37 seconds
Started Sep 11 09:52:14 AM UTC 24
Finished Sep 11 09:52:17 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248634939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.edn_smoke.248634939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_stress_all.3289550323
Short name T120
Test name
Test status
Simulation time 325143981 ps
CPU time 5.07 seconds
Started Sep 11 09:52:15 AM UTC 24
Finished Sep 11 09:52:21 AM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289550323 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3289550323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.3637130728
Short name T39
Test name
Test status
Simulation time 6194415220 ps
CPU time 48.45 seconds
Started Sep 11 09:52:16 AM UTC 24
Finished Sep 11 09:53:06 AM UTC 24
Peak memory 234452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3637130728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all
_with_rand_reset.3637130728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/110.edn_alert.2567152368
Short name T714
Test name
Test status
Simulation time 96396043 ps
CPU time 1.84 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567152368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.2567152368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/110.edn_genbits.2033967481
Short name T710
Test name
Test status
Simulation time 48432849 ps
CPU time 1.58 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033967481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2033967481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/111.edn_alert.27735813
Short name T713
Test name
Test status
Simulation time 57435205 ps
CPU time 1.66 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27735813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 111.edn_alert.27735813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/111.edn_genbits.246572892
Short name T715
Test name
Test status
Simulation time 41974270 ps
CPU time 2 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246572892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 111.edn_genbits.246572892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/112.edn_genbits.3978641150
Short name T727
Test name
Test status
Simulation time 461087833 ps
CPU time 6.45 seconds
Started Sep 11 09:58:08 AM UTC 24
Finished Sep 11 09:58:16 AM UTC 24
Peak memory 231424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978641150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3978641150
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/113.edn_alert.2818569498
Short name T717
Test name
Test status
Simulation time 36001695 ps
CPU time 1.53 seconds
Started Sep 11 09:58:10 AM UTC 24
Finished Sep 11 09:58:13 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818569498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.2818569498
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/113.edn_genbits.3354162936
Short name T719
Test name
Test status
Simulation time 42137034 ps
CPU time 1.95 seconds
Started Sep 11 09:58:10 AM UTC 24
Finished Sep 11 09:58:13 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354162936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3354162936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/114.edn_alert.197529506
Short name T718
Test name
Test status
Simulation time 29116246 ps
CPU time 1.71 seconds
Started Sep 11 09:58:10 AM UTC 24
Finished Sep 11 09:58:13 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197529506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 114.edn_alert.197529506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/114.edn_genbits.4039946238
Short name T716
Test name
Test status
Simulation time 111181215 ps
CPU time 1.33 seconds
Started Sep 11 09:58:10 AM UTC 24
Finished Sep 11 09:58:13 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039946238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4039946238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/115.edn_alert.2284535730
Short name T721
Test name
Test status
Simulation time 42202269 ps
CPU time 1.55 seconds
Started Sep 11 09:58:11 AM UTC 24
Finished Sep 11 09:58:14 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284535730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.2284535730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/116.edn_alert.1534752130
Short name T310
Test name
Test status
Simulation time 45376499 ps
CPU time 1.71 seconds
Started Sep 11 09:58:11 AM UTC 24
Finished Sep 11 09:58:14 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534752130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.1534752130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/117.edn_genbits.1479502796
Short name T339
Test name
Test status
Simulation time 35267275 ps
CPU time 2.02 seconds
Started Sep 11 09:58:13 AM UTC 24
Finished Sep 11 09:58:16 AM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479502796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1479502796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/118.edn_alert.3323935324
Short name T724
Test name
Test status
Simulation time 24895036 ps
CPU time 1.27 seconds
Started Sep 11 09:58:13 AM UTC 24
Finished Sep 11 09:58:15 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323935324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.3323935324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/118.edn_genbits.2816799312
Short name T725
Test name
Test status
Simulation time 48905106 ps
CPU time 1.85 seconds
Started Sep 11 09:58:13 AM UTC 24
Finished Sep 11 09:58:16 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816799312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2816799312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/119.edn_alert.1453548127
Short name T301
Test name
Test status
Simulation time 131990850 ps
CPU time 1.67 seconds
Started Sep 11 09:58:14 AM UTC 24
Finished Sep 11 09:58:17 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453548127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.1453548127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/119.edn_genbits.1386099417
Short name T726
Test name
Test status
Simulation time 23604306 ps
CPU time 1.44 seconds
Started Sep 11 09:58:14 AM UTC 24
Finished Sep 11 09:58:16 AM UTC 24
Peak memory 227896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386099417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1386099417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_alert.2396179965
Short name T160
Test name
Test status
Simulation time 148721344 ps
CPU time 1.75 seconds
Started Sep 11 09:52:24 AM UTC 24
Finished Sep 11 09:52:26 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396179965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.2396179965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_alert_test.3460045968
Short name T358
Test name
Test status
Simulation time 52402903 ps
CPU time 1.23 seconds
Started Sep 11 09:52:26 AM UTC 24
Finished Sep 11 09:52:28 AM UTC 24
Peak memory 217084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460045968 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3460045968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_disable.2285336671
Short name T172
Test name
Test status
Simulation time 31069863 ps
CPU time 1.09 seconds
Started Sep 11 09:52:25 AM UTC 24
Finished Sep 11 09:52:27 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285336671 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2285336671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_err.36112922
Short name T216
Test name
Test status
Simulation time 31251692 ps
CPU time 1.33 seconds
Started Sep 11 09:52:24 AM UTC 24
Finished Sep 11 09:52:26 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36112922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 12.edn_err.36112922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_genbits.4144760104
Short name T357
Test name
Test status
Simulation time 81215544 ps
CPU time 2.03 seconds
Started Sep 11 09:52:21 AM UTC 24
Finished Sep 11 09:52:25 AM UTC 24
Peak memory 231772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144760104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4144760104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_intr.1532552826
Short name T36
Test name
Test status
Simulation time 35336903 ps
CPU time 1.17 seconds
Started Sep 11 09:52:23 AM UTC 24
Finished Sep 11 09:52:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532552826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.1532552826
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_smoke.2375738496
Short name T355
Test name
Test status
Simulation time 16074712 ps
CPU time 1.24 seconds
Started Sep 11 09:52:20 AM UTC 24
Finished Sep 11 09:52:23 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375738496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.2375738496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_stress_all.1136566939
Short name T298
Test name
Test status
Simulation time 266035201 ps
CPU time 2.36 seconds
Started Sep 11 09:52:21 AM UTC 24
Finished Sep 11 09:52:25 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136566939 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1136566939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.963779881
Short name T237
Test name
Test status
Simulation time 47917189139 ps
CPU time 134.22 seconds
Started Sep 11 09:52:22 AM UTC 24
Finished Sep 11 09:54:40 AM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=963779881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_
with_rand_reset.963779881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/120.edn_genbits.1565575044
Short name T728
Test name
Test status
Simulation time 58995753 ps
CPU time 2.37 seconds
Started Sep 11 09:58:14 AM UTC 24
Finished Sep 11 09:58:17 AM UTC 24
Peak memory 231504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565575044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1565575044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/121.edn_alert.1459960331
Short name T729
Test name
Test status
Simulation time 146152392 ps
CPU time 1.24 seconds
Started Sep 11 09:58:15 AM UTC 24
Finished Sep 11 09:58:17 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459960331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.1459960331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/121.edn_genbits.2957102128
Short name T733
Test name
Test status
Simulation time 51407722 ps
CPU time 1.99 seconds
Started Sep 11 09:58:15 AM UTC 24
Finished Sep 11 09:58:18 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957102128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2957102128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/122.edn_alert.1291630705
Short name T730
Test name
Test status
Simulation time 30740443 ps
CPU time 1.61 seconds
Started Sep 11 09:58:15 AM UTC 24
Finished Sep 11 09:58:18 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291630705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 122.edn_alert.1291630705
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/122.edn_genbits.3226611118
Short name T734
Test name
Test status
Simulation time 37702188 ps
CPU time 1.92 seconds
Started Sep 11 09:58:15 AM UTC 24
Finished Sep 11 09:58:18 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226611118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3226611118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/123.edn_alert.2747271036
Short name T731
Test name
Test status
Simulation time 32290176 ps
CPU time 1.6 seconds
Started Sep 11 09:58:15 AM UTC 24
Finished Sep 11 09:58:18 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747271036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.2747271036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/123.edn_genbits.61807067
Short name T732
Test name
Test status
Simulation time 55861599 ps
CPU time 1.69 seconds
Started Sep 11 09:58:15 AM UTC 24
Finished Sep 11 09:58:18 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61807067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 123.edn_genbits.61807067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/124.edn_alert.1754748750
Short name T292
Test name
Test status
Simulation time 59659683 ps
CPU time 1.63 seconds
Started Sep 11 09:58:16 AM UTC 24
Finished Sep 11 09:58:19 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754748750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.1754748750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/124.edn_genbits.1002996972
Short name T736
Test name
Test status
Simulation time 78670660 ps
CPU time 1.58 seconds
Started Sep 11 09:58:16 AM UTC 24
Finished Sep 11 09:58:19 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002996972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1002996972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/125.edn_alert.1531433258
Short name T735
Test name
Test status
Simulation time 25845898 ps
CPU time 1.24 seconds
Started Sep 11 09:58:17 AM UTC 24
Finished Sep 11 09:58:19 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531433258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.1531433258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/125.edn_genbits.1266609415
Short name T738
Test name
Test status
Simulation time 46042625 ps
CPU time 1.55 seconds
Started Sep 11 09:58:16 AM UTC 24
Finished Sep 11 09:58:19 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266609415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1266609415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/126.edn_alert.950446972
Short name T739
Test name
Test status
Simulation time 40618989 ps
CPU time 1.3 seconds
Started Sep 11 09:58:18 AM UTC 24
Finished Sep 11 09:58:20 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950446972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 126.edn_alert.950446972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/126.edn_genbits.2978968795
Short name T737
Test name
Test status
Simulation time 84902216 ps
CPU time 1.46 seconds
Started Sep 11 09:58:17 AM UTC 24
Finished Sep 11 09:58:19 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978968795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2978968795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/127.edn_alert.1844050524
Short name T740
Test name
Test status
Simulation time 103711931 ps
CPU time 1.35 seconds
Started Sep 11 09:58:18 AM UTC 24
Finished Sep 11 09:58:20 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844050524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.1844050524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/127.edn_genbits.3670503347
Short name T741
Test name
Test status
Simulation time 34675819 ps
CPU time 1.63 seconds
Started Sep 11 09:58:18 AM UTC 24
Finished Sep 11 09:58:20 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670503347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3670503347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/128.edn_alert.3827798040
Short name T744
Test name
Test status
Simulation time 25954149 ps
CPU time 1.19 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:21 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827798040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.3827798040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/128.edn_genbits.95544799
Short name T743
Test name
Test status
Simulation time 51267052 ps
CPU time 1.81 seconds
Started Sep 11 09:58:18 AM UTC 24
Finished Sep 11 09:58:21 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95544799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 128.edn_genbits.95544799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/129.edn_alert.4112889748
Short name T746
Test name
Test status
Simulation time 24838007 ps
CPU time 1.36 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112889748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 129.edn_alert.4112889748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/129.edn_genbits.3756525503
Short name T745
Test name
Test status
Simulation time 110733466 ps
CPU time 1.4 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756525503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3756525503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_alert_test.4286636138
Short name T361
Test name
Test status
Simulation time 17907511 ps
CPU time 1.38 seconds
Started Sep 11 09:52:31 AM UTC 24
Finished Sep 11 09:52:33 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286636138 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4286636138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_disable.1370723128
Short name T55
Test name
Test status
Simulation time 10359205 ps
CPU time 1.13 seconds
Started Sep 11 09:52:30 AM UTC 24
Finished Sep 11 09:52:32 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370723128 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1370723128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_genbits.1300554429
Short name T304
Test name
Test status
Simulation time 48278262 ps
CPU time 1.67 seconds
Started Sep 11 09:52:27 AM UTC 24
Finished Sep 11 09:52:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300554429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1300554429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_intr.3036673425
Short name T360
Test name
Test status
Simulation time 21109528 ps
CPU time 1.43 seconds
Started Sep 11 09:52:28 AM UTC 24
Finished Sep 11 09:52:31 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036673425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.3036673425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_smoke.3601879336
Short name T359
Test name
Test status
Simulation time 14371002 ps
CPU time 1.27 seconds
Started Sep 11 09:52:27 AM UTC 24
Finished Sep 11 09:52:29 AM UTC 24
Peak memory 226264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601879336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.3601879336
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/13.edn_stress_all.2882020703
Short name T250
Test name
Test status
Simulation time 260853607 ps
CPU time 7.34 seconds
Started Sep 11 09:52:27 AM UTC 24
Finished Sep 11 09:52:35 AM UTC 24
Peak memory 229660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882020703 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2882020703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/130.edn_alert.2996080549
Short name T260
Test name
Test status
Simulation time 55363675 ps
CPU time 1.74 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 230384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996080549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.2996080549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/130.edn_genbits.270746354
Short name T750
Test name
Test status
Simulation time 35466916 ps
CPU time 1.7 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 230336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270746354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 130.edn_genbits.270746354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/131.edn_alert.3437454124
Short name T749
Test name
Test status
Simulation time 90021891 ps
CPU time 1.36 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437454124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.3437454124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/131.edn_genbits.837819175
Short name T748
Test name
Test status
Simulation time 22519364 ps
CPU time 1.51 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837819175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 131.edn_genbits.837819175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/132.edn_genbits.1370034099
Short name T747
Test name
Test status
Simulation time 19746029 ps
CPU time 1.19 seconds
Started Sep 11 09:58:19 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370034099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1370034099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/133.edn_alert.694766591
Short name T753
Test name
Test status
Simulation time 26538640 ps
CPU time 1.35 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:23 AM UTC 24
Peak memory 230476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694766591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 133.edn_alert.694766591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/133.edn_genbits.870000945
Short name T319
Test name
Test status
Simulation time 107200018 ps
CPU time 2.43 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:24 AM UTC 24
Peak memory 231492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870000945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 133.edn_genbits.870000945
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/134.edn_alert.766655228
Short name T752
Test name
Test status
Simulation time 115384492 ps
CPU time 1.16 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:23 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766655228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 134.edn_alert.766655228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/134.edn_genbits.1748030493
Short name T757
Test name
Test status
Simulation time 46529705 ps
CPU time 2.07 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:24 AM UTC 24
Peak memory 229716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748030493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1748030493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/135.edn_alert.1657599933
Short name T755
Test name
Test status
Simulation time 40313597 ps
CPU time 1.53 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:24 AM UTC 24
Peak memory 230416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657599933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.1657599933
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/135.edn_genbits.57360256
Short name T756
Test name
Test status
Simulation time 37633771 ps
CPU time 1.76 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:24 AM UTC 24
Peak memory 228280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57360256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 135.edn_genbits.57360256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/136.edn_alert.4264725449
Short name T754
Test name
Test status
Simulation time 165315526 ps
CPU time 1.17 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:23 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264725449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.4264725449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/136.edn_genbits.3688087635
Short name T758
Test name
Test status
Simulation time 35534330 ps
CPU time 1.87 seconds
Started Sep 11 09:58:21 AM UTC 24
Finished Sep 11 09:58:24 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688087635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3688087635
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/137.edn_alert.2390512499
Short name T762
Test name
Test status
Simulation time 341028956 ps
CPU time 1.64 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390512499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.2390512499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/138.edn_alert.3991102016
Short name T761
Test name
Test status
Simulation time 30404884 ps
CPU time 1.31 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991102016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.3991102016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/138.edn_genbits.3984751162
Short name T763
Test name
Test status
Simulation time 48314468 ps
CPU time 1.71 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984751162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3984751162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/139.edn_alert.3335452589
Short name T760
Test name
Test status
Simulation time 46121325 ps
CPU time 1.18 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335452589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.3335452589
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_alert.2421774738
Short name T88
Test name
Test status
Simulation time 86960317 ps
CPU time 1.54 seconds
Started Sep 11 09:52:34 AM UTC 24
Finished Sep 11 09:52:37 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421774738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.2421774738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_alert_test.304136065
Short name T363
Test name
Test status
Simulation time 24124967 ps
CPU time 1.31 seconds
Started Sep 11 09:52:37 AM UTC 24
Finished Sep 11 09:52:40 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304136065 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.304136065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_disable.4104100713
Short name T95
Test name
Test status
Simulation time 38188228 ps
CPU time 1.35 seconds
Started Sep 11 09:52:36 AM UTC 24
Finished Sep 11 09:52:38 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104100713 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.4104100713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.667967343
Short name T163
Test name
Test status
Simulation time 45374433 ps
CPU time 1.91 seconds
Started Sep 11 09:52:37 AM UTC 24
Finished Sep 11 09:52:40 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667967343 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.667967343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_err.4110731942
Short name T182
Test name
Test status
Simulation time 36625332 ps
CPU time 1.6 seconds
Started Sep 11 09:52:35 AM UTC 24
Finished Sep 11 09:52:38 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110731942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.4110731942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_genbits.2270530156
Short name T131
Test name
Test status
Simulation time 64368357 ps
CPU time 1.99 seconds
Started Sep 11 09:52:33 AM UTC 24
Finished Sep 11 09:52:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270530156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2270530156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_intr.933166865
Short name T104
Test name
Test status
Simulation time 24661079 ps
CPU time 1.47 seconds
Started Sep 11 09:52:34 AM UTC 24
Finished Sep 11 09:52:37 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933166865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.933166865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/14.edn_smoke.1738138198
Short name T362
Test name
Test status
Simulation time 37346648 ps
CPU time 1.28 seconds
Started Sep 11 09:52:32 AM UTC 24
Finished Sep 11 09:52:34 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738138198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.1738138198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/140.edn_alert.3113187416
Short name T768
Test name
Test status
Simulation time 50736528 ps
CPU time 1.58 seconds
Started Sep 11 09:58:24 AM UTC 24
Finished Sep 11 09:58:26 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113187416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.3113187416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/140.edn_genbits.164083808
Short name T764
Test name
Test status
Simulation time 55038860 ps
CPU time 1.76 seconds
Started Sep 11 09:58:22 AM UTC 24
Finished Sep 11 09:58:25 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164083808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 140.edn_genbits.164083808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/141.edn_alert.648936899
Short name T766
Test name
Test status
Simulation time 98978603 ps
CPU time 1.28 seconds
Started Sep 11 09:58:24 AM UTC 24
Finished Sep 11 09:58:26 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648936899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 141.edn_alert.648936899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/141.edn_genbits.3776867215
Short name T767
Test name
Test status
Simulation time 87466995 ps
CPU time 1.45 seconds
Started Sep 11 09:58:24 AM UTC 24
Finished Sep 11 09:58:26 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776867215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3776867215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/142.edn_alert.3420390205
Short name T293
Test name
Test status
Simulation time 58488205 ps
CPU time 1.2 seconds
Started Sep 11 09:58:24 AM UTC 24
Finished Sep 11 09:58:26 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420390205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.3420390205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/142.edn_genbits.3150339459
Short name T769
Test name
Test status
Simulation time 44756855 ps
CPU time 1.54 seconds
Started Sep 11 09:58:24 AM UTC 24
Finished Sep 11 09:58:26 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150339459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3150339459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/143.edn_genbits.3716178903
Short name T770
Test name
Test status
Simulation time 38962328 ps
CPU time 1.97 seconds
Started Sep 11 09:58:24 AM UTC 24
Finished Sep 11 09:58:27 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716178903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3716178903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/144.edn_alert.773924942
Short name T772
Test name
Test status
Simulation time 212171936 ps
CPU time 1.52 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:27 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773924942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 144.edn_alert.773924942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/144.edn_genbits.298098099
Short name T773
Test name
Test status
Simulation time 71609585 ps
CPU time 1.68 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:28 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298098099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 144.edn_genbits.298098099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/145.edn_alert.330724606
Short name T771
Test name
Test status
Simulation time 26512043 ps
CPU time 1.15 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:27 AM UTC 24
Peak memory 230480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330724606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 145.edn_alert.330724606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/145.edn_genbits.1782258231
Short name T775
Test name
Test status
Simulation time 81405951 ps
CPU time 1.99 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:28 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782258231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1782258231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/146.edn_alert.2670319600
Short name T774
Test name
Test status
Simulation time 136408017 ps
CPU time 1.53 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:28 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670319600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.2670319600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/146.edn_genbits.2102395848
Short name T326
Test name
Test status
Simulation time 51674174 ps
CPU time 2.57 seconds
Started Sep 11 09:58:25 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102395848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2102395848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/147.edn_alert.3244813363
Short name T777
Test name
Test status
Simulation time 46790184 ps
CPU time 1.4 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244813363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.3244813363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/147.edn_genbits.2608052659
Short name T787
Test name
Test status
Simulation time 155913182 ps
CPU time 3.23 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 231480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608052659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2608052659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/148.edn_alert.3925837556
Short name T780
Test name
Test status
Simulation time 25101398 ps
CPU time 1.74 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925837556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.3925837556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/148.edn_genbits.865954896
Short name T779
Test name
Test status
Simulation time 92961715 ps
CPU time 1.54 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865954896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 148.edn_genbits.865954896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/149.edn_alert.3974437962
Short name T778
Test name
Test status
Simulation time 37078765 ps
CPU time 1.2 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974437962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.3974437962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/149.edn_genbits.1845709912
Short name T776
Test name
Test status
Simulation time 76324159 ps
CPU time 1.36 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845709912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1845709912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_alert.1711269713
Short name T173
Test name
Test status
Simulation time 88848198 ps
CPU time 1.38 seconds
Started Sep 11 09:52:41 AM UTC 24
Finished Sep 11 09:52:43 AM UTC 24
Peak memory 230480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711269713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.1711269713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_alert_test.3755066813
Short name T367
Test name
Test status
Simulation time 52280922 ps
CPU time 1.28 seconds
Started Sep 11 09:52:44 AM UTC 24
Finished Sep 11 09:52:46 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755066813 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3755066813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_disable.3369335445
Short name T178
Test name
Test status
Simulation time 13845175 ps
CPU time 1.4 seconds
Started Sep 11 09:52:43 AM UTC 24
Finished Sep 11 09:52:45 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369335445 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3369335445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.1452083643
Short name T82
Test name
Test status
Simulation time 30384131 ps
CPU time 1.68 seconds
Started Sep 11 09:52:44 AM UTC 24
Finished Sep 11 09:52:47 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452083643 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.1452083643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_err.520551917
Short name T366
Test name
Test status
Simulation time 32296291 ps
CPU time 1.32 seconds
Started Sep 11 09:52:42 AM UTC 24
Finished Sep 11 09:52:44 AM UTC 24
Peak memory 237136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520551917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.edn_err.520551917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_genbits.1453063039
Short name T74
Test name
Test status
Simulation time 117691324 ps
CPU time 1.64 seconds
Started Sep 11 09:52:38 AM UTC 24
Finished Sep 11 09:52:41 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453063039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1453063039
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_intr.1259947551
Short name T365
Test name
Test status
Simulation time 35041172 ps
CPU time 1.35 seconds
Started Sep 11 09:52:41 AM UTC 24
Finished Sep 11 09:52:43 AM UTC 24
Peak memory 237200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259947551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.1259947551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_smoke.2729753475
Short name T364
Test name
Test status
Simulation time 46253872 ps
CPU time 1.34 seconds
Started Sep 11 09:52:37 AM UTC 24
Finished Sep 11 09:52:40 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729753475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.2729753475
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_stress_all.2226952949
Short name T121
Test name
Test status
Simulation time 108825811 ps
CPU time 3.42 seconds
Started Sep 11 09:52:39 AM UTC 24
Finished Sep 11 09:52:44 AM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226952949 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2226952949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.3485725570
Short name T232
Test name
Test status
Simulation time 4387549757 ps
CPU time 58.93 seconds
Started Sep 11 09:52:41 AM UTC 24
Finished Sep 11 09:53:41 AM UTC 24
Peak memory 229980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3485725570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all
_with_rand_reset.3485725570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/150.edn_alert.916294852
Short name T781
Test name
Test status
Simulation time 24786929 ps
CPU time 1.33 seconds
Started Sep 11 09:58:27 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916294852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 150.edn_alert.916294852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/150.edn_genbits.2454775597
Short name T329
Test name
Test status
Simulation time 122785110 ps
CPU time 1.55 seconds
Started Sep 11 09:58:26 AM UTC 24
Finished Sep 11 09:58:29 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454775597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2454775597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/151.edn_alert.899237293
Short name T783
Test name
Test status
Simulation time 131118372 ps
CPU time 1.6 seconds
Started Sep 11 09:58:28 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899237293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 151.edn_alert.899237293
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/151.edn_genbits.2579462313
Short name T782
Test name
Test status
Simulation time 32849845 ps
CPU time 1.56 seconds
Started Sep 11 09:58:27 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579462313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2579462313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/152.edn_alert.2682299550
Short name T786
Test name
Test status
Simulation time 404108852 ps
CPU time 1.75 seconds
Started Sep 11 09:58:28 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682299550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.2682299550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/152.edn_genbits.3297436098
Short name T788
Test name
Test status
Simulation time 116580765 ps
CPU time 2.41 seconds
Started Sep 11 09:58:28 AM UTC 24
Finished Sep 11 09:58:31 AM UTC 24
Peak memory 231620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297436098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3297436098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/153.edn_alert.4169920027
Short name T784
Test name
Test status
Simulation time 33508356 ps
CPU time 1.46 seconds
Started Sep 11 09:58:28 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169920027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.4169920027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/153.edn_genbits.3904472801
Short name T785
Test name
Test status
Simulation time 55558742 ps
CPU time 1.65 seconds
Started Sep 11 09:58:28 AM UTC 24
Finished Sep 11 09:58:30 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904472801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3904472801
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/154.edn_genbits.2295944964
Short name T792
Test name
Test status
Simulation time 53859023 ps
CPU time 2.15 seconds
Started Sep 11 09:58:29 AM UTC 24
Finished Sep 11 09:58:32 AM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295944964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2295944964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/155.edn_alert.4143697865
Short name T790
Test name
Test status
Simulation time 29720466 ps
CPU time 1.5 seconds
Started Sep 11 09:58:29 AM UTC 24
Finished Sep 11 09:58:32 AM UTC 24
Peak memory 230452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143697865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.4143697865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/155.edn_genbits.3398749365
Short name T791
Test name
Test status
Simulation time 38251474 ps
CPU time 1.6 seconds
Started Sep 11 09:58:29 AM UTC 24
Finished Sep 11 09:58:32 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398749365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3398749365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/156.edn_genbits.2321989094
Short name T789
Test name
Test status
Simulation time 37243481 ps
CPU time 1.38 seconds
Started Sep 11 09:58:29 AM UTC 24
Finished Sep 11 09:58:32 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321989094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2321989094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/157.edn_alert.3070007586
Short name T797
Test name
Test status
Simulation time 43869252 ps
CPU time 1.55 seconds
Started Sep 11 09:58:30 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070007586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.3070007586
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/157.edn_genbits.2834150281
Short name T795
Test name
Test status
Simulation time 32993386 ps
CPU time 1.47 seconds
Started Sep 11 09:58:30 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 228608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834150281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2834150281
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/158.edn_alert.3801781593
Short name T798
Test name
Test status
Simulation time 40841729 ps
CPU time 1.6 seconds
Started Sep 11 09:58:30 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801781593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.3801781593
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/158.edn_genbits.1649793807
Short name T793
Test name
Test status
Simulation time 39704708 ps
CPU time 0.99 seconds
Started Sep 11 09:58:30 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649793807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1649793807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/159.edn_alert.3270755847
Short name T799
Test name
Test status
Simulation time 72448543 ps
CPU time 1.57 seconds
Started Sep 11 09:58:31 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270755847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 159.edn_alert.3270755847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/159.edn_genbits.2857631999
Short name T810
Test name
Test status
Simulation time 582348203 ps
CPU time 4.22 seconds
Started Sep 11 09:58:30 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 231568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857631999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2857631999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_alert_test.4103573332
Short name T370
Test name
Test status
Simulation time 16666827 ps
CPU time 1.37 seconds
Started Sep 11 09:52:53 AM UTC 24
Finished Sep 11 09:52:55 AM UTC 24
Peak memory 216860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103573332 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4103573332
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_disable.2452093511
Short name T96
Test name
Test status
Simulation time 55812921 ps
CPU time 1.14 seconds
Started Sep 11 09:52:51 AM UTC 24
Finished Sep 11 09:52:53 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452093511 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2452093511
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.3364414652
Short name T168
Test name
Test status
Simulation time 27932746 ps
CPU time 1.59 seconds
Started Sep 11 09:52:52 AM UTC 24
Finished Sep 11 09:52:54 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364414652 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.3364414652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_err.2511514762
Short name T170
Test name
Test status
Simulation time 159393213 ps
CPU time 1.79 seconds
Started Sep 11 09:52:48 AM UTC 24
Finished Sep 11 09:52:51 AM UTC 24
Peak memory 242060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511514762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.2511514762
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_genbits.2189447033
Short name T51
Test name
Test status
Simulation time 78708503 ps
CPU time 1.74 seconds
Started Sep 11 09:52:45 AM UTC 24
Finished Sep 11 09:52:48 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189447033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2189447033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_intr.2365768186
Short name T47
Test name
Test status
Simulation time 37373397 ps
CPU time 1.13 seconds
Started Sep 11 09:52:47 AM UTC 24
Finished Sep 11 09:52:49 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365768186 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.2365768186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_smoke.2513157805
Short name T368
Test name
Test status
Simulation time 61502194 ps
CPU time 1.21 seconds
Started Sep 11 09:52:45 AM UTC 24
Finished Sep 11 09:52:47 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513157805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.2513157805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/16.edn_stress_all.2608687933
Short name T300
Test name
Test status
Simulation time 281282097 ps
CPU time 4.54 seconds
Started Sep 11 09:52:46 AM UTC 24
Finished Sep 11 09:52:52 AM UTC 24
Peak memory 229744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608687933 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2608687933
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/160.edn_alert.394146154
Short name T800
Test name
Test status
Simulation time 24420268 ps
CPU time 1.28 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:34 AM UTC 24
Peak memory 228432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394146154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 160.edn_alert.394146154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/160.edn_genbits.2694152162
Short name T796
Test name
Test status
Simulation time 46371829 ps
CPU time 1.32 seconds
Started Sep 11 09:58:31 AM UTC 24
Finished Sep 11 09:58:33 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694152162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2694152162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/161.edn_alert.1361154505
Short name T802
Test name
Test status
Simulation time 45880438 ps
CPU time 1.64 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:34 AM UTC 24
Peak memory 228380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361154505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.1361154505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/161.edn_genbits.1682633820
Short name T804
Test name
Test status
Simulation time 66358792 ps
CPU time 1.89 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:35 AM UTC 24
Peak memory 228540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682633820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1682633820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/162.edn_alert.615378477
Short name T805
Test name
Test status
Simulation time 24977490 ps
CPU time 1.73 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:35 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615378477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 162.edn_alert.615378477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/162.edn_genbits.3466435991
Short name T806
Test name
Test status
Simulation time 63276910 ps
CPU time 1.85 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:35 AM UTC 24
Peak memory 230656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466435991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3466435991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/163.edn_alert.71039249
Short name T803
Test name
Test status
Simulation time 49709648 ps
CPU time 1.57 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:35 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71039249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 163.edn_alert.71039249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/163.edn_genbits.289554040
Short name T801
Test name
Test status
Simulation time 28910623 ps
CPU time 1.38 seconds
Started Sep 11 09:58:32 AM UTC 24
Finished Sep 11 09:58:34 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289554040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 163.edn_genbits.289554040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/164.edn_alert.4045524810
Short name T194
Test name
Test status
Simulation time 83805345 ps
CPU time 1.6 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045524810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.4045524810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/164.edn_genbits.120574889
Short name T807
Test name
Test status
Simulation time 132670705 ps
CPU time 1.5 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120574889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 164.edn_genbits.120574889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/165.edn_alert.3178560882
Short name T808
Test name
Test status
Simulation time 103554468 ps
CPU time 1.47 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178560882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.3178560882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/165.edn_genbits.1181717988
Short name T809
Test name
Test status
Simulation time 71152662 ps
CPU time 1.44 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181717988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1181717988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/166.edn_alert.2426544059
Short name T811
Test name
Test status
Simulation time 24581390 ps
CPU time 1.49 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426544059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.2426544059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/166.edn_genbits.3326955845
Short name T812
Test name
Test status
Simulation time 37554737 ps
CPU time 1.73 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326955845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3326955845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/167.edn_alert.4086865321
Short name T815
Test name
Test status
Simulation time 40672283 ps
CPU time 1.58 seconds
Started Sep 11 09:58:34 AM UTC 24
Finished Sep 11 09:58:37 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086865321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.4086865321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/167.edn_genbits.1964517997
Short name T813
Test name
Test status
Simulation time 61288235 ps
CPU time 1.66 seconds
Started Sep 11 09:58:33 AM UTC 24
Finished Sep 11 09:58:36 AM UTC 24
Peak memory 230376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964517997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1964517997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/168.edn_alert.3231598583
Short name T765
Test name
Test status
Simulation time 27287188 ps
CPU time 1.31 seconds
Started Sep 11 09:58:35 AM UTC 24
Finished Sep 11 09:58:37 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231598583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 168.edn_alert.3231598583
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/168.edn_genbits.607428171
Short name T814
Test name
Test status
Simulation time 60158749 ps
CPU time 1.25 seconds
Started Sep 11 09:58:34 AM UTC 24
Finished Sep 11 09:58:37 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607428171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 168.edn_genbits.607428171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/169.edn_alert.3052171193
Short name T742
Test name
Test status
Simulation time 87939279 ps
CPU time 1.14 seconds
Started Sep 11 09:58:35 AM UTC 24
Finished Sep 11 09:58:37 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052171193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.3052171193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/169.edn_genbits.709901712
Short name T816
Test name
Test status
Simulation time 87364838 ps
CPU time 1.62 seconds
Started Sep 11 09:58:35 AM UTC 24
Finished Sep 11 09:58:37 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709901712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.edn_genbits.709901712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_alert.4184387687
Short name T297
Test name
Test status
Simulation time 57914980 ps
CPU time 1.51 seconds
Started Sep 11 09:52:57 AM UTC 24
Finished Sep 11 09:53:00 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184387687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.4184387687
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_alert_test.2458180793
Short name T373
Test name
Test status
Simulation time 107947583 ps
CPU time 1.27 seconds
Started Sep 11 09:53:02 AM UTC 24
Finished Sep 11 09:53:05 AM UTC 24
Peak memory 226736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458180793 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2458180793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_disable.35109495
Short name T89
Test name
Test status
Simulation time 42724306 ps
CPU time 1.19 seconds
Started Sep 11 09:53:00 AM UTC 24
Finished Sep 11 09:53:02 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35109495 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.35109495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.281409632
Short name T229
Test name
Test status
Simulation time 32393893 ps
CPU time 1.4 seconds
Started Sep 11 09:53:01 AM UTC 24
Finished Sep 11 09:53:04 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281409632 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.281409632
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_err.2023816879
Short name T183
Test name
Test status
Simulation time 116636539 ps
CPU time 1.5 seconds
Started Sep 11 09:52:59 AM UTC 24
Finished Sep 11 09:53:02 AM UTC 24
Peak memory 242296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023816879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.2023816879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_genbits.644843466
Short name T371
Test name
Test status
Simulation time 40639452 ps
CPU time 1.78 seconds
Started Sep 11 09:52:54 AM UTC 24
Finished Sep 11 09:52:56 AM UTC 24
Peak memory 228636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644843466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_genbits.644843466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_intr.1702687958
Short name T372
Test name
Test status
Simulation time 20408035 ps
CPU time 1.54 seconds
Started Sep 11 09:52:56 AM UTC 24
Finished Sep 11 09:52:59 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702687958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.1702687958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_smoke.2999213319
Short name T369
Test name
Test status
Simulation time 17825451 ps
CPU time 1.3 seconds
Started Sep 11 09:52:53 AM UTC 24
Finished Sep 11 09:52:55 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999213319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.2999213319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_stress_all.3697167620
Short name T251
Test name
Test status
Simulation time 173962762 ps
CPU time 4.52 seconds
Started Sep 11 09:52:55 AM UTC 24
Finished Sep 11 09:53:00 AM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697167620 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3697167620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.1848402210
Short name T234
Test name
Test status
Simulation time 2318767384 ps
CPU time 61.87 seconds
Started Sep 11 09:52:56 AM UTC 24
Finished Sep 11 09:54:00 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1848402210 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all
_with_rand_reset.1848402210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/170.edn_alert.3341915695
Short name T818
Test name
Test status
Simulation time 27122126 ps
CPU time 1.42 seconds
Started Sep 11 09:58:36 AM UTC 24
Finished Sep 11 09:58:38 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341915695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.3341915695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/170.edn_genbits.2189174668
Short name T820
Test name
Test status
Simulation time 342132491 ps
CPU time 2.71 seconds
Started Sep 11 09:58:35 AM UTC 24
Finished Sep 11 09:58:38 AM UTC 24
Peak memory 231488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189174668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2189174668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/171.edn_alert.1901594015
Short name T821
Test name
Test status
Simulation time 37282347 ps
CPU time 1.6 seconds
Started Sep 11 09:58:36 AM UTC 24
Finished Sep 11 09:58:39 AM UTC 24
Peak memory 232508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901594015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.1901594015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/171.edn_genbits.1470497472
Short name T817
Test name
Test status
Simulation time 53698467 ps
CPU time 1.13 seconds
Started Sep 11 09:58:36 AM UTC 24
Finished Sep 11 09:58:38 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470497472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1470497472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/172.edn_alert.2094149544
Short name T822
Test name
Test status
Simulation time 32813407 ps
CPU time 1.45 seconds
Started Sep 11 09:58:36 AM UTC 24
Finished Sep 11 09:58:39 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094149544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.2094149544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/172.edn_genbits.948467336
Short name T327
Test name
Test status
Simulation time 272696877 ps
CPU time 4.58 seconds
Started Sep 11 09:58:36 AM UTC 24
Finished Sep 11 09:58:42 AM UTC 24
Peak memory 231696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948467336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 172.edn_genbits.948467336
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/173.edn_alert.4226364914
Short name T825
Test name
Test status
Simulation time 26715374 ps
CPU time 1.45 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226364914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.4226364914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/173.edn_genbits.188997009
Short name T819
Test name
Test status
Simulation time 49547906 ps
CPU time 1.25 seconds
Started Sep 11 09:58:36 AM UTC 24
Finished Sep 11 09:58:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188997009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 173.edn_genbits.188997009
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/174.edn_alert.1639987615
Short name T826
Test name
Test status
Simulation time 39350784 ps
CPU time 1.34 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639987615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.1639987615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/174.edn_genbits.1061851889
Short name T827
Test name
Test status
Simulation time 51410549 ps
CPU time 1.66 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061851889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1061851889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/175.edn_alert.1948900163
Short name T824
Test name
Test status
Simulation time 27858329 ps
CPU time 1.25 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948900163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.1948900163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/175.edn_genbits.679878756
Short name T823
Test name
Test status
Simulation time 83832283 ps
CPU time 1.13 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:39 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679878756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 175.edn_genbits.679878756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/176.edn_alert.1946407751
Short name T828
Test name
Test status
Simulation time 130925251 ps
CPU time 1.57 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946407751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.1946407751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/176.edn_genbits.3534686447
Short name T830
Test name
Test status
Simulation time 50727857 ps
CPU time 1.69 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534686447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3534686447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/177.edn_alert.4018697297
Short name T829
Test name
Test status
Simulation time 32994257 ps
CPU time 1.57 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:40 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018697297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 177.edn_alert.4018697297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/177.edn_genbits.1646063518
Short name T835
Test name
Test status
Simulation time 63782649 ps
CPU time 2.63 seconds
Started Sep 11 09:58:37 AM UTC 24
Finished Sep 11 09:58:41 AM UTC 24
Peak memory 229432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646063518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1646063518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/178.edn_alert.653320005
Short name T833
Test name
Test status
Simulation time 31470552 ps
CPU time 1.3 seconds
Started Sep 11 09:58:38 AM UTC 24
Finished Sep 11 09:58:41 AM UTC 24
Peak memory 230480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653320005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 178.edn_alert.653320005
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/178.edn_genbits.1741687715
Short name T831
Test name
Test status
Simulation time 41859723 ps
CPU time 1.23 seconds
Started Sep 11 09:58:38 AM UTC 24
Finished Sep 11 09:58:41 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741687715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1741687715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/179.edn_alert.3485897778
Short name T834
Test name
Test status
Simulation time 67919971 ps
CPU time 1.36 seconds
Started Sep 11 09:58:39 AM UTC 24
Finished Sep 11 09:58:41 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485897778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 179.edn_alert.3485897778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/179.edn_genbits.661553983
Short name T843
Test name
Test status
Simulation time 91052394 ps
CPU time 3.14 seconds
Started Sep 11 09:58:39 AM UTC 24
Finished Sep 11 09:58:43 AM UTC 24
Peak memory 229432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661553983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 179.edn_genbits.661553983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_alert.1803953423
Short name T97
Test name
Test status
Simulation time 25854882 ps
CPU time 1.62 seconds
Started Sep 11 09:53:07 AM UTC 24
Finished Sep 11 09:53:09 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803953423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.1803953423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_alert_test.1424104639
Short name T376
Test name
Test status
Simulation time 15915091 ps
CPU time 1.23 seconds
Started Sep 11 09:53:10 AM UTC 24
Finished Sep 11 09:53:12 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424104639 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1424104639
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_disable.912165649
Short name T230
Test name
Test status
Simulation time 12936850 ps
CPU time 1.35 seconds
Started Sep 11 09:53:09 AM UTC 24
Finished Sep 11 09:53:11 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912165649 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.912165649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.2415831289
Short name T377
Test name
Test status
Simulation time 32008051 ps
CPU time 1.39 seconds
Started Sep 11 09:53:10 AM UTC 24
Finished Sep 11 09:53:12 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415831289 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.2415831289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_err.3782053810
Short name T375
Test name
Test status
Simulation time 41962022 ps
CPU time 1.07 seconds
Started Sep 11 09:53:07 AM UTC 24
Finished Sep 11 09:53:09 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782053810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.3782053810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_genbits.1100100680
Short name T48
Test name
Test status
Simulation time 44304808 ps
CPU time 1.88 seconds
Started Sep 11 09:53:04 AM UTC 24
Finished Sep 11 09:53:06 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100100680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1100100680
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_intr.283572122
Short name T105
Test name
Test status
Simulation time 37889561 ps
CPU time 1.34 seconds
Started Sep 11 09:53:06 AM UTC 24
Finished Sep 11 09:53:08 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283572122 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.283572122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_smoke.399631338
Short name T374
Test name
Test status
Simulation time 15738713 ps
CPU time 1.33 seconds
Started Sep 11 09:53:02 AM UTC 24
Finished Sep 11 09:53:05 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399631338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.edn_smoke.399631338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/18.edn_stress_all.2239653001
Short name T210
Test name
Test status
Simulation time 1911143179 ps
CPU time 3.57 seconds
Started Sep 11 09:53:05 AM UTC 24
Finished Sep 11 09:53:09 AM UTC 24
Peak memory 229548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239653001 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2239653001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/180.edn_alert.2152379370
Short name T837
Test name
Test status
Simulation time 57431699 ps
CPU time 1.36 seconds
Started Sep 11 09:58:40 AM UTC 24
Finished Sep 11 09:58:42 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152379370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.edn_alert.2152379370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/180.edn_genbits.590638553
Short name T832
Test name
Test status
Simulation time 165616977 ps
CPU time 1 seconds
Started Sep 11 09:58:39 AM UTC 24
Finished Sep 11 09:58:41 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590638553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 180.edn_genbits.590638553
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/181.edn_alert.39752552
Short name T840
Test name
Test status
Simulation time 39202222 ps
CPU time 1.63 seconds
Started Sep 11 09:58:40 AM UTC 24
Finished Sep 11 09:58:42 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39752552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 181.edn_alert.39752552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/182.edn_alert.2725266226
Short name T836
Test name
Test status
Simulation time 37227064 ps
CPU time 1.18 seconds
Started Sep 11 09:58:40 AM UTC 24
Finished Sep 11 09:58:42 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725266226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.2725266226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/182.edn_genbits.822358154
Short name T838
Test name
Test status
Simulation time 28186963 ps
CPU time 1.36 seconds
Started Sep 11 09:58:40 AM UTC 24
Finished Sep 11 09:58:42 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822358154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.edn_genbits.822358154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/183.edn_alert.3902667457
Short name T844
Test name
Test status
Simulation time 26858762 ps
CPU time 1.38 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:43 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902667457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.3902667457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/183.edn_genbits.206540837
Short name T846
Test name
Test status
Simulation time 76023332 ps
CPU time 2.75 seconds
Started Sep 11 09:58:40 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 231904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206540837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 183.edn_genbits.206540837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/184.edn_alert.1015558523
Short name T849
Test name
Test status
Simulation time 21765340 ps
CPU time 1.7 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015558523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.1015558523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/184.edn_genbits.1649949028
Short name T845
Test name
Test status
Simulation time 69770320 ps
CPU time 1.48 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649949028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1649949028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/185.edn_alert.1920423793
Short name T847
Test name
Test status
Simulation time 65078448 ps
CPU time 1.58 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920423793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 185.edn_alert.1920423793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/185.edn_genbits.3514135684
Short name T850
Test name
Test status
Simulation time 46722907 ps
CPU time 1.87 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514135684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3514135684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/186.edn_alert.422494130
Short name T848
Test name
Test status
Simulation time 49229482 ps
CPU time 1.51 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 226384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422494130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 186.edn_alert.422494130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/186.edn_genbits.119537847
Short name T859
Test name
Test status
Simulation time 262167998 ps
CPU time 3.6 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:46 AM UTC 24
Peak memory 231496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119537847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.edn_genbits.119537847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/187.edn_alert.1224243421
Short name T851
Test name
Test status
Simulation time 31058250 ps
CPU time 1.34 seconds
Started Sep 11 09:58:42 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224243421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.1224243421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/187.edn_genbits.2573413850
Short name T330
Test name
Test status
Simulation time 90686622 ps
CPU time 1.64 seconds
Started Sep 11 09:58:41 AM UTC 24
Finished Sep 11 09:58:44 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573413850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2573413850
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/188.edn_alert.2759274264
Short name T854
Test name
Test status
Simulation time 26461496 ps
CPU time 1.55 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759274264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.2759274264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/188.edn_genbits.2035093134
Short name T852
Test name
Test status
Simulation time 45279757 ps
CPU time 1.32 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035093134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2035093134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/189.edn_alert.3198799652
Short name T856
Test name
Test status
Simulation time 39793329 ps
CPU time 1.62 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198799652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.3198799652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/189.edn_genbits.872064056
Short name T857
Test name
Test status
Simulation time 39263859 ps
CPU time 1.68 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872064056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 189.edn_genbits.872064056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_alert_test.3141275244
Short name T383
Test name
Test status
Simulation time 17826266 ps
CPU time 1.39 seconds
Started Sep 11 09:53:22 AM UTC 24
Finished Sep 11 09:53:24 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141275244 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3141275244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_disable.1291797134
Short name T381
Test name
Test status
Simulation time 22159720 ps
CPU time 1.01 seconds
Started Sep 11 09:53:20 AM UTC 24
Finished Sep 11 09:53:22 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291797134 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1291797134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.1208538595
Short name T382
Test name
Test status
Simulation time 29717662 ps
CPU time 1.46 seconds
Started Sep 11 09:53:20 AM UTC 24
Finished Sep 11 09:53:22 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208538595 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.1208538595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_err.1138434669
Short name T380
Test name
Test status
Simulation time 59778899 ps
CPU time 1.46 seconds
Started Sep 11 09:53:17 AM UTC 24
Finished Sep 11 09:53:19 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138434669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.1138434669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_genbits.1161863650
Short name T93
Test name
Test status
Simulation time 43315264 ps
CPU time 1.84 seconds
Started Sep 11 09:53:12 AM UTC 24
Finished Sep 11 09:53:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161863650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1161863650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_intr.1532024053
Short name T379
Test name
Test status
Simulation time 37368017 ps
CPU time 1.31 seconds
Started Sep 11 09:53:13 AM UTC 24
Finished Sep 11 09:53:16 AM UTC 24
Peak memory 237620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532024053 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.1532024053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_smoke.1330380964
Short name T378
Test name
Test status
Simulation time 18427272 ps
CPU time 1.35 seconds
Started Sep 11 09:53:10 AM UTC 24
Finished Sep 11 09:53:12 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330380964 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_smoke.1330380964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.3810412163
Short name T236
Test name
Test status
Simulation time 6186220120 ps
CPU time 80.01 seconds
Started Sep 11 09:53:13 AM UTC 24
Finished Sep 11 09:54:35 AM UTC 24
Peak memory 233812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3810412163 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all
_with_rand_reset.3810412163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/190.edn_alert.4046519636
Short name T853
Test name
Test status
Simulation time 71091581 ps
CPU time 1.19 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046519636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.4046519636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/190.edn_genbits.766838394
Short name T858
Test name
Test status
Simulation time 31767352 ps
CPU time 1.85 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:46 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766838394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 190.edn_genbits.766838394
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/191.edn_alert.4018104075
Short name T860
Test name
Test status
Simulation time 67420899 ps
CPU time 1.15 seconds
Started Sep 11 09:58:44 AM UTC 24
Finished Sep 11 09:58:46 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018104075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.4018104075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/191.edn_genbits.118787823
Short name T855
Test name
Test status
Simulation time 192349318 ps
CPU time 1.42 seconds
Started Sep 11 09:58:43 AM UTC 24
Finished Sep 11 09:58:45 AM UTC 24
Peak memory 230660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118787823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.edn_genbits.118787823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/192.edn_alert.4123212739
Short name T861
Test name
Test status
Simulation time 92079145 ps
CPU time 1.32 seconds
Started Sep 11 09:58:44 AM UTC 24
Finished Sep 11 09:58:46 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123212739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.4123212739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/192.edn_genbits.1390779339
Short name T862
Test name
Test status
Simulation time 80973057 ps
CPU time 1.64 seconds
Started Sep 11 09:58:44 AM UTC 24
Finished Sep 11 09:58:47 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390779339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1390779339
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/193.edn_alert.276897041
Short name T865
Test name
Test status
Simulation time 47680483 ps
CPU time 1.49 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:48 AM UTC 24
Peak memory 226384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276897041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 193.edn_alert.276897041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/193.edn_genbits.2031737594
Short name T863
Test name
Test status
Simulation time 154705290 ps
CPU time 1.68 seconds
Started Sep 11 09:58:44 AM UTC 24
Finished Sep 11 09:58:47 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031737594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2031737594
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/194.edn_alert.4145414834
Short name T868
Test name
Test status
Simulation time 47849698 ps
CPU time 1.67 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:48 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145414834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.4145414834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/194.edn_genbits.2576335295
Short name T879
Test name
Test status
Simulation time 78849952 ps
CPU time 3.49 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:50 AM UTC 24
Peak memory 231756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576335295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2576335295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/195.edn_alert.3185677640
Short name T864
Test name
Test status
Simulation time 273157189 ps
CPU time 1.09 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:47 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185677640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 195.edn_alert.3185677640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/195.edn_genbits.315609342
Short name T870
Test name
Test status
Simulation time 32455754 ps
CPU time 1.93 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:48 AM UTC 24
Peak memory 230684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315609342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 195.edn_genbits.315609342
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/196.edn_alert.117070149
Short name T866
Test name
Test status
Simulation time 36357246 ps
CPU time 1.18 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:48 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117070149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 196.edn_alert.117070149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/196.edn_genbits.2642584995
Short name T867
Test name
Test status
Simulation time 63777750 ps
CPU time 1.43 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:48 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642584995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2642584995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/197.edn_alert.1184739953
Short name T875
Test name
Test status
Simulation time 52716423 ps
CPU time 1.69 seconds
Started Sep 11 09:58:46 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184739953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 197.edn_alert.1184739953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/197.edn_genbits.1292934107
Short name T871
Test name
Test status
Simulation time 61673020 ps
CPU time 2.2 seconds
Started Sep 11 09:58:45 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 229508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292934107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1292934107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/198.edn_alert.3934955495
Short name T872
Test name
Test status
Simulation time 63345637 ps
CPU time 1.43 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934955495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.3934955495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/198.edn_genbits.3131785030
Short name T874
Test name
Test status
Simulation time 21973477 ps
CPU time 1.66 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131785030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3131785030
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/199.edn_alert.2556743663
Short name T873
Test name
Test status
Simulation time 66964523 ps
CPU time 1.39 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 228380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556743663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.2556743663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/199.edn_genbits.1683030652
Short name T876
Test name
Test status
Simulation time 46476400 ps
CPU time 1.56 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 228312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683030652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1683030652
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_alert.610725454
Short name T32
Test name
Test status
Simulation time 105688432 ps
CPU time 1.94 seconds
Started Sep 11 09:51:04 AM UTC 24
Finished Sep 11 09:51:07 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610725454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.edn_alert.610725454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_alert_test.2819508185
Short name T69
Test name
Test status
Simulation time 20089413 ps
CPU time 1.12 seconds
Started Sep 11 09:51:08 AM UTC 24
Finished Sep 11 09:51:10 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819508185 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2819508185
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_disable.709740256
Short name T68
Test name
Test status
Simulation time 25505681 ps
CPU time 1.21 seconds
Started Sep 11 09:51:05 AM UTC 24
Finished Sep 11 09:51:07 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709740256 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.709740256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_err.212256229
Short name T8
Test name
Test status
Simulation time 21308145 ps
CPU time 1.67 seconds
Started Sep 11 09:51:04 AM UTC 24
Finished Sep 11 09:51:07 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212256229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 2.edn_err.212256229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_genbits.2517009069
Short name T41
Test name
Test status
Simulation time 39338982 ps
CPU time 2.48 seconds
Started Sep 11 09:51:02 AM UTC 24
Finished Sep 11 09:51:06 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517009069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2517009069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_intr.4289619174
Short name T33
Test name
Test status
Simulation time 20015138 ps
CPU time 1.67 seconds
Started Sep 11 09:51:02 AM UTC 24
Finished Sep 11 09:51:05 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289619174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.4289619174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_regwen.1525048919
Short name T66
Test name
Test status
Simulation time 45426108 ps
CPU time 1.34 seconds
Started Sep 11 09:51:01 AM UTC 24
Finished Sep 11 09:51:03 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525048919 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.1525048919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_smoke.2189310956
Short name T65
Test name
Test status
Simulation time 15344468 ps
CPU time 1.26 seconds
Started Sep 11 09:51:01 AM UTC 24
Finished Sep 11 09:51:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189310956 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.2189310956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/2.edn_stress_all.3217747025
Short name T61
Test name
Test status
Simulation time 381371692 ps
CPU time 7.07 seconds
Started Sep 11 09:51:02 AM UTC 24
Finished Sep 11 09:51:10 AM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217747025 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3217747025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_alert.3785742726
Short name T75
Test name
Test status
Simulation time 215067446 ps
CPU time 1.61 seconds
Started Sep 11 09:53:28 AM UTC 24
Finished Sep 11 09:53:31 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785742726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_alert.3785742726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_alert_test.848844191
Short name T388
Test name
Test status
Simulation time 29608751 ps
CPU time 1.18 seconds
Started Sep 11 09:53:34 AM UTC 24
Finished Sep 11 09:53:36 AM UTC 24
Peak memory 216820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848844191 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.848844191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_disable.59425902
Short name T228
Test name
Test status
Simulation time 17860438 ps
CPU time 1.22 seconds
Started Sep 11 09:53:31 AM UTC 24
Finished Sep 11 09:53:34 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59425902 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.59425902
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.2933665955
Short name T387
Test name
Test status
Simulation time 54781545 ps
CPU time 1.41 seconds
Started Sep 11 09:53:31 AM UTC 24
Finished Sep 11 09:53:34 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933665955 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.2933665955
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_err.3514011161
Short name T196
Test name
Test status
Simulation time 23972273 ps
CPU time 1.33 seconds
Started Sep 11 09:53:30 AM UTC 24
Finished Sep 11 09:53:33 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514011161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.3514011161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_genbits.1534981344
Short name T385
Test name
Test status
Simulation time 62796848 ps
CPU time 2.57 seconds
Started Sep 11 09:53:23 AM UTC 24
Finished Sep 11 09:53:26 AM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534981344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1534981344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_intr.607245152
Short name T136
Test name
Test status
Simulation time 28132715 ps
CPU time 1.3 seconds
Started Sep 11 09:53:27 AM UTC 24
Finished Sep 11 09:53:29 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607245152 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.607245152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_smoke.3622620780
Short name T384
Test name
Test status
Simulation time 48862737 ps
CPU time 1.31 seconds
Started Sep 11 09:53:23 AM UTC 24
Finished Sep 11 09:53:25 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622620780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_smoke.3622620780
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/20.edn_stress_all.2473750881
Short name T386
Test name
Test status
Simulation time 512154460 ps
CPU time 4.32 seconds
Started Sep 11 09:53:25 AM UTC 24
Finished Sep 11 09:53:30 AM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473750881 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2473750881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/200.edn_genbits.3815228847
Short name T881
Test name
Test status
Simulation time 59095811 ps
CPU time 2.69 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:50 AM UTC 24
Peak memory 231508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815228847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3815228847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/201.edn_genbits.1977898973
Short name T878
Test name
Test status
Simulation time 41615837 ps
CPU time 1.58 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977898973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1977898973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/202.edn_genbits.3832683001
Short name T877
Test name
Test status
Simulation time 43177880 ps
CPU time 1.48 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:49 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832683001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3832683001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/203.edn_genbits.2152789819
Short name T335
Test name
Test status
Simulation time 78704916 ps
CPU time 3.52 seconds
Started Sep 11 09:58:47 AM UTC 24
Finished Sep 11 09:58:51 AM UTC 24
Peak memory 231496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152789819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2152789819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/204.edn_genbits.396809093
Short name T971
Test name
Test status
Simulation time 16939954128 ps
CPU time 134.25 seconds
Started Sep 11 09:58:48 AM UTC 24
Finished Sep 11 10:01:04 AM UTC 24
Peak memory 231872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396809093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 204.edn_genbits.396809093
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/205.edn_genbits.1407867481
Short name T336
Test name
Test status
Simulation time 344304221 ps
CPU time 2.39 seconds
Started Sep 11 09:58:48 AM UTC 24
Finished Sep 11 09:58:51 AM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407867481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1407867481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/206.edn_genbits.1206233069
Short name T880
Test name
Test status
Simulation time 43315961 ps
CPU time 1.11 seconds
Started Sep 11 09:58:48 AM UTC 24
Finished Sep 11 09:58:50 AM UTC 24
Peak memory 230216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206233069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1206233069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/207.edn_genbits.3501826668
Short name T882
Test name
Test status
Simulation time 139968480 ps
CPU time 1.96 seconds
Started Sep 11 09:58:48 AM UTC 24
Finished Sep 11 09:58:51 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501826668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3501826668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/208.edn_genbits.4034953170
Short name T885
Test name
Test status
Simulation time 61732106 ps
CPU time 1.74 seconds
Started Sep 11 09:58:49 AM UTC 24
Finished Sep 11 09:58:52 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034953170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4034953170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/209.edn_genbits.570586930
Short name T899
Test name
Test status
Simulation time 345346442 ps
CPU time 4.99 seconds
Started Sep 11 09:58:49 AM UTC 24
Finished Sep 11 09:58:55 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570586930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 209.edn_genbits.570586930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_alert.4014679833
Short name T311
Test name
Test status
Simulation time 91456541 ps
CPU time 1.55 seconds
Started Sep 11 09:53:38 AM UTC 24
Finished Sep 11 09:53:41 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014679833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.4014679833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_alert_test.520245347
Short name T395
Test name
Test status
Simulation time 15272719 ps
CPU time 1.41 seconds
Started Sep 11 09:53:42 AM UTC 24
Finished Sep 11 09:53:45 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520245347 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.520245347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.2199148273
Short name T393
Test name
Test status
Simulation time 46999547 ps
CPU time 1.47 seconds
Started Sep 11 09:53:41 AM UTC 24
Finished Sep 11 09:53:44 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199148273 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.2199148273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_err.1384441016
Short name T155
Test name
Test status
Simulation time 64624498 ps
CPU time 1.52 seconds
Started Sep 11 09:53:39 AM UTC 24
Finished Sep 11 09:53:42 AM UTC 24
Peak memory 244092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384441016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.1384441016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_genbits.1060400272
Short name T12
Test name
Test status
Simulation time 295185052 ps
CPU time 2.39 seconds
Started Sep 11 09:53:35 AM UTC 24
Finished Sep 11 09:53:38 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060400272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1060400272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_intr.1561771557
Short name T390
Test name
Test status
Simulation time 41089735 ps
CPU time 1.42 seconds
Started Sep 11 09:53:37 AM UTC 24
Finished Sep 11 09:53:39 AM UTC 24
Peak memory 226552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561771557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.1561771557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_smoke.1696224927
Short name T389
Test name
Test status
Simulation time 23693199 ps
CPU time 1.42 seconds
Started Sep 11 09:53:35 AM UTC 24
Finished Sep 11 09:53:37 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696224927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.1696224927
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_stress_all.526479337
Short name T391
Test name
Test status
Simulation time 820916512 ps
CPU time 4.6 seconds
Started Sep 11 09:53:36 AM UTC 24
Finished Sep 11 09:53:42 AM UTC 24
Peak memory 227652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526479337 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.526479337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.1054490936
Short name T243
Test name
Test status
Simulation time 31092870727 ps
CPU time 73.37 seconds
Started Sep 11 09:53:36 AM UTC 24
Finished Sep 11 09:54:51 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1054490936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.1054490936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/210.edn_genbits.4220169841
Short name T886
Test name
Test status
Simulation time 72787607 ps
CPU time 1.77 seconds
Started Sep 11 09:58:49 AM UTC 24
Finished Sep 11 09:58:52 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220169841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4220169841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/211.edn_genbits.3097216213
Short name T884
Test name
Test status
Simulation time 87209034 ps
CPU time 1.62 seconds
Started Sep 11 09:58:49 AM UTC 24
Finished Sep 11 09:58:52 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097216213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3097216213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/212.edn_genbits.2682746446
Short name T887
Test name
Test status
Simulation time 47040702 ps
CPU time 1.73 seconds
Started Sep 11 09:58:49 AM UTC 24
Finished Sep 11 09:58:52 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682746446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2682746446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/213.edn_genbits.2531914354
Short name T883
Test name
Test status
Simulation time 58625036 ps
CPU time 1.21 seconds
Started Sep 11 09:58:49 AM UTC 24
Finished Sep 11 09:58:52 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531914354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2531914354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/214.edn_genbits.21227006
Short name T890
Test name
Test status
Simulation time 83497312 ps
CPU time 1.7 seconds
Started Sep 11 09:58:50 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21227006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 214.edn_genbits.21227006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/215.edn_genbits.3640569829
Short name T892
Test name
Test status
Simulation time 176665123 ps
CPU time 1.77 seconds
Started Sep 11 09:58:50 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640569829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3640569829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/216.edn_genbits.3898724019
Short name T332
Test name
Test status
Simulation time 38444142 ps
CPU time 1.75 seconds
Started Sep 11 09:58:50 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 230252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898724019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3898724019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/217.edn_genbits.563235322
Short name T888
Test name
Test status
Simulation time 87591742 ps
CPU time 1.42 seconds
Started Sep 11 09:58:50 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563235322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 217.edn_genbits.563235322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/218.edn_genbits.599476060
Short name T889
Test name
Test status
Simulation time 185538173 ps
CPU time 1.52 seconds
Started Sep 11 09:58:51 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599476060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 218.edn_genbits.599476060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/219.edn_genbits.3898988071
Short name T893
Test name
Test status
Simulation time 50919172 ps
CPU time 1.67 seconds
Started Sep 11 09:58:51 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898988071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3898988071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_alert_test.201744961
Short name T396
Test name
Test status
Simulation time 56567451 ps
CPU time 1.31 seconds
Started Sep 11 09:53:50 AM UTC 24
Finished Sep 11 09:53:53 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201744961 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.201744961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_disable.2540911688
Short name T186
Test name
Test status
Simulation time 16311156 ps
CPU time 1.23 seconds
Started Sep 11 09:53:47 AM UTC 24
Finished Sep 11 09:53:49 AM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540911688 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2540911688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.1266696367
Short name T398
Test name
Test status
Simulation time 335109362 ps
CPU time 1.7 seconds
Started Sep 11 09:53:50 AM UTC 24
Finished Sep 11 09:53:53 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266696367 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.1266696367
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_err.4038019070
Short name T159
Test name
Test status
Simulation time 36406342 ps
CPU time 1.4 seconds
Started Sep 11 09:53:47 AM UTC 24
Finished Sep 11 09:53:49 AM UTC 24
Peak memory 228328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038019070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.edn_err.4038019070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_genbits.2685695136
Short name T76
Test name
Test status
Simulation time 91333641 ps
CPU time 1.97 seconds
Started Sep 11 09:53:42 AM UTC 24
Finished Sep 11 09:53:45 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685695136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2685695136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_intr.1729297288
Short name T35
Test name
Test status
Simulation time 20561770 ps
CPU time 1.45 seconds
Started Sep 11 09:53:46 AM UTC 24
Finished Sep 11 09:53:49 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729297288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.1729297288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_smoke.950904461
Short name T394
Test name
Test status
Simulation time 114187568 ps
CPU time 1.14 seconds
Started Sep 11 09:53:42 AM UTC 24
Finished Sep 11 09:53:45 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950904461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.edn_smoke.950904461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_stress_all.377566061
Short name T252
Test name
Test status
Simulation time 403139966 ps
CPU time 5.96 seconds
Started Sep 11 09:53:43 AM UTC 24
Finished Sep 11 09:53:51 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377566061 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.377566061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.866643211
Short name T244
Test name
Test status
Simulation time 9822947640 ps
CPU time 67.81 seconds
Started Sep 11 09:53:45 AM UTC 24
Finished Sep 11 09:54:55 AM UTC 24
Peak memory 229716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=866643211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_
with_rand_reset.866643211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/220.edn_genbits.4073811407
Short name T891
Test name
Test status
Simulation time 40100342 ps
CPU time 1.5 seconds
Started Sep 11 09:58:51 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 230652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073811407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4073811407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/221.edn_genbits.344738650
Short name T894
Test name
Test status
Simulation time 51910827 ps
CPU time 1.74 seconds
Started Sep 11 09:58:51 AM UTC 24
Finished Sep 11 09:58:53 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344738650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 221.edn_genbits.344738650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/222.edn_genbits.509994512
Short name T897
Test name
Test status
Simulation time 68224781 ps
CPU time 2.66 seconds
Started Sep 11 09:58:51 AM UTC 24
Finished Sep 11 09:58:54 AM UTC 24
Peak memory 231496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509994512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 222.edn_genbits.509994512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/223.edn_genbits.4062557415
Short name T911
Test name
Test status
Simulation time 272504044 ps
CPU time 4.68 seconds
Started Sep 11 09:58:52 AM UTC 24
Finished Sep 11 09:58:58 AM UTC 24
Peak memory 229580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062557415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4062557415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/224.edn_genbits.3097429579
Short name T896
Test name
Test status
Simulation time 75651431 ps
CPU time 1.41 seconds
Started Sep 11 09:58:52 AM UTC 24
Finished Sep 11 09:58:54 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097429579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3097429579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/225.edn_genbits.3584822804
Short name T895
Test name
Test status
Simulation time 74070104 ps
CPU time 1.22 seconds
Started Sep 11 09:58:52 AM UTC 24
Finished Sep 11 09:58:54 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584822804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3584822804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/226.edn_genbits.1504117160
Short name T898
Test name
Test status
Simulation time 41045728 ps
CPU time 1.44 seconds
Started Sep 11 09:58:52 AM UTC 24
Finished Sep 11 09:58:54 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504117160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1504117160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/227.edn_genbits.573090272
Short name T904
Test name
Test status
Simulation time 278361920 ps
CPU time 1.87 seconds
Started Sep 11 09:58:53 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573090272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 227.edn_genbits.573090272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/228.edn_genbits.629616663
Short name T901
Test name
Test status
Simulation time 41544757 ps
CPU time 1.49 seconds
Started Sep 11 09:58:53 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 230604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629616663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 228.edn_genbits.629616663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/229.edn_genbits.1470288797
Short name T905
Test name
Test status
Simulation time 90822719 ps
CPU time 1.77 seconds
Started Sep 11 09:58:53 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470288797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1470288797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_alert.1725405032
Short name T180
Test name
Test status
Simulation time 152257452 ps
CPU time 1.55 seconds
Started Sep 11 09:53:53 AM UTC 24
Finished Sep 11 09:53:56 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725405032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.1725405032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_alert_test.1727731744
Short name T402
Test name
Test status
Simulation time 62090899 ps
CPU time 1.36 seconds
Started Sep 11 09:53:54 AM UTC 24
Finished Sep 11 09:53:57 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727731744 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1727731744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_disable.3346854804
Short name T399
Test name
Test status
Simulation time 43046764 ps
CPU time 1.29 seconds
Started Sep 11 09:53:53 AM UTC 24
Finished Sep 11 09:53:56 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346854804 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3346854804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.4206200383
Short name T403
Test name
Test status
Simulation time 97775609 ps
CPU time 1.81 seconds
Started Sep 11 09:53:54 AM UTC 24
Finished Sep 11 09:53:57 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206200383 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.4206200383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_err.911988319
Short name T401
Test name
Test status
Simulation time 44220983 ps
CPU time 1.37 seconds
Started Sep 11 09:53:53 AM UTC 24
Finished Sep 11 09:53:56 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911988319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.edn_err.911988319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_genbits.4020855310
Short name T344
Test name
Test status
Simulation time 48902531 ps
CPU time 1.6 seconds
Started Sep 11 09:53:50 AM UTC 24
Finished Sep 11 09:53:53 AM UTC 24
Peak memory 230604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020855310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4020855310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_intr.2815379885
Short name T400
Test name
Test status
Simulation time 24088144 ps
CPU time 1.48 seconds
Started Sep 11 09:53:53 AM UTC 24
Finished Sep 11 09:53:56 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815379885 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.2815379885
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_smoke.3405919270
Short name T397
Test name
Test status
Simulation time 18551871 ps
CPU time 1.32 seconds
Started Sep 11 09:53:50 AM UTC 24
Finished Sep 11 09:53:53 AM UTC 24
Peak memory 226264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405919270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.3405919270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_stress_all.4251751214
Short name T315
Test name
Test status
Simulation time 363524140 ps
CPU time 5.22 seconds
Started Sep 11 09:53:50 AM UTC 24
Finished Sep 11 09:53:57 AM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251751214 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4251751214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.1618504066
Short name T320
Test name
Test status
Simulation time 12483246059 ps
CPU time 69.22 seconds
Started Sep 11 09:53:51 AM UTC 24
Finished Sep 11 09:55:03 AM UTC 24
Peak memory 234352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1618504066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all
_with_rand_reset.1618504066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/230.edn_genbits.2137680062
Short name T906
Test name
Test status
Simulation time 43647158 ps
CPU time 1.82 seconds
Started Sep 11 09:58:53 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137680062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2137680062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/231.edn_genbits.78216555
Short name T902
Test name
Test status
Simulation time 97061372 ps
CPU time 1.46 seconds
Started Sep 11 09:58:53 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78216555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 231.edn_genbits.78216555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/232.edn_genbits.3525699775
Short name T903
Test name
Test status
Simulation time 81147562 ps
CPU time 1.47 seconds
Started Sep 11 09:58:53 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525699775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3525699775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/233.edn_genbits.1744613015
Short name T900
Test name
Test status
Simulation time 58365797 ps
CPU time 1.24 seconds
Started Sep 11 09:58:54 AM UTC 24
Finished Sep 11 09:58:56 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744613015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1744613015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/234.edn_genbits.1763694205
Short name T841
Test name
Test status
Simulation time 35057122 ps
CPU time 1.7 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:57 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763694205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1763694205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/235.edn_genbits.2411842656
Short name T909
Test name
Test status
Simulation time 96761682 ps
CPU time 1.67 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:57 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411842656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2411842656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/236.edn_genbits.4252628324
Short name T869
Test name
Test status
Simulation time 47237715 ps
CPU time 1.74 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:57 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252628324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4252628324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/237.edn_genbits.4283706695
Short name T912
Test name
Test status
Simulation time 56977311 ps
CPU time 1.87 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:58 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283706695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4283706695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/238.edn_genbits.3981148071
Short name T910
Test name
Test status
Simulation time 43389164 ps
CPU time 1.66 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:58 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981148071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3981148071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/239.edn_genbits.3015732808
Short name T907
Test name
Test status
Simulation time 302359027 ps
CPU time 0.97 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:57 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015732808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3015732808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_alert_test.2392971250
Short name T409
Test name
Test status
Simulation time 14074965 ps
CPU time 1.32 seconds
Started Sep 11 09:54:01 AM UTC 24
Finished Sep 11 09:54:03 AM UTC 24
Peak memory 215860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392971250 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2392971250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_disable.1939219055
Short name T407
Test name
Test status
Simulation time 11617669 ps
CPU time 1.26 seconds
Started Sep 11 09:54:00 AM UTC 24
Finished Sep 11 09:54:02 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939219055 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1939219055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2902118005
Short name T212
Test name
Test status
Simulation time 36872991 ps
CPU time 1.59 seconds
Started Sep 11 09:54:00 AM UTC 24
Finished Sep 11 09:54:02 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902118005 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.2902118005
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_err.2656780137
Short name T190
Test name
Test status
Simulation time 18352058 ps
CPU time 1.59 seconds
Started Sep 11 09:53:58 AM UTC 24
Finished Sep 11 09:54:00 AM UTC 24
Peak memory 228596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656780137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.2656780137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_genbits.4164074208
Short name T49
Test name
Test status
Simulation time 41251008 ps
CPU time 1.68 seconds
Started Sep 11 09:53:56 AM UTC 24
Finished Sep 11 09:53:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164074208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4164074208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_intr.1743052420
Short name T405
Test name
Test status
Simulation time 22311213 ps
CPU time 1.59 seconds
Started Sep 11 09:53:58 AM UTC 24
Finished Sep 11 09:54:00 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743052420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.1743052420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_smoke.1569410040
Short name T404
Test name
Test status
Simulation time 34370046 ps
CPU time 1.37 seconds
Started Sep 11 09:53:56 AM UTC 24
Finished Sep 11 09:53:59 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569410040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_smoke.1569410040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/24.edn_stress_all.3445123022
Short name T406
Test name
Test status
Simulation time 213356832 ps
CPU time 2.99 seconds
Started Sep 11 09:53:57 AM UTC 24
Finished Sep 11 09:54:01 AM UTC 24
Peak memory 229444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445123022 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3445123022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/240.edn_genbits.2178240672
Short name T842
Test name
Test status
Simulation time 71691817 ps
CPU time 1.46 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:57 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178240672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2178240672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/241.edn_genbits.42585834
Short name T908
Test name
Test status
Simulation time 57745589 ps
CPU time 1.14 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:57 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42585834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 241.edn_genbits.42585834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/242.edn_genbits.1809964361
Short name T913
Test name
Test status
Simulation time 35403274 ps
CPU time 1.78 seconds
Started Sep 11 09:58:55 AM UTC 24
Finished Sep 11 09:58:58 AM UTC 24
Peak memory 230600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809964361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1809964361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/243.edn_genbits.441264273
Short name T914
Test name
Test status
Simulation time 116404371 ps
CPU time 1.49 seconds
Started Sep 11 09:58:56 AM UTC 24
Finished Sep 11 09:58:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441264273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.edn_genbits.441264273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/244.edn_genbits.1794452264
Short name T915
Test name
Test status
Simulation time 162683889 ps
CPU time 1.51 seconds
Started Sep 11 09:58:56 AM UTC 24
Finished Sep 11 09:58:59 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794452264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1794452264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/245.edn_genbits.812767615
Short name T916
Test name
Test status
Simulation time 40906116 ps
CPU time 1.58 seconds
Started Sep 11 09:58:56 AM UTC 24
Finished Sep 11 09:58:59 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812767615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.edn_genbits.812767615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/246.edn_genbits.3388814938
Short name T917
Test name
Test status
Simulation time 55759925 ps
CPU time 1.71 seconds
Started Sep 11 09:58:56 AM UTC 24
Finished Sep 11 09:58:59 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388814938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3388814938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/247.edn_genbits.2438341483
Short name T918
Test name
Test status
Simulation time 46680757 ps
CPU time 1.82 seconds
Started Sep 11 09:58:56 AM UTC 24
Finished Sep 11 09:58:59 AM UTC 24
Peak memory 226504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438341483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2438341483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/248.edn_genbits.3899269792
Short name T921
Test name
Test status
Simulation time 185071982 ps
CPU time 1.49 seconds
Started Sep 11 09:58:57 AM UTC 24
Finished Sep 11 09:59:00 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899269792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3899269792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/249.edn_genbits.1259347249
Short name T919
Test name
Test status
Simulation time 94606090 ps
CPU time 1.39 seconds
Started Sep 11 09:58:57 AM UTC 24
Finished Sep 11 09:59:00 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259347249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1259347249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_alert.691899838
Short name T143
Test name
Test status
Simulation time 92075239 ps
CPU time 1.54 seconds
Started Sep 11 09:54:05 AM UTC 24
Finished Sep 11 09:54:07 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691899838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 25.edn_alert.691899838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_alert_test.703924006
Short name T415
Test name
Test status
Simulation time 22777009 ps
CPU time 1.2 seconds
Started Sep 11 09:54:08 AM UTC 24
Finished Sep 11 09:54:10 AM UTC 24
Peak memory 215860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703924006 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.703924006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_disable.615153815
Short name T412
Test name
Test status
Simulation time 28328105 ps
CPU time 1.23 seconds
Started Sep 11 09:54:06 AM UTC 24
Finished Sep 11 09:54:08 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615153815 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.615153815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_err.1069292206
Short name T414
Test name
Test status
Simulation time 35688583 ps
CPU time 1.98 seconds
Started Sep 11 09:54:06 AM UTC 24
Finished Sep 11 09:54:09 AM UTC 24
Peak memory 242076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069292206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.1069292206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_genbits.3605128052
Short name T13
Test name
Test status
Simulation time 51832039 ps
CPU time 1.78 seconds
Started Sep 11 09:54:01 AM UTC 24
Finished Sep 11 09:54:04 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605128052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3605128052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_intr.1786365380
Short name T411
Test name
Test status
Simulation time 25278116 ps
CPU time 1.85 seconds
Started Sep 11 09:54:05 AM UTC 24
Finished Sep 11 09:54:08 AM UTC 24
Peak memory 242068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786365380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.1786365380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_smoke.1203769211
Short name T408
Test name
Test status
Simulation time 42984654 ps
CPU time 1.27 seconds
Started Sep 11 09:54:01 AM UTC 24
Finished Sep 11 09:54:03 AM UTC 24
Peak memory 226264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203769211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.1203769211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_stress_all.1959839065
Short name T410
Test name
Test status
Simulation time 490904852 ps
CPU time 4.69 seconds
Started Sep 11 09:54:01 AM UTC 24
Finished Sep 11 09:54:07 AM UTC 24
Peak memory 229704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959839065 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1959839065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.2218183186
Short name T245
Test name
Test status
Simulation time 5282052512 ps
CPU time 59.77 seconds
Started Sep 11 09:54:01 AM UTC 24
Finished Sep 11 09:55:03 AM UTC 24
Peak memory 234020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2218183186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.2218183186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/250.edn_genbits.4061785141
Short name T924
Test name
Test status
Simulation time 46503347 ps
CPU time 1.76 seconds
Started Sep 11 09:58:57 AM UTC 24
Finished Sep 11 09:59:00 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061785141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.4061785141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/251.edn_genbits.1475464470
Short name T920
Test name
Test status
Simulation time 73153837 ps
CPU time 1.22 seconds
Started Sep 11 09:58:57 AM UTC 24
Finished Sep 11 09:59:00 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475464470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1475464470
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/252.edn_genbits.1906144834
Short name T922
Test name
Test status
Simulation time 81227324 ps
CPU time 1.41 seconds
Started Sep 11 09:58:58 AM UTC 24
Finished Sep 11 09:59:00 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906144834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1906144834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/253.edn_genbits.1327497932
Short name T923
Test name
Test status
Simulation time 156065533 ps
CPU time 1.36 seconds
Started Sep 11 09:58:58 AM UTC 24
Finished Sep 11 09:59:00 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327497932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1327497932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/254.edn_genbits.3939061659
Short name T928
Test name
Test status
Simulation time 49531670 ps
CPU time 2.01 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939061659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3939061659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/255.edn_genbits.3922274156
Short name T925
Test name
Test status
Simulation time 47949652 ps
CPU time 1.25 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:01 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922274156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3922274156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/256.edn_genbits.4144456463
Short name T931
Test name
Test status
Simulation time 43892291 ps
CPU time 1.96 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144456463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4144456463
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/257.edn_genbits.889881987
Short name T930
Test name
Test status
Simulation time 35806899 ps
CPU time 1.99 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 230604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889881987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 257.edn_genbits.889881987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/258.edn_genbits.759092444
Short name T933
Test name
Test status
Simulation time 54668903 ps
CPU time 2.45 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 229512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759092444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 258.edn_genbits.759092444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/259.edn_genbits.707862605
Short name T927
Test name
Test status
Simulation time 31386452 ps
CPU time 1.52 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707862605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 259.edn_genbits.707862605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_alert.1378039354
Short name T174
Test name
Test status
Simulation time 26453000 ps
CPU time 1.76 seconds
Started Sep 11 09:54:12 AM UTC 24
Finished Sep 11 09:54:15 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378039354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_alert.1378039354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_alert_test.518328815
Short name T421
Test name
Test status
Simulation time 16513033 ps
CPU time 1.26 seconds
Started Sep 11 09:54:17 AM UTC 24
Finished Sep 11 09:54:19 AM UTC 24
Peak memory 217040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518328815 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.518328815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_disable.2346302286
Short name T418
Test name
Test status
Simulation time 14346453 ps
CPU time 1.29 seconds
Started Sep 11 09:54:13 AM UTC 24
Finished Sep 11 09:54:15 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346302286 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2346302286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.3288269478
Short name T419
Test name
Test status
Simulation time 225151401 ps
CPU time 1.51 seconds
Started Sep 11 09:54:15 AM UTC 24
Finished Sep 11 09:54:17 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288269478 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.3288269478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_err.1743404481
Short name T417
Test name
Test status
Simulation time 36101195 ps
CPU time 1.32 seconds
Started Sep 11 09:54:13 AM UTC 24
Finished Sep 11 09:54:15 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743404481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.1743404481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_intr.713633325
Short name T101
Test name
Test status
Simulation time 22325460 ps
CPU time 1.46 seconds
Started Sep 11 09:54:10 AM UTC 24
Finished Sep 11 09:54:13 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713633325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.713633325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_smoke.2848104871
Short name T416
Test name
Test status
Simulation time 19409216 ps
CPU time 1.55 seconds
Started Sep 11 09:54:08 AM UTC 24
Finished Sep 11 09:54:11 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848104871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.2848104871
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_stress_all.3430031214
Short name T420
Test name
Test status
Simulation time 2941616563 ps
CPU time 6.13 seconds
Started Sep 11 09:54:10 AM UTC 24
Finished Sep 11 09:54:18 AM UTC 24
Peak memory 229644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430031214 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3430031214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.2103235300
Short name T540
Test name
Test status
Simulation time 4274897737 ps
CPU time 111.78 seconds
Started Sep 11 09:54:10 AM UTC 24
Finished Sep 11 09:56:04 AM UTC 24
Peak memory 229852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2103235300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all
_with_rand_reset.2103235300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/260.edn_genbits.944458441
Short name T926
Test name
Test status
Simulation time 57559933 ps
CPU time 1.28 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:01 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944458441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.edn_genbits.944458441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/261.edn_genbits.2023285782
Short name T929
Test name
Test status
Simulation time 60103820 ps
CPU time 1.67 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023285782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2023285782
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/262.edn_genbits.3977712712
Short name T932
Test name
Test status
Simulation time 44338338 ps
CPU time 1.72 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977712712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3977712712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/263.edn_genbits.3221088359
Short name T934
Test name
Test status
Simulation time 62045390 ps
CPU time 2.27 seconds
Started Sep 11 09:58:59 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221088359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3221088359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/264.edn_genbits.1527151243
Short name T938
Test name
Test status
Simulation time 26717368 ps
CPU time 1.69 seconds
Started Sep 11 09:59:00 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527151243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1527151243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/265.edn_genbits.808959373
Short name T936
Test name
Test status
Simulation time 47141157 ps
CPU time 1.61 seconds
Started Sep 11 09:59:00 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808959373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 265.edn_genbits.808959373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/266.edn_genbits.581857426
Short name T942
Test name
Test status
Simulation time 66581864 ps
CPU time 2.01 seconds
Started Sep 11 09:59:00 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 231748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581857426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 266.edn_genbits.581857426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/267.edn_genbits.3430796646
Short name T935
Test name
Test status
Simulation time 97326417 ps
CPU time 1.02 seconds
Started Sep 11 09:59:00 AM UTC 24
Finished Sep 11 09:59:02 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430796646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3430796646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/268.edn_genbits.87210980
Short name T939
Test name
Test status
Simulation time 42217796 ps
CPU time 1.72 seconds
Started Sep 11 09:59:00 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87210980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 268.edn_genbits.87210980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/269.edn_genbits.3804186617
Short name T940
Test name
Test status
Simulation time 72354895 ps
CPU time 1.74 seconds
Started Sep 11 09:59:01 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804186617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3804186617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_alert.2748695296
Short name T428
Test name
Test status
Simulation time 22262367 ps
CPU time 1.65 seconds
Started Sep 11 09:54:21 AM UTC 24
Finished Sep 11 09:54:24 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748695296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.2748695296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_alert_test.4082008792
Short name T426
Test name
Test status
Simulation time 13256699 ps
CPU time 1.09 seconds
Started Sep 11 09:54:22 AM UTC 24
Finished Sep 11 09:54:24 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082008792 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4082008792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_disable.2638615287
Short name T425
Test name
Test status
Simulation time 22361149 ps
CPU time 1.18 seconds
Started Sep 11 09:54:21 AM UTC 24
Finished Sep 11 09:54:24 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638615287 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2638615287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.974933247
Short name T427
Test name
Test status
Simulation time 46339091 ps
CPU time 1.46 seconds
Started Sep 11 09:54:22 AM UTC 24
Finished Sep 11 09:54:24 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974933247 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.974933247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_err.341693391
Short name T219
Test name
Test status
Simulation time 30871199 ps
CPU time 1.26 seconds
Started Sep 11 09:54:21 AM UTC 24
Finished Sep 11 09:54:24 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341693391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.edn_err.341693391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_intr.344429526
Short name T424
Test name
Test status
Simulation time 21559088 ps
CPU time 1.41 seconds
Started Sep 11 09:54:19 AM UTC 24
Finished Sep 11 09:54:21 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344429526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.344429526
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_smoke.445729042
Short name T422
Test name
Test status
Simulation time 16709455 ps
CPU time 1.47 seconds
Started Sep 11 09:54:17 AM UTC 24
Finished Sep 11 09:54:19 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445729042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.edn_smoke.445729042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_stress_all.3317724125
Short name T423
Test name
Test status
Simulation time 208129486 ps
CPU time 2.13 seconds
Started Sep 11 09:54:17 AM UTC 24
Finished Sep 11 09:54:20 AM UTC 24
Peak memory 227724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317724125 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3317724125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.3441456715
Short name T511
Test name
Test status
Simulation time 6789833557 ps
CPU time 76.7 seconds
Started Sep 11 09:54:19 AM UTC 24
Finished Sep 11 09:55:38 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3441456715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all
_with_rand_reset.3441456715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/270.edn_genbits.3064803744
Short name T937
Test name
Test status
Simulation time 36086135 ps
CPU time 1.27 seconds
Started Sep 11 09:59:01 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064803744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3064803744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/271.edn_genbits.1395000502
Short name T943
Test name
Test status
Simulation time 32386254 ps
CPU time 1.71 seconds
Started Sep 11 09:59:01 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395000502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1395000502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/272.edn_genbits.566372728
Short name T941
Test name
Test status
Simulation time 19702868 ps
CPU time 1.6 seconds
Started Sep 11 09:59:01 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566372728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 272.edn_genbits.566372728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/273.edn_genbits.3243982120
Short name T944
Test name
Test status
Simulation time 228410099 ps
CPU time 1.71 seconds
Started Sep 11 09:59:01 AM UTC 24
Finished Sep 11 09:59:03 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243982120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3243982120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/274.edn_genbits.3025365138
Short name T947
Test name
Test status
Simulation time 41218498 ps
CPU time 1.65 seconds
Started Sep 11 09:59:02 AM UTC 24
Finished Sep 11 09:59:04 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025365138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3025365138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/275.edn_genbits.3188006813
Short name T945
Test name
Test status
Simulation time 219571860 ps
CPU time 1.19 seconds
Started Sep 11 09:59:02 AM UTC 24
Finished Sep 11 09:59:04 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188006813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3188006813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/276.edn_genbits.516775383
Short name T946
Test name
Test status
Simulation time 83186005 ps
CPU time 1.44 seconds
Started Sep 11 09:59:02 AM UTC 24
Finished Sep 11 09:59:04 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516775383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 276.edn_genbits.516775383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/277.edn_genbits.3684429630
Short name T952
Test name
Test status
Simulation time 76312583 ps
CPU time 1.69 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684429630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3684429630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/278.edn_genbits.1055886297
Short name T948
Test name
Test status
Simulation time 48028093 ps
CPU time 1.49 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:05 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055886297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1055886297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/279.edn_genbits.504269472
Short name T950
Test name
Test status
Simulation time 88515105 ps
CPU time 1.52 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504269472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 279.edn_genbits.504269472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_alert.493150276
Short name T200
Test name
Test status
Simulation time 29718670 ps
CPU time 1.76 seconds
Started Sep 11 09:54:26 AM UTC 24
Finished Sep 11 09:54:29 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493150276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.edn_alert.493150276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_alert_test.4218992660
Short name T436
Test name
Test status
Simulation time 32809623 ps
CPU time 1.36 seconds
Started Sep 11 09:54:30 AM UTC 24
Finished Sep 11 09:54:32 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218992660 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4218992660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_disable.1491424479
Short name T433
Test name
Test status
Simulation time 19793248 ps
CPU time 1.35 seconds
Started Sep 11 09:54:27 AM UTC 24
Finished Sep 11 09:54:30 AM UTC 24
Peak memory 226284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491424479 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1491424479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.3694607602
Short name T434
Test name
Test status
Simulation time 94034223 ps
CPU time 1.41 seconds
Started Sep 11 09:54:27 AM UTC 24
Finished Sep 11 09:54:30 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694607602 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.3694607602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_err.3536464260
Short name T175
Test name
Test status
Simulation time 18714886 ps
CPU time 1.52 seconds
Started Sep 11 09:54:26 AM UTC 24
Finished Sep 11 09:54:29 AM UTC 24
Peak memory 236952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536464260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.3536464260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_genbits.4116445725
Short name T430
Test name
Test status
Simulation time 82788703 ps
CPU time 1.85 seconds
Started Sep 11 09:54:24 AM UTC 24
Finished Sep 11 09:54:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116445725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4116445725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_intr.731713197
Short name T432
Test name
Test status
Simulation time 29138239 ps
CPU time 1.45 seconds
Started Sep 11 09:54:26 AM UTC 24
Finished Sep 11 09:54:29 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731713197 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.731713197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_smoke.4206183383
Short name T429
Test name
Test status
Simulation time 23245241 ps
CPU time 1.35 seconds
Started Sep 11 09:54:24 AM UTC 24
Finished Sep 11 09:54:26 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206183383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.4206183383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/28.edn_stress_all.2982020053
Short name T431
Test name
Test status
Simulation time 31877382 ps
CPU time 1.96 seconds
Started Sep 11 09:54:25 AM UTC 24
Finished Sep 11 09:54:28 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982020053 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2982020053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/280.edn_genbits.2980360079
Short name T949
Test name
Test status
Simulation time 29636956 ps
CPU time 1.44 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 230656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980360079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2980360079
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/281.edn_genbits.1228160459
Short name T951
Test name
Test status
Simulation time 187199749 ps
CPU time 1.48 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228160459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1228160459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/282.edn_genbits.1576776551
Short name T953
Test name
Test status
Simulation time 85841758 ps
CPU time 1.57 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576776551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1576776551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/283.edn_genbits.1329006188
Short name T955
Test name
Test status
Simulation time 100326525 ps
CPU time 1.99 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329006188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1329006188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/284.edn_genbits.2376480829
Short name T954
Test name
Test status
Simulation time 37472305 ps
CPU time 1.75 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:06 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376480829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2376480829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/285.edn_genbits.2591758345
Short name T956
Test name
Test status
Simulation time 57663457 ps
CPU time 2.55 seconds
Started Sep 11 09:59:03 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591758345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2591758345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/286.edn_genbits.3779407253
Short name T968
Test name
Test status
Simulation time 120230635 ps
CPU time 2.87 seconds
Started Sep 11 09:59:04 AM UTC 24
Finished Sep 11 09:59:08 AM UTC 24
Peak memory 231764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779407253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3779407253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/287.edn_genbits.4202443409
Short name T964
Test name
Test status
Simulation time 190379670 ps
CPU time 2.48 seconds
Started Sep 11 09:59:04 AM UTC 24
Finished Sep 11 09:59:08 AM UTC 24
Peak memory 231644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202443409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4202443409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/288.edn_genbits.2763927928
Short name T962
Test name
Test status
Simulation time 75275594 ps
CPU time 1.89 seconds
Started Sep 11 09:59:04 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763927928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2763927928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/289.edn_genbits.4038241459
Short name T957
Test name
Test status
Simulation time 55824673 ps
CPU time 1.34 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038241459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4038241459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_alert.1648390004
Short name T181
Test name
Test status
Simulation time 73117466 ps
CPU time 1.52 seconds
Started Sep 11 09:54:31 AM UTC 24
Finished Sep 11 09:54:33 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648390004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.1648390004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_alert_test.96446096
Short name T442
Test name
Test status
Simulation time 14949815 ps
CPU time 1.45 seconds
Started Sep 11 09:54:34 AM UTC 24
Finished Sep 11 09:54:37 AM UTC 24
Peak memory 216864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96446096 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.96446096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_disable.881423608
Short name T438
Test name
Test status
Simulation time 60682607 ps
CPU time 1.3 seconds
Started Sep 11 09:54:33 AM UTC 24
Finished Sep 11 09:54:35 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881423608 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.881423608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.2879882592
Short name T443
Test name
Test status
Simulation time 46554307 ps
CPU time 1.57 seconds
Started Sep 11 09:54:34 AM UTC 24
Finished Sep 11 09:54:37 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879882592 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.2879882592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_err.582984379
Short name T439
Test name
Test status
Simulation time 22060245 ps
CPU time 1.73 seconds
Started Sep 11 09:54:33 AM UTC 24
Finished Sep 11 09:54:36 AM UTC 24
Peak memory 228296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582984379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.edn_err.582984379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_intr.2833704267
Short name T437
Test name
Test status
Simulation time 38737992 ps
CPU time 1.34 seconds
Started Sep 11 09:54:31 AM UTC 24
Finished Sep 11 09:54:33 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833704267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.2833704267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_smoke.1035607277
Short name T435
Test name
Test status
Simulation time 115908331 ps
CPU time 1.24 seconds
Started Sep 11 09:54:30 AM UTC 24
Finished Sep 11 09:54:32 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035607277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.1035607277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/29.edn_stress_all.282146231
Short name T441
Test name
Test status
Simulation time 288602563 ps
CPU time 4.93 seconds
Started Sep 11 09:54:30 AM UTC 24
Finished Sep 11 09:54:36 AM UTC 24
Peak memory 229504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282146231 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.282146231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/290.edn_genbits.2748871884
Short name T963
Test name
Test status
Simulation time 44001797 ps
CPU time 1.88 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748871884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2748871884
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/291.edn_genbits.1293848438
Short name T969
Test name
Test status
Simulation time 121412806 ps
CPU time 3.19 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:09 AM UTC 24
Peak memory 229440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293848438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1293848438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/292.edn_genbits.1654278086
Short name T961
Test name
Test status
Simulation time 62686750 ps
CPU time 1.62 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654278086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1654278086
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/293.edn_genbits.3409679370
Short name T959
Test name
Test status
Simulation time 41873375 ps
CPU time 1.54 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409679370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3409679370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/294.edn_genbits.3051842854
Short name T960
Test name
Test status
Simulation time 62727700 ps
CPU time 1.52 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051842854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3051842854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/295.edn_genbits.1185536540
Short name T958
Test name
Test status
Simulation time 115641977 ps
CPU time 1.11 seconds
Started Sep 11 09:59:05 AM UTC 24
Finished Sep 11 09:59:07 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185536540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1185536540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/296.edn_genbits.2041720542
Short name T965
Test name
Test status
Simulation time 79209319 ps
CPU time 1.29 seconds
Started Sep 11 09:59:06 AM UTC 24
Finished Sep 11 09:59:08 AM UTC 24
Peak memory 227788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041720542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2041720542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/297.edn_genbits.1987784952
Short name T967
Test name
Test status
Simulation time 28505459 ps
CPU time 1.31 seconds
Started Sep 11 09:59:06 AM UTC 24
Finished Sep 11 09:59:08 AM UTC 24
Peak memory 230084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987784952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1987784952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/298.edn_genbits.3535833912
Short name T970
Test name
Test status
Simulation time 65086080 ps
CPU time 2.63 seconds
Started Sep 11 09:59:06 AM UTC 24
Finished Sep 11 09:59:10 AM UTC 24
Peak memory 231488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535833912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3535833912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/299.edn_genbits.2359031194
Short name T966
Test name
Test status
Simulation time 51501370 ps
CPU time 1.15 seconds
Started Sep 11 09:59:06 AM UTC 24
Finished Sep 11 09:59:08 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359031194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2359031194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_alert_test.1193523041
Short name T130
Test name
Test status
Simulation time 43582535 ps
CPU time 1.18 seconds
Started Sep 11 09:51:17 AM UTC 24
Finished Sep 11 09:51:19 AM UTC 24
Peak memory 216272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193523041 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1193523041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.3773711765
Short name T22
Test name
Test status
Simulation time 473664325 ps
CPU time 1.58 seconds
Started Sep 11 09:51:15 AM UTC 24
Finished Sep 11 09:51:18 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773711765 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.3773711765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_genbits.297861989
Short name T57
Test name
Test status
Simulation time 45782121 ps
CPU time 2.02 seconds
Started Sep 11 09:51:09 AM UTC 24
Finished Sep 11 09:51:12 AM UTC 24
Peak memory 229508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297861989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_genbits.297861989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_intr.1814246875
Short name T71
Test name
Test status
Simulation time 20395051 ps
CPU time 1.76 seconds
Started Sep 11 09:51:11 AM UTC 24
Finished Sep 11 09:51:14 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814246875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.1814246875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_sec_cm.315192739
Short name T26
Test name
Test status
Simulation time 4872180569 ps
CPU time 13.37 seconds
Started Sep 11 09:51:17 AM UTC 24
Finished Sep 11 09:51:31 AM UTC 24
Peak memory 262496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315192739 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.315192739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_smoke.3354586823
Short name T70
Test name
Test status
Simulation time 18705819 ps
CPU time 1.37 seconds
Started Sep 11 09:51:08 AM UTC 24
Finished Sep 11 09:51:10 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354586823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.3354586823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/3.edn_stress_all.2865111782
Short name T112
Test name
Test status
Simulation time 669184293 ps
CPU time 4.61 seconds
Started Sep 11 09:51:11 AM UTC 24
Finished Sep 11 09:51:17 AM UTC 24
Peak memory 227388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865111782 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2865111782
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_alert.2434903514
Short name T156
Test name
Test status
Simulation time 70793729 ps
CPU time 1.67 seconds
Started Sep 11 09:54:37 AM UTC 24
Finished Sep 11 09:54:40 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434903514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.2434903514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_alert_test.1734972835
Short name T448
Test name
Test status
Simulation time 14851471 ps
CPU time 1.35 seconds
Started Sep 11 09:54:41 AM UTC 24
Finished Sep 11 09:54:43 AM UTC 24
Peak memory 217040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734972835 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1734972835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_disable.1187769212
Short name T446
Test name
Test status
Simulation time 17667824 ps
CPU time 1.32 seconds
Started Sep 11 09:54:39 AM UTC 24
Finished Sep 11 09:54:41 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187769212 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1187769212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.778343665
Short name T447
Test name
Test status
Simulation time 439185115 ps
CPU time 1.97 seconds
Started Sep 11 09:54:40 AM UTC 24
Finished Sep 11 09:54:43 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778343665 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.778343665
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_err.2832248480
Short name T223
Test name
Test status
Simulation time 19553111 ps
CPU time 1.49 seconds
Started Sep 11 09:54:38 AM UTC 24
Finished Sep 11 09:54:40 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832248480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.2832248480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_genbits.3188751916
Short name T98
Test name
Test status
Simulation time 45856895 ps
CPU time 2.51 seconds
Started Sep 11 09:54:36 AM UTC 24
Finished Sep 11 09:54:40 AM UTC 24
Peak memory 229576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188751916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3188751916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_intr.4038290238
Short name T445
Test name
Test status
Simulation time 23266643 ps
CPU time 1.7 seconds
Started Sep 11 09:54:36 AM UTC 24
Finished Sep 11 09:54:39 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038290238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.4038290238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_smoke.1715005720
Short name T444
Test name
Test status
Simulation time 55559605 ps
CPU time 1.38 seconds
Started Sep 11 09:54:35 AM UTC 24
Finished Sep 11 09:54:38 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715005720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_smoke.1715005720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/30.edn_stress_all.828722757
Short name T450
Test name
Test status
Simulation time 227606607 ps
CPU time 6.76 seconds
Started Sep 11 09:54:36 AM UTC 24
Finished Sep 11 09:54:44 AM UTC 24
Peak memory 229448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828722757 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.828722757
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_alert.2435250675
Short name T204
Test name
Test status
Simulation time 35026891 ps
CPU time 1.8 seconds
Started Sep 11 09:54:44 AM UTC 24
Finished Sep 11 09:54:47 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435250675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_alert.2435250675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_alert_test.2215847456
Short name T454
Test name
Test status
Simulation time 11589535 ps
CPU time 1.25 seconds
Started Sep 11 09:54:46 AM UTC 24
Finished Sep 11 09:54:49 AM UTC 24
Peak memory 216364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215847456 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2215847456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_disable.780452122
Short name T452
Test name
Test status
Simulation time 22291481 ps
CPU time 1.35 seconds
Started Sep 11 09:54:45 AM UTC 24
Finished Sep 11 09:54:48 AM UTC 24
Peak memory 216488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780452122 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.780452122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.4246981966
Short name T453
Test name
Test status
Simulation time 42470870 ps
CPU time 1.49 seconds
Started Sep 11 09:54:45 AM UTC 24
Finished Sep 11 09:54:48 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246981966 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.4246981966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_err.262934406
Short name T451
Test name
Test status
Simulation time 57413794 ps
CPU time 1.66 seconds
Started Sep 11 09:54:44 AM UTC 24
Finished Sep 11 09:54:47 AM UTC 24
Peak memory 236956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262934406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.edn_err.262934406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_genbits.680541899
Short name T343
Test name
Test status
Simulation time 51297350 ps
CPU time 2.31 seconds
Started Sep 11 09:54:41 AM UTC 24
Finished Sep 11 09:54:44 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680541899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_genbits.680541899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_intr.644310264
Short name T106
Test name
Test status
Simulation time 75852389 ps
CPU time 1.32 seconds
Started Sep 11 09:54:43 AM UTC 24
Finished Sep 11 09:54:45 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644310264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.644310264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_smoke.984589013
Short name T449
Test name
Test status
Simulation time 16187767 ps
CPU time 1.35 seconds
Started Sep 11 09:54:41 AM UTC 24
Finished Sep 11 09:54:43 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984589013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_smoke.984589013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_stress_all.997902949
Short name T456
Test name
Test status
Simulation time 297682811 ps
CPU time 8.38 seconds
Started Sep 11 09:54:41 AM UTC 24
Finished Sep 11 09:54:50 AM UTC 24
Peak memory 229432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997902949 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.997902949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.2992882256
Short name T246
Test name
Test status
Simulation time 2626431341 ps
CPU time 77.85 seconds
Started Sep 11 09:54:42 AM UTC 24
Finished Sep 11 09:56:02 AM UTC 24
Peak memory 231824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2992882256 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all
_with_rand_reset.2992882256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_alert.1043025283
Short name T99
Test name
Test status
Simulation time 29625104 ps
CPU time 1.68 seconds
Started Sep 11 09:54:51 AM UTC 24
Finished Sep 11 09:54:53 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043025283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.1043025283
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_alert_test.13979530
Short name T460
Test name
Test status
Simulation time 36208366 ps
CPU time 1.06 seconds
Started Sep 11 09:54:53 AM UTC 24
Finished Sep 11 09:54:55 AM UTC 24
Peak memory 216308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13979530 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.13979530
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_disable.2629675973
Short name T215
Test name
Test status
Simulation time 19947557 ps
CPU time 1.35 seconds
Started Sep 11 09:54:52 AM UTC 24
Finished Sep 11 09:54:54 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629675973 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2629675973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.122743091
Short name T459
Test name
Test status
Simulation time 122227228 ps
CPU time 1.5 seconds
Started Sep 11 09:54:52 AM UTC 24
Finished Sep 11 09:54:54 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122743091 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.122743091
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_err.736244123
Short name T458
Test name
Test status
Simulation time 24544384 ps
CPU time 1.27 seconds
Started Sep 11 09:54:51 AM UTC 24
Finished Sep 11 09:54:53 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736244123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 32.edn_err.736244123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_genbits.2495086124
Short name T457
Test name
Test status
Simulation time 40895737 ps
CPU time 2.33 seconds
Started Sep 11 09:54:48 AM UTC 24
Finished Sep 11 09:54:51 AM UTC 24
Peak memory 229520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495086124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2495086124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_intr.397251461
Short name T103
Test name
Test status
Simulation time 24803441 ps
CPU time 1.21 seconds
Started Sep 11 09:54:50 AM UTC 24
Finished Sep 11 09:54:52 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397251461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.397251461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_smoke.2831377547
Short name T455
Test name
Test status
Simulation time 25411126 ps
CPU time 1.39 seconds
Started Sep 11 09:54:47 AM UTC 24
Finished Sep 11 09:54:50 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831377547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.2831377547
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_stress_all.625344337
Short name T317
Test name
Test status
Simulation time 669651821 ps
CPU time 5.79 seconds
Started Sep 11 09:54:49 AM UTC 24
Finished Sep 11 09:54:55 AM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625344337 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.625344337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.2566715472
Short name T544
Test name
Test status
Simulation time 2485507243 ps
CPU time 75.72 seconds
Started Sep 11 09:54:49 AM UTC 24
Finished Sep 11 09:56:06 AM UTC 24
Peak memory 229772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2566715472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all
_with_rand_reset.2566715472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_alert.669062281
Short name T465
Test name
Test status
Simulation time 43659493 ps
CPU time 1.69 seconds
Started Sep 11 09:54:56 AM UTC 24
Finished Sep 11 09:54:59 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669062281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_alert.669062281
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_alert_test.491333911
Short name T469
Test name
Test status
Simulation time 21091820 ps
CPU time 1.4 seconds
Started Sep 11 09:54:59 AM UTC 24
Finished Sep 11 09:55:02 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491333911 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.491333911
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_disable.2776479820
Short name T466
Test name
Test status
Simulation time 10628222 ps
CPU time 1.32 seconds
Started Sep 11 09:54:58 AM UTC 24
Finished Sep 11 09:55:00 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776479820 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2776479820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.39768487
Short name T467
Test name
Test status
Simulation time 53357531 ps
CPU time 1.8 seconds
Started Sep 11 09:54:58 AM UTC 24
Finished Sep 11 09:55:00 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39768487 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.39768487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_err.3381178153
Short name T464
Test name
Test status
Simulation time 50100858 ps
CPU time 1.4 seconds
Started Sep 11 09:54:56 AM UTC 24
Finished Sep 11 09:54:59 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381178153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.3381178153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_genbits.2275092890
Short name T462
Test name
Test status
Simulation time 114164701 ps
CPU time 1.61 seconds
Started Sep 11 09:54:54 AM UTC 24
Finished Sep 11 09:54:57 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275092890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2275092890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_intr.3338330346
Short name T463
Test name
Test status
Simulation time 28042596 ps
CPU time 1.34 seconds
Started Sep 11 09:54:55 AM UTC 24
Finished Sep 11 09:54:58 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338330346 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.3338330346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_smoke.3937678348
Short name T461
Test name
Test status
Simulation time 53990836 ps
CPU time 1.34 seconds
Started Sep 11 09:54:54 AM UTC 24
Finished Sep 11 09:54:56 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937678348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.3937678348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/33.edn_stress_all.2888594502
Short name T468
Test name
Test status
Simulation time 304750220 ps
CPU time 4.73 seconds
Started Sep 11 09:54:55 AM UTC 24
Finished Sep 11 09:55:01 AM UTC 24
Peak memory 229520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888594502 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2888594502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_alert.3686345417
Short name T288
Test name
Test status
Simulation time 40045122 ps
CPU time 1.48 seconds
Started Sep 11 09:55:02 AM UTC 24
Finished Sep 11 09:55:05 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686345417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_alert.3686345417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_alert_test.1884234914
Short name T474
Test name
Test status
Simulation time 22388657 ps
CPU time 1.2 seconds
Started Sep 11 09:55:04 AM UTC 24
Finished Sep 11 09:55:07 AM UTC 24
Peak memory 226524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884234914 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1884234914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_disable.4025692955
Short name T472
Test name
Test status
Simulation time 52491906 ps
CPU time 1.21 seconds
Started Sep 11 09:55:03 AM UTC 24
Finished Sep 11 09:55:06 AM UTC 24
Peak memory 216124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025692955 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4025692955
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.260287922
Short name T289
Test name
Test status
Simulation time 28712755 ps
CPU time 1.64 seconds
Started Sep 11 09:55:04 AM UTC 24
Finished Sep 11 09:55:07 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260287922 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.260287922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_err.2670998455
Short name T473
Test name
Test status
Simulation time 25827631 ps
CPU time 1.35 seconds
Started Sep 11 09:55:03 AM UTC 24
Finished Sep 11 09:55:06 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670998455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.edn_err.2670998455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_intr.2354064774
Short name T471
Test name
Test status
Simulation time 41617806 ps
CPU time 1.26 seconds
Started Sep 11 09:55:02 AM UTC 24
Finished Sep 11 09:55:04 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354064774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.2354064774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_smoke.552182239
Short name T470
Test name
Test status
Simulation time 45304685 ps
CPU time 1.25 seconds
Started Sep 11 09:55:00 AM UTC 24
Finished Sep 11 09:55:02 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552182239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_smoke.552182239
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_stress_all.2387344932
Short name T479
Test name
Test status
Simulation time 423253660 ps
CPU time 9.73 seconds
Started Sep 11 09:55:01 AM UTC 24
Finished Sep 11 09:55:12 AM UTC 24
Peak memory 231576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387344932 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2387344932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.2462173721
Short name T247
Test name
Test status
Simulation time 6974376346 ps
CPU time 93.22 seconds
Started Sep 11 09:55:01 AM UTC 24
Finished Sep 11 09:56:36 AM UTC 24
Peak memory 229980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2462173721 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all
_with_rand_reset.2462173721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_alert.2769418786
Short name T164
Test name
Test status
Simulation time 55300710 ps
CPU time 1.7 seconds
Started Sep 11 09:55:08 AM UTC 24
Finished Sep 11 09:55:11 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769418786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.2769418786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_alert_test.1566712584
Short name T482
Test name
Test status
Simulation time 20124127 ps
CPU time 1.1 seconds
Started Sep 11 09:55:11 AM UTC 24
Finished Sep 11 09:55:13 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566712584 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1566712584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_disable.2647853123
Short name T480
Test name
Test status
Simulation time 27609281 ps
CPU time 1.12 seconds
Started Sep 11 09:55:10 AM UTC 24
Finished Sep 11 09:55:12 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647853123 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2647853123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.2386036383
Short name T483
Test name
Test status
Simulation time 61655895 ps
CPU time 1.41 seconds
Started Sep 11 09:55:11 AM UTC 24
Finished Sep 11 09:55:13 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386036383 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.2386036383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_err.2386311421
Short name T478
Test name
Test status
Simulation time 29375614 ps
CPU time 1.37 seconds
Started Sep 11 09:55:09 AM UTC 24
Finished Sep 11 09:55:11 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386311421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.2386311421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_genbits.1911402864
Short name T476
Test name
Test status
Simulation time 58968463 ps
CPU time 2.24 seconds
Started Sep 11 09:55:05 AM UTC 24
Finished Sep 11 09:55:09 AM UTC 24
Peak memory 231508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911402864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1911402864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_intr.489980035
Short name T477
Test name
Test status
Simulation time 35237606 ps
CPU time 1.06 seconds
Started Sep 11 09:55:08 AM UTC 24
Finished Sep 11 09:55:10 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489980035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.489980035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_smoke.685111210
Short name T475
Test name
Test status
Simulation time 34393581 ps
CPU time 1.2 seconds
Started Sep 11 09:55:05 AM UTC 24
Finished Sep 11 09:55:08 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685111210 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.edn_smoke.685111210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/35.edn_stress_all.1813432162
Short name T481
Test name
Test status
Simulation time 304575121 ps
CPU time 5.18 seconds
Started Sep 11 09:55:07 AM UTC 24
Finished Sep 11 09:55:13 AM UTC 24
Peak memory 229444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813432162 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1813432162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_alert.3929700544
Short name T488
Test name
Test status
Simulation time 68477843 ps
CPU time 1.61 seconds
Started Sep 11 09:55:15 AM UTC 24
Finished Sep 11 09:55:17 AM UTC 24
Peak memory 228432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929700544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.3929700544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_alert_test.1915767139
Short name T491
Test name
Test status
Simulation time 14863187 ps
CPU time 1.19 seconds
Started Sep 11 09:55:18 AM UTC 24
Finished Sep 11 09:55:20 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915767139 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1915767139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_disable.272959969
Short name T100
Test name
Test status
Simulation time 20973090 ps
CPU time 1.18 seconds
Started Sep 11 09:55:16 AM UTC 24
Finished Sep 11 09:55:18 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272959969 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.272959969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.841206515
Short name T489
Test name
Test status
Simulation time 49853945 ps
CPU time 1.45 seconds
Started Sep 11 09:55:17 AM UTC 24
Finished Sep 11 09:55:19 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841206515 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.841206515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_err.62341952
Short name T487
Test name
Test status
Simulation time 24211355 ps
CPU time 1.22 seconds
Started Sep 11 09:55:15 AM UTC 24
Finished Sep 11 09:55:17 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62341952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 36.edn_err.62341952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_genbits.4027702377
Short name T486
Test name
Test status
Simulation time 30830469 ps
CPU time 2.25 seconds
Started Sep 11 09:55:13 AM UTC 24
Finished Sep 11 09:55:17 AM UTC 24
Peak memory 229444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027702377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4027702377
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_intr.431721838
Short name T485
Test name
Test status
Simulation time 22071274 ps
CPU time 1.71 seconds
Started Sep 11 09:55:13 AM UTC 24
Finished Sep 11 09:55:16 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431721838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.431721838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_smoke.2370631917
Short name T484
Test name
Test status
Simulation time 99080850 ps
CPU time 1.22 seconds
Started Sep 11 09:55:12 AM UTC 24
Finished Sep 11 09:55:14 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370631917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.2370631917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/36.edn_stress_all.3935774800
Short name T490
Test name
Test status
Simulation time 2346563067 ps
CPU time 5.05 seconds
Started Sep 11 09:55:13 AM UTC 24
Finished Sep 11 09:55:19 AM UTC 24
Peak memory 231948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935774800 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3935774800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_alert.2873708845
Short name T495
Test name
Test status
Simulation time 81665949 ps
CPU time 1.61 seconds
Started Sep 11 09:55:21 AM UTC 24
Finished Sep 11 09:55:24 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873708845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.2873708845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_alert_test.2733986753
Short name T499
Test name
Test status
Simulation time 25196327 ps
CPU time 1.3 seconds
Started Sep 11 09:55:24 AM UTC 24
Finished Sep 11 09:55:27 AM UTC 24
Peak memory 217040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733986753 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2733986753
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_disable.1411413173
Short name T497
Test name
Test status
Simulation time 15388255 ps
CPU time 1.38 seconds
Started Sep 11 09:55:22 AM UTC 24
Finished Sep 11 09:55:25 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411413173 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1411413173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.3347975102
Short name T498
Test name
Test status
Simulation time 39790548 ps
CPU time 1.5 seconds
Started Sep 11 09:55:23 AM UTC 24
Finished Sep 11 09:55:26 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347975102 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.3347975102
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_err.2574871987
Short name T496
Test name
Test status
Simulation time 22956783 ps
CPU time 1.73 seconds
Started Sep 11 09:55:21 AM UTC 24
Finished Sep 11 09:55:24 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574871987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.2574871987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_genbits.4196713923
Short name T493
Test name
Test status
Simulation time 62147054 ps
CPU time 1.78 seconds
Started Sep 11 09:55:18 AM UTC 24
Finished Sep 11 09:55:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196713923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4196713923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_intr.4086957277
Short name T494
Test name
Test status
Simulation time 32360413 ps
CPU time 1.36 seconds
Started Sep 11 09:55:20 AM UTC 24
Finished Sep 11 09:55:23 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086957277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.4086957277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_smoke.3213936739
Short name T492
Test name
Test status
Simulation time 26669668 ps
CPU time 1.44 seconds
Started Sep 11 09:55:18 AM UTC 24
Finished Sep 11 09:55:20 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213936739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.3213936739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/37.edn_stress_all.3128449355
Short name T502
Test name
Test status
Simulation time 369613480 ps
CPU time 8.6 seconds
Started Sep 11 09:55:19 AM UTC 24
Finished Sep 11 09:55:29 AM UTC 24
Peak memory 231568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128449355 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3128449355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_alert.564720393
Short name T505
Test name
Test status
Simulation time 41362583 ps
CPU time 1.82 seconds
Started Sep 11 09:55:28 AM UTC 24
Finished Sep 11 09:55:31 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564720393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_alert.564720393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_alert_test.202538653
Short name T507
Test name
Test status
Simulation time 30219931 ps
CPU time 1.42 seconds
Started Sep 11 09:55:31 AM UTC 24
Finished Sep 11 09:55:34 AM UTC 24
Peak memory 216800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202538653 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.202538653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_disable.3641924935
Short name T506
Test name
Test status
Simulation time 17434082 ps
CPU time 1.32 seconds
Started Sep 11 09:55:30 AM UTC 24
Finished Sep 11 09:55:33 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641924935 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3641924935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.3295462181
Short name T508
Test name
Test status
Simulation time 156974945 ps
CPU time 1.54 seconds
Started Sep 11 09:55:31 AM UTC 24
Finished Sep 11 09:55:34 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295462181 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.3295462181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_err.227106499
Short name T161
Test name
Test status
Simulation time 24905677 ps
CPU time 1.27 seconds
Started Sep 11 09:55:30 AM UTC 24
Finished Sep 11 09:55:33 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227106499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.edn_err.227106499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_genbits.298568482
Short name T501
Test name
Test status
Simulation time 114356448 ps
CPU time 2.12 seconds
Started Sep 11 09:55:26 AM UTC 24
Finished Sep 11 09:55:29 AM UTC 24
Peak memory 231488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298568482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.298568482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_intr.480708758
Short name T503
Test name
Test status
Simulation time 41672672 ps
CPU time 1.24 seconds
Started Sep 11 09:55:28 AM UTC 24
Finished Sep 11 09:55:30 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480708758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.480708758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_smoke.2195173848
Short name T500
Test name
Test status
Simulation time 25456802 ps
CPU time 1.23 seconds
Started Sep 11 09:55:25 AM UTC 24
Finished Sep 11 09:55:27 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195173848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.2195173848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/38.edn_stress_all.1909016469
Short name T504
Test name
Test status
Simulation time 370101422 ps
CPU time 2.81 seconds
Started Sep 11 09:55:27 AM UTC 24
Finished Sep 11 09:55:31 AM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909016469 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1909016469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_alert.1822599587
Short name T144
Test name
Test status
Simulation time 56209636 ps
CPU time 1.92 seconds
Started Sep 11 09:55:36 AM UTC 24
Finished Sep 11 09:55:39 AM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822599587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.1822599587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_alert_test.2820165903
Short name T514
Test name
Test status
Simulation time 38505057 ps
CPU time 1.28 seconds
Started Sep 11 09:55:39 AM UTC 24
Finished Sep 11 09:55:41 AM UTC 24
Peak memory 216964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820165903 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2820165903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_disable.1358984938
Short name T513
Test name
Test status
Simulation time 14076346 ps
CPU time 1.41 seconds
Started Sep 11 09:55:38 AM UTC 24
Finished Sep 11 09:55:40 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358984938 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1358984938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.3986641076
Short name T515
Test name
Test status
Simulation time 80756068 ps
CPU time 1.6 seconds
Started Sep 11 09:55:39 AM UTC 24
Finished Sep 11 09:55:42 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986641076 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.3986641076
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_err.4125228392
Short name T512
Test name
Test status
Simulation time 22007363 ps
CPU time 1.31 seconds
Started Sep 11 09:55:37 AM UTC 24
Finished Sep 11 09:55:39 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125228392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.4125228392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_genbits.1940781136
Short name T337
Test name
Test status
Simulation time 28766551 ps
CPU time 1.66 seconds
Started Sep 11 09:55:33 AM UTC 24
Finished Sep 11 09:55:36 AM UTC 24
Peak memory 230604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940781136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1940781136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_intr.2285226232
Short name T440
Test name
Test status
Simulation time 26722769 ps
CPU time 1.21 seconds
Started Sep 11 09:55:35 AM UTC 24
Finished Sep 11 09:55:37 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285226232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.2285226232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_smoke.2257853156
Short name T509
Test name
Test status
Simulation time 44215838 ps
CPU time 1.42 seconds
Started Sep 11 09:55:32 AM UTC 24
Finished Sep 11 09:55:35 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257853156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.2257853156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/39.edn_stress_all.2233701438
Short name T510
Test name
Test status
Simulation time 546979501 ps
CPU time 3.72 seconds
Started Sep 11 09:55:33 AM UTC 24
Finished Sep 11 09:55:38 AM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233701438 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2233701438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_alert.3857050579
Short name T59
Test name
Test status
Simulation time 32016866 ps
CPU time 1.64 seconds
Started Sep 11 09:51:20 AM UTC 24
Finished Sep 11 09:51:23 AM UTC 24
Peak memory 230468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857050579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.3857050579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_alert_test.1589379618
Short name T346
Test name
Test status
Simulation time 17617305 ps
CPU time 1.14 seconds
Started Sep 11 09:51:24 AM UTC 24
Finished Sep 11 09:51:27 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589379618 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1589379618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_disable.1509051299
Short name T86
Test name
Test status
Simulation time 36648944 ps
CPU time 1.03 seconds
Started Sep 11 09:51:22 AM UTC 24
Finished Sep 11 09:51:24 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509051299 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1509051299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.3965197997
Short name T23
Test name
Test status
Simulation time 66797682 ps
CPU time 1.75 seconds
Started Sep 11 09:51:23 AM UTC 24
Finished Sep 11 09:51:26 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965197997 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.3965197997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_err.3658945474
Short name T207
Test name
Test status
Simulation time 29321366 ps
CPU time 1.19 seconds
Started Sep 11 09:51:21 AM UTC 24
Finished Sep 11 09:51:24 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658945474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.3658945474
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_genbits.150622378
Short name T42
Test name
Test status
Simulation time 83578632 ps
CPU time 2.18 seconds
Started Sep 11 09:51:18 AM UTC 24
Finished Sep 11 09:51:21 AM UTC 24
Peak memory 229508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150622378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_genbits.150622378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_regwen.3373283099
Short name T253
Test name
Test status
Simulation time 26227097 ps
CPU time 1.26 seconds
Started Sep 11 09:51:18 AM UTC 24
Finished Sep 11 09:51:20 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373283099 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_regwen.3373283099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_sec_cm.3444307619
Short name T62
Test name
Test status
Simulation time 3520772893 ps
CPU time 8.23 seconds
Started Sep 11 09:51:23 AM UTC 24
Finished Sep 11 09:51:33 AM UTC 24
Peak memory 260640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444307619 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3444307619
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_smoke.1688459704
Short name T116
Test name
Test status
Simulation time 16180664 ps
CPU time 1.31 seconds
Started Sep 11 09:51:17 AM UTC 24
Finished Sep 11 09:51:19 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688459704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.1688459704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/4.edn_stress_all.2763975569
Short name T114
Test name
Test status
Simulation time 331708700 ps
CPU time 4.87 seconds
Started Sep 11 09:51:19 AM UTC 24
Finished Sep 11 09:51:25 AM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763975569 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2763975569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_alert.3807187824
Short name T519
Test name
Test status
Simulation time 58929766 ps
CPU time 1.57 seconds
Started Sep 11 09:55:43 AM UTC 24
Finished Sep 11 09:55:46 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807187824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.3807187824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_alert_test.2896253781
Short name T522
Test name
Test status
Simulation time 34035469 ps
CPU time 1.35 seconds
Started Sep 11 09:55:47 AM UTC 24
Finished Sep 11 09:55:49 AM UTC 24
Peak memory 216980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896253781 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2896253781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_disable.2301944867
Short name T521
Test name
Test status
Simulation time 13628692 ps
CPU time 1.43 seconds
Started Sep 11 09:55:45 AM UTC 24
Finished Sep 11 09:55:48 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301944867 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2301944867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.2334694186
Short name T290
Test name
Test status
Simulation time 72016406 ps
CPU time 1.36 seconds
Started Sep 11 09:55:47 AM UTC 24
Finished Sep 11 09:55:49 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334694186 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.2334694186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_err.1278729372
Short name T518
Test name
Test status
Simulation time 28294060 ps
CPU time 1.11 seconds
Started Sep 11 09:55:43 AM UTC 24
Finished Sep 11 09:55:45 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278729372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.1278729372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_genbits.1977165577
Short name T345
Test name
Test status
Simulation time 41252296 ps
CPU time 1.7 seconds
Started Sep 11 09:55:40 AM UTC 24
Finished Sep 11 09:55:43 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977165577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1977165577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_intr.1606515929
Short name T517
Test name
Test status
Simulation time 28205736 ps
CPU time 1.69 seconds
Started Sep 11 09:55:42 AM UTC 24
Finished Sep 11 09:55:45 AM UTC 24
Peak memory 236960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606515929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.1606515929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_smoke.2838234283
Short name T516
Test name
Test status
Simulation time 27845018 ps
CPU time 1.36 seconds
Started Sep 11 09:55:40 AM UTC 24
Finished Sep 11 09:55:42 AM UTC 24
Peak memory 226264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838234283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.2838234283
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/40.edn_stress_all.3999263754
Short name T520
Test name
Test status
Simulation time 392275264 ps
CPU time 4.17 seconds
Started Sep 11 09:55:41 AM UTC 24
Finished Sep 11 09:55:46 AM UTC 24
Peak memory 229444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999263754 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3999263754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_alert.2399470587
Short name T528
Test name
Test status
Simulation time 86396424 ps
CPU time 1.74 seconds
Started Sep 11 09:55:50 AM UTC 24
Finished Sep 11 09:55:53 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399470587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.2399470587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_alert_test.2165064934
Short name T531
Test name
Test status
Simulation time 64017090 ps
CPU time 1.36 seconds
Started Sep 11 09:55:54 AM UTC 24
Finished Sep 11 09:55:56 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165064934 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2165064934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_disable.194052595
Short name T529
Test name
Test status
Simulation time 14729183 ps
CPU time 1.22 seconds
Started Sep 11 09:55:52 AM UTC 24
Finished Sep 11 09:55:55 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194052595 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.194052595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.2389006848
Short name T530
Test name
Test status
Simulation time 59641876 ps
CPU time 1.51 seconds
Started Sep 11 09:55:52 AM UTC 24
Finished Sep 11 09:55:55 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389006848 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.2389006848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_err.867223317
Short name T198
Test name
Test status
Simulation time 19738885 ps
CPU time 1.59 seconds
Started Sep 11 09:55:52 AM UTC 24
Finished Sep 11 09:55:55 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867223317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.edn_err.867223317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_genbits.3185458677
Short name T526
Test name
Test status
Simulation time 170861343 ps
CPU time 4.16 seconds
Started Sep 11 09:55:47 AM UTC 24
Finished Sep 11 09:55:52 AM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185458677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3185458677
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_intr.3294382034
Short name T527
Test name
Test status
Simulation time 26200516 ps
CPU time 1.44 seconds
Started Sep 11 09:55:50 AM UTC 24
Finished Sep 11 09:55:53 AM UTC 24
Peak memory 228420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294382034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.3294382034
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_smoke.2932485429
Short name T523
Test name
Test status
Simulation time 45604725 ps
CPU time 1.48 seconds
Started Sep 11 09:55:47 AM UTC 24
Finished Sep 11 09:55:49 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932485429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.2932485429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_stress_all.3559147704
Short name T525
Test name
Test status
Simulation time 48928512 ps
CPU time 1.81 seconds
Started Sep 11 09:55:49 AM UTC 24
Finished Sep 11 09:55:52 AM UTC 24
Peak memory 226668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559147704 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3559147704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.55986232
Short name T599
Test name
Test status
Simulation time 5465464567 ps
CPU time 82.08 seconds
Started Sep 11 09:55:50 AM UTC 24
Finished Sep 11 09:57:14 AM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=55986232 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_w
ith_rand_reset.55986232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_alert_test.4019044716
Short name T541
Test name
Test status
Simulation time 33152883 ps
CPU time 1.22 seconds
Started Sep 11 09:56:02 AM UTC 24
Finished Sep 11 09:56:04 AM UTC 24
Peak memory 216160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019044716 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4019044716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_disable.2492741393
Short name T536
Test name
Test status
Simulation time 12476202 ps
CPU time 1.28 seconds
Started Sep 11 09:56:00 AM UTC 24
Finished Sep 11 09:56:02 AM UTC 24
Peak memory 216124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492741393 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2492741393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.1897000404
Short name T539
Test name
Test status
Simulation time 411648155 ps
CPU time 1.25 seconds
Started Sep 11 09:56:01 AM UTC 24
Finished Sep 11 09:56:03 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897000404 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.1897000404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_err.3492257103
Short name T538
Test name
Test status
Simulation time 41048609 ps
CPU time 1.76 seconds
Started Sep 11 09:56:00 AM UTC 24
Finished Sep 11 09:56:03 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492257103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.3492257103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_genbits.2238676265
Short name T533
Test name
Test status
Simulation time 34487436 ps
CPU time 2.24 seconds
Started Sep 11 09:55:56 AM UTC 24
Finished Sep 11 09:55:59 AM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238676265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2238676265
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_intr.3504988211
Short name T534
Test name
Test status
Simulation time 25229009 ps
CPU time 1.31 seconds
Started Sep 11 09:55:57 AM UTC 24
Finished Sep 11 09:55:59 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504988211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.3504988211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_smoke.3262315693
Short name T532
Test name
Test status
Simulation time 86927805 ps
CPU time 1.44 seconds
Started Sep 11 09:55:54 AM UTC 24
Finished Sep 11 09:55:56 AM UTC 24
Peak memory 226264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262315693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_smoke.3262315693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_stress_all.1966346602
Short name T535
Test name
Test status
Simulation time 167817682 ps
CPU time 4.62 seconds
Started Sep 11 09:55:56 AM UTC 24
Finished Sep 11 09:56:01 AM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966346602 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1966346602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.4010985432
Short name T583
Test name
Test status
Simulation time 2168981019 ps
CPU time 51.15 seconds
Started Sep 11 09:55:56 AM UTC 24
Finished Sep 11 09:56:49 AM UTC 24
Peak memory 231836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4010985432 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all
_with_rand_reset.4010985432
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_alert.4099043551
Short name T546
Test name
Test status
Simulation time 37827617 ps
CPU time 1.77 seconds
Started Sep 11 09:56:06 AM UTC 24
Finished Sep 11 09:56:08 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099043551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.4099043551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_alert_test.2557358460
Short name T549
Test name
Test status
Simulation time 33917285 ps
CPU time 1.12 seconds
Started Sep 11 09:56:09 AM UTC 24
Finished Sep 11 09:56:11 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557358460 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2557358460
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.2500720798
Short name T548
Test name
Test status
Simulation time 109626453 ps
CPU time 1.6 seconds
Started Sep 11 09:56:08 AM UTC 24
Finished Sep 11 09:56:10 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500720798 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.2500720798
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_err.1773422258
Short name T205
Test name
Test status
Simulation time 23808145 ps
CPU time 1.44 seconds
Started Sep 11 09:56:07 AM UTC 24
Finished Sep 11 09:56:09 AM UTC 24
Peak memory 246076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773422258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.1773422258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_genbits.3359979821
Short name T543
Test name
Test status
Simulation time 36525966 ps
CPU time 2.02 seconds
Started Sep 11 09:56:03 AM UTC 24
Finished Sep 11 09:56:06 AM UTC 24
Peak memory 231768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359979821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3359979821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_intr.1690650858
Short name T545
Test name
Test status
Simulation time 24449853 ps
CPU time 1.41 seconds
Started Sep 11 09:56:06 AM UTC 24
Finished Sep 11 09:56:08 AM UTC 24
Peak memory 228304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690650858 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.1690650858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_smoke.916076145
Short name T542
Test name
Test status
Simulation time 118015247 ps
CPU time 1.49 seconds
Started Sep 11 09:56:03 AM UTC 24
Finished Sep 11 09:56:06 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916076145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.edn_smoke.916076145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_stress_all.3003953711
Short name T547
Test name
Test status
Simulation time 2765935603 ps
CPU time 5.05 seconds
Started Sep 11 09:56:03 AM UTC 24
Finished Sep 11 09:56:09 AM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003953711 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3003953711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.3506030103
Short name T587
Test name
Test status
Simulation time 2320570715 ps
CPU time 48.77 seconds
Started Sep 11 09:56:04 AM UTC 24
Finished Sep 11 09:56:55 AM UTC 24
Peak memory 231908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3506030103 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all
_with_rand_reset.3506030103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_alert.1176915253
Short name T553
Test name
Test status
Simulation time 63091806 ps
CPU time 1.63 seconds
Started Sep 11 09:56:12 AM UTC 24
Finished Sep 11 09:56:15 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176915253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.1176915253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_alert_test.4157143496
Short name T554
Test name
Test status
Simulation time 44286656 ps
CPU time 1.07 seconds
Started Sep 11 09:56:14 AM UTC 24
Finished Sep 11 09:56:16 AM UTC 24
Peak memory 216200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157143496 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4157143496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.2653534809
Short name T557
Test name
Test status
Simulation time 106107894 ps
CPU time 1.63 seconds
Started Sep 11 09:56:14 AM UTC 24
Finished Sep 11 09:56:16 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653534809 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.2653534809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_err.1230992366
Short name T140
Test name
Test status
Simulation time 25777627 ps
CPU time 1.71 seconds
Started Sep 11 09:56:13 AM UTC 24
Finished Sep 11 09:56:15 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230992366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.1230992366
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_genbits.2552382881
Short name T551
Test name
Test status
Simulation time 77236915 ps
CPU time 1.71 seconds
Started Sep 11 09:56:10 AM UTC 24
Finished Sep 11 09:56:13 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552382881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2552382881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_intr.2067411296
Short name T552
Test name
Test status
Simulation time 35832248 ps
CPU time 0.99 seconds
Started Sep 11 09:56:11 AM UTC 24
Finished Sep 11 09:56:13 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067411296 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.2067411296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_smoke.2705037596
Short name T550
Test name
Test status
Simulation time 33838338 ps
CPU time 1.16 seconds
Started Sep 11 09:56:09 AM UTC 24
Finished Sep 11 09:56:11 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705037596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.2705037596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_stress_all.3179932197
Short name T556
Test name
Test status
Simulation time 410706353 ps
CPU time 5.1 seconds
Started Sep 11 09:56:10 AM UTC 24
Finished Sep 11 09:56:16 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179932197 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3179932197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.1640108440
Short name T723
Test name
Test status
Simulation time 3833352591 ps
CPU time 122.22 seconds
Started Sep 11 09:56:10 AM UTC 24
Finished Sep 11 09:58:15 AM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1640108440 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all
_with_rand_reset.1640108440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_alert.239020141
Short name T560
Test name
Test status
Simulation time 38001086 ps
CPU time 1.67 seconds
Started Sep 11 09:56:17 AM UTC 24
Finished Sep 11 09:56:20 AM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239020141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.edn_alert.239020141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_alert_test.3204972175
Short name T563
Test name
Test status
Simulation time 14597325 ps
CPU time 1.36 seconds
Started Sep 11 09:56:21 AM UTC 24
Finished Sep 11 09:56:23 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204972175 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3204972175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_disable.1602292306
Short name T559
Test name
Test status
Simulation time 21460528 ps
CPU time 1.32 seconds
Started Sep 11 09:56:17 AM UTC 24
Finished Sep 11 09:56:20 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602292306 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1602292306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3823519775
Short name T562
Test name
Test status
Simulation time 163097347 ps
CPU time 1.71 seconds
Started Sep 11 09:56:19 AM UTC 24
Finished Sep 11 09:56:22 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823519775 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3823519775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_err.2429992673
Short name T206
Test name
Test status
Simulation time 35528760 ps
CPU time 1.3 seconds
Started Sep 11 09:56:17 AM UTC 24
Finished Sep 11 09:56:20 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429992673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.2429992673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_genbits.1841077735
Short name T321
Test name
Test status
Simulation time 44702703 ps
CPU time 1.67 seconds
Started Sep 11 09:56:16 AM UTC 24
Finished Sep 11 09:56:19 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841077735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1841077735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_smoke.4183586690
Short name T555
Test name
Test status
Simulation time 29296178 ps
CPU time 1.2 seconds
Started Sep 11 09:56:14 AM UTC 24
Finished Sep 11 09:56:16 AM UTC 24
Peak memory 215908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183586690 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.4183586690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/45.edn_stress_all.2487203929
Short name T561
Test name
Test status
Simulation time 193571814 ps
CPU time 3.45 seconds
Started Sep 11 09:56:16 AM UTC 24
Finished Sep 11 09:56:21 AM UTC 24
Peak memory 227452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487203929 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2487203929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_alert.3523024112
Short name T567
Test name
Test status
Simulation time 85598911 ps
CPU time 1.75 seconds
Started Sep 11 09:56:24 AM UTC 24
Finished Sep 11 09:56:27 AM UTC 24
Peak memory 228428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523024112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.3523024112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_alert_test.1623531656
Short name T570
Test name
Test status
Simulation time 50430113 ps
CPU time 1.36 seconds
Started Sep 11 09:56:27 AM UTC 24
Finished Sep 11 09:56:30 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623531656 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1623531656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_disable.3806288729
Short name T218
Test name
Test status
Simulation time 41463698 ps
CPU time 1.2 seconds
Started Sep 11 09:56:25 AM UTC 24
Finished Sep 11 09:56:27 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806288729 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3806288729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.2828927536
Short name T568
Test name
Test status
Simulation time 161795734 ps
CPU time 1.63 seconds
Started Sep 11 09:56:26 AM UTC 24
Finished Sep 11 09:56:29 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828927536 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.2828927536
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_err.450956107
Short name T226
Test name
Test status
Simulation time 27849418 ps
CPU time 1.39 seconds
Started Sep 11 09:56:24 AM UTC 24
Finished Sep 11 09:56:26 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450956107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.edn_err.450956107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_genbits.44325469
Short name T653
Test name
Test status
Simulation time 2266491186 ps
CPU time 84.63 seconds
Started Sep 11 09:56:21 AM UTC 24
Finished Sep 11 09:57:47 AM UTC 24
Peak memory 229488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44325469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.edn_genbits.44325469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_intr.2632325778
Short name T566
Test name
Test status
Simulation time 28185854 ps
CPU time 1.4 seconds
Started Sep 11 09:56:23 AM UTC 24
Finished Sep 11 09:56:25 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632325778 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.2632325778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_smoke.2420089033
Short name T564
Test name
Test status
Simulation time 48164915 ps
CPU time 1.35 seconds
Started Sep 11 09:56:21 AM UTC 24
Finished Sep 11 09:56:23 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420089033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.2420089033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/46.edn_stress_all.3440092533
Short name T565
Test name
Test status
Simulation time 563457409 ps
CPU time 2.32 seconds
Started Sep 11 09:56:21 AM UTC 24
Finished Sep 11 09:56:24 AM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440092533 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3440092533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_alert.357380112
Short name T573
Test name
Test status
Simulation time 24433198 ps
CPU time 1.77 seconds
Started Sep 11 09:56:33 AM UTC 24
Finished Sep 11 09:56:35 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357380112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.edn_alert.357380112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_alert_test.755574516
Short name T576
Test name
Test status
Simulation time 31096720 ps
CPU time 1.33 seconds
Started Sep 11 09:56:37 AM UTC 24
Finished Sep 11 09:56:39 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755574516 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.755574516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_disable.1187957671
Short name T575
Test name
Test status
Simulation time 37830570 ps
CPU time 1.18 seconds
Started Sep 11 09:56:36 AM UTC 24
Finished Sep 11 09:56:38 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187957671 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1187957671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.534821323
Short name T213
Test name
Test status
Simulation time 94642183 ps
CPU time 1.53 seconds
Started Sep 11 09:56:36 AM UTC 24
Finished Sep 11 09:56:38 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534821323 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.534821323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_err.642004153
Short name T574
Test name
Test status
Simulation time 18790654 ps
CPU time 1.4 seconds
Started Sep 11 09:56:34 AM UTC 24
Finished Sep 11 09:56:36 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642004153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.edn_err.642004153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_intr.3275307845
Short name T571
Test name
Test status
Simulation time 34169389 ps
CPU time 1.31 seconds
Started Sep 11 09:56:30 AM UTC 24
Finished Sep 11 09:56:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275307845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.3275307845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_smoke.1665405672
Short name T569
Test name
Test status
Simulation time 50030623 ps
CPU time 1.33 seconds
Started Sep 11 09:56:27 AM UTC 24
Finished Sep 11 09:56:29 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665405672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.1665405672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_stress_all.1389835212
Short name T572
Test name
Test status
Simulation time 548121659 ps
CPU time 4.05 seconds
Started Sep 11 09:56:29 AM UTC 24
Finished Sep 11 09:56:34 AM UTC 24
Peak memory 227668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389835212 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1389835212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.430119243
Short name T706
Test name
Test status
Simulation time 6185347308 ps
CPU time 95.96 seconds
Started Sep 11 09:56:30 AM UTC 24
Finished Sep 11 09:58:08 AM UTC 24
Peak memory 229848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=430119243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_
with_rand_reset.430119243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_alert.2738861294
Short name T581
Test name
Test status
Simulation time 74197703 ps
CPU time 1.53 seconds
Started Sep 11 09:56:43 AM UTC 24
Finished Sep 11 09:56:46 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738861294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.2738861294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_alert_test.73340201
Short name T537
Test name
Test status
Simulation time 34814982 ps
CPU time 1.51 seconds
Started Sep 11 09:56:49 AM UTC 24
Finished Sep 11 09:56:51 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73340201 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.73340201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_disable.54691864
Short name T582
Test name
Test status
Simulation time 75773893 ps
CPU time 1.2 seconds
Started Sep 11 09:56:46 AM UTC 24
Finished Sep 11 09:56:48 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54691864 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.54691864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_err.4101331080
Short name T162
Test name
Test status
Simulation time 26143840 ps
CPU time 1.61 seconds
Started Sep 11 09:56:45 AM UTC 24
Finished Sep 11 09:56:48 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101331080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.4101331080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_genbits.1606894929
Short name T579
Test name
Test status
Simulation time 114967591 ps
CPU time 4.39 seconds
Started Sep 11 09:56:39 AM UTC 24
Finished Sep 11 09:56:44 AM UTC 24
Peak memory 231508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606894929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1606894929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_intr.301254283
Short name T578
Test name
Test status
Simulation time 21381646 ps
CPU time 1.59 seconds
Started Sep 11 09:56:40 AM UTC 24
Finished Sep 11 09:56:43 AM UTC 24
Peak memory 236692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301254283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.301254283
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_smoke.3918496863
Short name T577
Test name
Test status
Simulation time 31737485 ps
CPU time 1.46 seconds
Started Sep 11 09:56:37 AM UTC 24
Finished Sep 11 09:56:39 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918496863 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.3918496863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/48.edn_stress_all.4194629603
Short name T580
Test name
Test status
Simulation time 1078771009 ps
CPU time 5.43 seconds
Started Sep 11 09:56:39 AM UTC 24
Finished Sep 11 09:56:45 AM UTC 24
Peak memory 231508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194629603 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4194629603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_alert.1014549316
Short name T153
Test name
Test status
Simulation time 23900306 ps
CPU time 1.69 seconds
Started Sep 11 09:56:52 AM UTC 24
Finished Sep 11 09:56:55 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014549316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.1014549316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_alert_test.3770675250
Short name T589
Test name
Test status
Simulation time 20998916 ps
CPU time 1.2 seconds
Started Sep 11 09:56:55 AM UTC 24
Finished Sep 11 09:56:57 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770675250 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3770675250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_disable.3781126337
Short name T588
Test name
Test status
Simulation time 34861009 ps
CPU time 1.18 seconds
Started Sep 11 09:56:53 AM UTC 24
Finished Sep 11 09:56:56 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781126337 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3781126337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.2771808869
Short name T222
Test name
Test status
Simulation time 105088461 ps
CPU time 1.64 seconds
Started Sep 11 09:56:53 AM UTC 24
Finished Sep 11 09:56:56 AM UTC 24
Peak memory 226244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771808869 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.2771808869
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_err.4263761506
Short name T176
Test name
Test status
Simulation time 30546863 ps
CPU time 1.23 seconds
Started Sep 11 09:56:52 AM UTC 24
Finished Sep 11 09:56:54 AM UTC 24
Peak memory 236952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263761506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.4263761506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_intr.4165961202
Short name T584
Test name
Test status
Simulation time 25080696 ps
CPU time 1.49 seconds
Started Sep 11 09:56:50 AM UTC 24
Finished Sep 11 09:56:53 AM UTC 24
Peak memory 237392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165961202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.4165961202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_smoke.3061172027
Short name T524
Test name
Test status
Simulation time 16112094 ps
CPU time 1.32 seconds
Started Sep 11 09:56:49 AM UTC 24
Finished Sep 11 09:56:51 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061172027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.3061172027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_stress_all.1773018106
Short name T586
Test name
Test status
Simulation time 85388547 ps
CPU time 2.8 seconds
Started Sep 11 09:56:50 AM UTC 24
Finished Sep 11 09:56:54 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773018106 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1773018106
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.1562996337
Short name T720
Test name
Test status
Simulation time 6081949174 ps
CPU time 81.84 seconds
Started Sep 11 09:56:50 AM UTC 24
Finished Sep 11 09:58:14 AM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1562996337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all
_with_rand_reset.1562996337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_alert.3135175894
Short name T128
Test name
Test status
Simulation time 49737458 ps
CPU time 1.52 seconds
Started Sep 11 09:51:30 AM UTC 24
Finished Sep 11 09:51:33 AM UTC 24
Peak memory 228420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135175894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.3135175894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_alert_test.2198528112
Short name T348
Test name
Test status
Simulation time 73668365 ps
CPU time 1.35 seconds
Started Sep 11 09:51:33 AM UTC 24
Finished Sep 11 09:51:36 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198528112 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2198528112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_disable.1553370480
Short name T44
Test name
Test status
Simulation time 23142033 ps
CPU time 1.32 seconds
Started Sep 11 09:51:32 AM UTC 24
Finished Sep 11 09:51:35 AM UTC 24
Peak memory 226292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553370480 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1553370480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.1521412244
Short name T24
Test name
Test status
Simulation time 98432192 ps
CPU time 1.61 seconds
Started Sep 11 09:51:32 AM UTC 24
Finished Sep 11 09:51:35 AM UTC 24
Peak memory 228252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521412244 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.1521412244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_err.3146782606
Short name T107
Test name
Test status
Simulation time 53678671 ps
CPU time 1.17 seconds
Started Sep 11 09:51:31 AM UTC 24
Finished Sep 11 09:51:34 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146782606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.3146782606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_genbits.3717862468
Short name T43
Test name
Test status
Simulation time 51223571 ps
CPU time 2.49 seconds
Started Sep 11 09:51:27 AM UTC 24
Finished Sep 11 09:51:30 AM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717862468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3717862468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_intr.2457324364
Short name T347
Test name
Test status
Simulation time 26612793 ps
CPU time 1.42 seconds
Started Sep 11 09:51:29 AM UTC 24
Finished Sep 11 09:51:31 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457324364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.2457324364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_regwen.1429218643
Short name T110
Test name
Test status
Simulation time 62693319 ps
CPU time 1.45 seconds
Started Sep 11 09:51:26 AM UTC 24
Finished Sep 11 09:51:28 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429218643 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.1429218643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/5.edn_smoke.3440241025
Short name T125
Test name
Test status
Simulation time 19906660 ps
CPU time 1.41 seconds
Started Sep 11 09:51:26 AM UTC 24
Finished Sep 11 09:51:28 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440241025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.3440241025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/50.edn_alert.426750105
Short name T591
Test name
Test status
Simulation time 26757781 ps
CPU time 1.7 seconds
Started Sep 11 09:56:56 AM UTC 24
Finished Sep 11 09:56:58 AM UTC 24
Peak memory 226072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426750105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 50.edn_alert.426750105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/50.edn_err.4127109982
Short name T590
Test name
Test status
Simulation time 26998822 ps
CPU time 1.27 seconds
Started Sep 11 09:56:56 AM UTC 24
Finished Sep 11 09:56:58 AM UTC 24
Peak memory 228104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127109982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.4127109982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/50.edn_genbits.2266550087
Short name T751
Test name
Test status
Simulation time 2297236912 ps
CPU time 85.79 seconds
Started Sep 11 09:56:55 AM UTC 24
Finished Sep 11 09:58:22 AM UTC 24
Peak memory 231632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266550087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2266550087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/51.edn_alert.2118040469
Short name T165
Test name
Test status
Simulation time 151437159 ps
CPU time 1.88 seconds
Started Sep 11 09:56:57 AM UTC 24
Finished Sep 11 09:57:00 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118040469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.2118040469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/51.edn_err.1863622199
Short name T185
Test name
Test status
Simulation time 24086625 ps
CPU time 1.36 seconds
Started Sep 11 09:56:57 AM UTC 24
Finished Sep 11 09:56:59 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863622199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.1863622199
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/51.edn_genbits.3793653817
Short name T592
Test name
Test status
Simulation time 31143285 ps
CPU time 1.74 seconds
Started Sep 11 09:56:56 AM UTC 24
Finished Sep 11 09:56:59 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793653817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3793653817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/52.edn_alert.390277829
Short name T132
Test name
Test status
Simulation time 27891447 ps
CPU time 1.97 seconds
Started Sep 11 09:56:59 AM UTC 24
Finished Sep 11 09:57:02 AM UTC 24
Peak memory 228420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390277829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 52.edn_alert.390277829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/52.edn_err.2478801307
Short name T214
Test name
Test status
Simulation time 47983387 ps
CPU time 1.23 seconds
Started Sep 11 09:56:59 AM UTC 24
Finished Sep 11 09:57:01 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478801307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.2478801307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/52.edn_genbits.3495950744
Short name T255
Test name
Test status
Simulation time 142503660 ps
CPU time 4.35 seconds
Started Sep 11 09:56:58 AM UTC 24
Finished Sep 11 09:57:03 AM UTC 24
Peak memory 231704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495950744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3495950744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/53.edn_alert.4041138538
Short name T157
Test name
Test status
Simulation time 97088313 ps
CPU time 1.71 seconds
Started Sep 11 09:57:00 AM UTC 24
Finished Sep 11 09:57:03 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041138538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.4041138538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/53.edn_genbits.1607773579
Short name T254
Test name
Test status
Simulation time 117314525 ps
CPU time 1.93 seconds
Started Sep 11 09:56:59 AM UTC 24
Finished Sep 11 09:57:02 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607773579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1607773579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/54.edn_alert.2164020161
Short name T257
Test name
Test status
Simulation time 46299753 ps
CPU time 1.68 seconds
Started Sep 11 09:57:02 AM UTC 24
Finished Sep 11 09:57:05 AM UTC 24
Peak memory 228432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164020161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 54.edn_alert.2164020161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/54.edn_err.435082736
Short name T258
Test name
Test status
Simulation time 32080310 ps
CPU time 1.55 seconds
Started Sep 11 09:57:04 AM UTC 24
Finished Sep 11 09:57:06 AM UTC 24
Peak memory 236908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435082736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 54.edn_err.435082736
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/54.edn_genbits.783785993
Short name T256
Test name
Test status
Simulation time 52537624 ps
CPU time 1.68 seconds
Started Sep 11 09:57:02 AM UTC 24
Finished Sep 11 09:57:05 AM UTC 24
Peak memory 226312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783785993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.edn_genbits.783785993
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/55.edn_alert.2770006465
Short name T593
Test name
Test status
Simulation time 37039754 ps
CPU time 1.78 seconds
Started Sep 11 09:57:04 AM UTC 24
Finished Sep 11 09:57:06 AM UTC 24
Peak memory 226280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770006465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.2770006465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/55.edn_err.4219931957
Short name T594
Test name
Test status
Simulation time 41281033 ps
CPU time 1.45 seconds
Started Sep 11 09:57:05 AM UTC 24
Finished Sep 11 09:57:07 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219931957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.4219931957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/55.edn_genbits.3914808279
Short name T333
Test name
Test status
Simulation time 25504830 ps
CPU time 1.88 seconds
Started Sep 11 09:57:04 AM UTC 24
Finished Sep 11 09:57:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914808279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3914808279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/56.edn_alert.4177880849
Short name T595
Test name
Test status
Simulation time 64748137 ps
CPU time 1.63 seconds
Started Sep 11 09:57:06 AM UTC 24
Finished Sep 11 09:57:08 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177880849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.4177880849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/56.edn_genbits.1412694911
Short name T596
Test name
Test status
Simulation time 270695472 ps
CPU time 4.18 seconds
Started Sep 11 09:57:06 AM UTC 24
Finished Sep 11 09:57:11 AM UTC 24
Peak memory 231564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412694911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1412694911
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/57.edn_alert.2229158595
Short name T597
Test name
Test status
Simulation time 29988401 ps
CPU time 1.82 seconds
Started Sep 11 09:57:07 AM UTC 24
Finished Sep 11 09:57:11 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229158595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.2229158595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/57.edn_err.1114080873
Short name T146
Test name
Test status
Simulation time 32694904 ps
CPU time 1.59 seconds
Started Sep 11 09:57:08 AM UTC 24
Finished Sep 11 09:57:11 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114080873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.1114080873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/58.edn_alert.3394801714
Short name T602
Test name
Test status
Simulation time 57483486 ps
CPU time 1.93 seconds
Started Sep 11 09:57:12 AM UTC 24
Finished Sep 11 09:57:15 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394801714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.3394801714
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/58.edn_err.2273379980
Short name T600
Test name
Test status
Simulation time 31957053 ps
CPU time 1.51 seconds
Started Sep 11 09:57:12 AM UTC 24
Finished Sep 11 09:57:15 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273379980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.2273379980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/58.edn_genbits.1744521647
Short name T323
Test name
Test status
Simulation time 43433117 ps
CPU time 2 seconds
Started Sep 11 09:57:10 AM UTC 24
Finished Sep 11 09:57:13 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744521647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1744521647
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/59.edn_alert.3513365430
Short name T201
Test name
Test status
Simulation time 24817223 ps
CPU time 1.45 seconds
Started Sep 11 09:57:12 AM UTC 24
Finished Sep 11 09:57:15 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513365430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.3513365430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/59.edn_err.1531221607
Short name T601
Test name
Test status
Simulation time 41353680 ps
CPU time 1.35 seconds
Started Sep 11 09:57:12 AM UTC 24
Finished Sep 11 09:57:15 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531221607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.1531221607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/59.edn_genbits.433167047
Short name T603
Test name
Test status
Simulation time 123332398 ps
CPU time 2.68 seconds
Started Sep 11 09:57:12 AM UTC 24
Finished Sep 11 09:57:16 AM UTC 24
Peak memory 231652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433167047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 59.edn_genbits.433167047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_alert.1726554094
Short name T129
Test name
Test status
Simulation time 26917694 ps
CPU time 1.69 seconds
Started Sep 11 09:51:37 AM UTC 24
Finished Sep 11 09:51:40 AM UTC 24
Peak memory 230468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726554094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.1726554094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_alert_test.3209640764
Short name T349
Test name
Test status
Simulation time 35798254 ps
CPU time 1.2 seconds
Started Sep 11 09:51:40 AM UTC 24
Finished Sep 11 09:51:42 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209640764 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3209640764
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_disable.975755674
Short name T87
Test name
Test status
Simulation time 37983094 ps
CPU time 1.32 seconds
Started Sep 11 09:51:39 AM UTC 24
Finished Sep 11 09:51:41 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975755674 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.975755674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.4022642916
Short name T94
Test name
Test status
Simulation time 104295338 ps
CPU time 1.43 seconds
Started Sep 11 09:51:39 AM UTC 24
Finished Sep 11 09:51:42 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022642916 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.4022642916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_err.867018487
Short name T9
Test name
Test status
Simulation time 31885961 ps
CPU time 1.41 seconds
Started Sep 11 09:51:38 AM UTC 24
Finished Sep 11 09:51:40 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867018487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.edn_err.867018487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_genbits.3622421045
Short name T138
Test name
Test status
Simulation time 42365926 ps
CPU time 2.37 seconds
Started Sep 11 09:51:35 AM UTC 24
Finished Sep 11 09:51:38 AM UTC 24
Peak memory 229644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622421045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3622421045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_intr.882765204
Short name T108
Test name
Test status
Simulation time 22331288 ps
CPU time 1.48 seconds
Started Sep 11 09:51:37 AM UTC 24
Finished Sep 11 09:51:39 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882765204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.882765204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_regwen.1757413951
Short name T314
Test name
Test status
Simulation time 110962680 ps
CPU time 1.37 seconds
Started Sep 11 09:51:35 AM UTC 24
Finished Sep 11 09:51:37 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757413951 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.1757413951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_smoke.2114053910
Short name T117
Test name
Test status
Simulation time 16396443 ps
CPU time 1.49 seconds
Started Sep 11 09:51:34 AM UTC 24
Finished Sep 11 09:51:36 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114053910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.2114053910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_stress_all.1191196739
Short name T118
Test name
Test status
Simulation time 195833978 ps
CPU time 2.08 seconds
Started Sep 11 09:51:36 AM UTC 24
Finished Sep 11 09:51:39 AM UTC 24
Peak memory 227404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191196739 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1191196739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.3002500396
Short name T38
Test name
Test status
Simulation time 5507554790 ps
CPU time 46.91 seconds
Started Sep 11 09:51:36 AM UTC 24
Finished Sep 11 09:52:24 AM UTC 24
Peak memory 229940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3002500396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_
with_rand_reset.3002500396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/60.edn_alert.2832887374
Short name T149
Test name
Test status
Simulation time 68603793 ps
CPU time 1.68 seconds
Started Sep 11 09:57:15 AM UTC 24
Finished Sep 11 09:57:18 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832887374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.2832887374
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/60.edn_err.2676077672
Short name T606
Test name
Test status
Simulation time 18620623 ps
CPU time 1.59 seconds
Started Sep 11 09:57:16 AM UTC 24
Finished Sep 11 09:57:18 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676077672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.2676077672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/60.edn_genbits.2717984230
Short name T604
Test name
Test status
Simulation time 50348886 ps
CPU time 2.71 seconds
Started Sep 11 09:57:14 AM UTC 24
Finished Sep 11 09:57:17 AM UTC 24
Peak memory 229448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717984230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2717984230
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/61.edn_alert.2441501624
Short name T605
Test name
Test status
Simulation time 66063918 ps
CPU time 1.53 seconds
Started Sep 11 09:57:16 AM UTC 24
Finished Sep 11 09:57:18 AM UTC 24
Peak memory 232512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441501624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.2441501624
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/61.edn_err.2891493795
Short name T607
Test name
Test status
Simulation time 30435507 ps
CPU time 1.74 seconds
Started Sep 11 09:57:16 AM UTC 24
Finished Sep 11 09:57:19 AM UTC 24
Peak memory 226304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891493795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.2891493795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/61.edn_genbits.1230872673
Short name T331
Test name
Test status
Simulation time 238777356 ps
CPU time 4.31 seconds
Started Sep 11 09:57:16 AM UTC 24
Finished Sep 11 09:57:21 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230872673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1230872673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/62.edn_alert.916548874
Short name T309
Test name
Test status
Simulation time 27850418 ps
CPU time 1.76 seconds
Started Sep 11 09:57:18 AM UTC 24
Finished Sep 11 09:57:22 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916548874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 62.edn_alert.916548874
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/62.edn_err.3186607784
Short name T610
Test name
Test status
Simulation time 73754387 ps
CPU time 1.53 seconds
Started Sep 11 09:57:19 AM UTC 24
Finished Sep 11 09:57:22 AM UTC 24
Peak memory 242232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186607784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.3186607784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/62.edn_genbits.867354136
Short name T608
Test name
Test status
Simulation time 80751588 ps
CPU time 1.57 seconds
Started Sep 11 09:57:17 AM UTC 24
Finished Sep 11 09:57:20 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867354136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 62.edn_genbits.867354136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/63.edn_alert.3931324809
Short name T611
Test name
Test status
Simulation time 40424001 ps
CPU time 1.6 seconds
Started Sep 11 09:57:19 AM UTC 24
Finished Sep 11 09:57:22 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931324809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.3931324809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/63.edn_err.4040336143
Short name T609
Test name
Test status
Simulation time 32125336 ps
CPU time 1.22 seconds
Started Sep 11 09:57:19 AM UTC 24
Finished Sep 11 09:57:22 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040336143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.4040336143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/64.edn_alert.1429351201
Short name T169
Test name
Test status
Simulation time 26724986 ps
CPU time 1.84 seconds
Started Sep 11 09:57:21 AM UTC 24
Finished Sep 11 09:57:24 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429351201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.1429351201
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/64.edn_err.1666907737
Short name T614
Test name
Test status
Simulation time 47373852 ps
CPU time 1.25 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:25 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666907737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.1666907737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/64.edn_genbits.1586975554
Short name T612
Test name
Test status
Simulation time 70679907 ps
CPU time 1.58 seconds
Started Sep 11 09:57:20 AM UTC 24
Finished Sep 11 09:57:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586975554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1586975554
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/65.edn_alert.1401177331
Short name T617
Test name
Test status
Simulation time 24283667 ps
CPU time 1.7 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:26 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401177331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.1401177331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/65.edn_err.3209255360
Short name T177
Test name
Test status
Simulation time 18583871 ps
CPU time 1.5 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:26 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209255360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.3209255360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/65.edn_genbits.659000568
Short name T615
Test name
Test status
Simulation time 43722790 ps
CPU time 1.61 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659000568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 65.edn_genbits.659000568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/66.edn_alert.1705513669
Short name T197
Test name
Test status
Simulation time 54206832 ps
CPU time 1.6 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:26 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705513669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.1705513669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/66.edn_err.3682117459
Short name T616
Test name
Test status
Simulation time 20020207 ps
CPU time 1.4 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:26 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682117459 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.3682117459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/66.edn_genbits.3397821779
Short name T618
Test name
Test status
Simulation time 59895276 ps
CPU time 2.52 seconds
Started Sep 11 09:57:23 AM UTC 24
Finished Sep 11 09:57:27 AM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397821779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3397821779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/67.edn_alert.539237145
Short name T619
Test name
Test status
Simulation time 29574064 ps
CPU time 1.9 seconds
Started Sep 11 09:57:25 AM UTC 24
Finished Sep 11 09:57:28 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539237145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 67.edn_alert.539237145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/67.edn_err.3042028683
Short name T220
Test name
Test status
Simulation time 32572233 ps
CPU time 1.42 seconds
Started Sep 11 09:57:25 AM UTC 24
Finished Sep 11 09:57:27 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042028683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.3042028683
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/67.edn_genbits.582800387
Short name T620
Test name
Test status
Simulation time 191056729 ps
CPU time 4.18 seconds
Started Sep 11 09:57:24 AM UTC 24
Finished Sep 11 09:57:29 AM UTC 24
Peak memory 231576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582800387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 67.edn_genbits.582800387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/68.edn_alert.3795803804
Short name T623
Test name
Test status
Simulation time 76730216 ps
CPU time 1.76 seconds
Started Sep 11 09:57:27 AM UTC 24
Finished Sep 11 09:57:30 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795803804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 68.edn_alert.3795803804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/68.edn_err.2605210161
Short name T171
Test name
Test status
Simulation time 84912745 ps
CPU time 1.3 seconds
Started Sep 11 09:57:27 AM UTC 24
Finished Sep 11 09:57:30 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605210161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 68.edn_err.2605210161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/68.edn_genbits.439063207
Short name T625
Test name
Test status
Simulation time 44080391 ps
CPU time 2.37 seconds
Started Sep 11 09:57:27 AM UTC 24
Finished Sep 11 09:57:31 AM UTC 24
Peak memory 229436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439063207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 68.edn_genbits.439063207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/69.edn_alert.2015637205
Short name T145
Test name
Test status
Simulation time 98109668 ps
CPU time 1.54 seconds
Started Sep 11 09:57:27 AM UTC 24
Finished Sep 11 09:57:30 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015637205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.2015637205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/69.edn_err.3097400886
Short name T621
Test name
Test status
Simulation time 31708536 ps
CPU time 1.36 seconds
Started Sep 11 09:57:27 AM UTC 24
Finished Sep 11 09:57:30 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097400886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.3097400886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/69.edn_genbits.1417849127
Short name T622
Test name
Test status
Simulation time 94839893 ps
CPU time 1.6 seconds
Started Sep 11 09:57:27 AM UTC 24
Finished Sep 11 09:57:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417849127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1417849127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_alert.1814884730
Short name T46
Test name
Test status
Simulation time 63788848 ps
CPU time 1.53 seconds
Started Sep 11 09:51:45 AM UTC 24
Finished Sep 11 09:51:47 AM UTC 24
Peak memory 230468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814884730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.1814884730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_alert_test.1793338557
Short name T350
Test name
Test status
Simulation time 59935626 ps
CPU time 1.31 seconds
Started Sep 11 09:51:49 AM UTC 24
Finished Sep 11 09:51:51 AM UTC 24
Peak memory 226884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793338557 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1793338557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_disable.1045807878
Short name T78
Test name
Test status
Simulation time 11466777 ps
CPU time 1.22 seconds
Started Sep 11 09:51:47 AM UTC 24
Finished Sep 11 09:51:49 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045807878 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1045807878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.4188756418
Short name T25
Test name
Test status
Simulation time 45594112 ps
CPU time 2.23 seconds
Started Sep 11 09:51:48 AM UTC 24
Finished Sep 11 09:51:51 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188756418 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.4188756418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_err.1528634544
Short name T7
Test name
Test status
Simulation time 25360913 ps
CPU time 1.38 seconds
Started Sep 11 09:51:46 AM UTC 24
Finished Sep 11 09:51:48 AM UTC 24
Peak memory 236952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528634544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.1528634544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_intr.1384317191
Short name T111
Test name
Test status
Simulation time 27021669 ps
CPU time 1.32 seconds
Started Sep 11 09:51:44 AM UTC 24
Finished Sep 11 09:51:46 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384317191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.1384317191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_regwen.4258252821
Short name T248
Test name
Test status
Simulation time 18269476 ps
CPU time 1.3 seconds
Started Sep 11 09:51:41 AM UTC 24
Finished Sep 11 09:51:44 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258252821 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.4258252821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_smoke.3823448303
Short name T115
Test name
Test status
Simulation time 57177152 ps
CPU time 1.25 seconds
Started Sep 11 09:51:40 AM UTC 24
Finished Sep 11 09:51:42 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823448303 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.3823448303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/7.edn_stress_all.2761948276
Short name T124
Test name
Test status
Simulation time 1068119538 ps
CPU time 6.14 seconds
Started Sep 11 09:51:42 AM UTC 24
Finished Sep 11 09:51:50 AM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761948276 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2761948276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/70.edn_alert.229643601
Short name T158
Test name
Test status
Simulation time 31773201 ps
CPU time 1.87 seconds
Started Sep 11 09:57:28 AM UTC 24
Finished Sep 11 09:57:31 AM UTC 24
Peak memory 230468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229643601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 70.edn_alert.229643601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/70.edn_err.1020217631
Short name T624
Test name
Test status
Simulation time 31430335 ps
CPU time 1.3 seconds
Started Sep 11 09:57:28 AM UTC 24
Finished Sep 11 09:57:30 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020217631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.1020217631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/70.edn_genbits.3153319868
Short name T626
Test name
Test status
Simulation time 45498543 ps
CPU time 2.26 seconds
Started Sep 11 09:57:28 AM UTC 24
Finished Sep 11 09:57:31 AM UTC 24
Peak memory 229440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153319868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3153319868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/71.edn_alert.1212318354
Short name T628
Test name
Test status
Simulation time 51255370 ps
CPU time 1.48 seconds
Started Sep 11 09:57:30 AM UTC 24
Finished Sep 11 09:57:33 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212318354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.1212318354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/71.edn_err.3169624226
Short name T141
Test name
Test status
Simulation time 25364217 ps
CPU time 1.44 seconds
Started Sep 11 09:57:30 AM UTC 24
Finished Sep 11 09:57:33 AM UTC 24
Peak memory 230400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169624226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.3169624226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/71.edn_genbits.117505171
Short name T627
Test name
Test status
Simulation time 63830200 ps
CPU time 1.43 seconds
Started Sep 11 09:57:29 AM UTC 24
Finished Sep 11 09:57:32 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117505171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.edn_genbits.117505171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/72.edn_alert.2234817496
Short name T291
Test name
Test status
Simulation time 79153818 ps
CPU time 1.61 seconds
Started Sep 11 09:57:30 AM UTC 24
Finished Sep 11 09:57:33 AM UTC 24
Peak memory 230480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234817496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.2234817496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/72.edn_err.1573863213
Short name T629
Test name
Test status
Simulation time 22015572 ps
CPU time 1.56 seconds
Started Sep 11 09:57:32 AM UTC 24
Finished Sep 11 09:57:34 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573863213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.1573863213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/72.edn_genbits.155316556
Short name T633
Test name
Test status
Simulation time 352749754 ps
CPU time 5.34 seconds
Started Sep 11 09:57:30 AM UTC 24
Finished Sep 11 09:57:37 AM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155316556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 72.edn_genbits.155316556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/73.edn_alert.1583316983
Short name T630
Test name
Test status
Simulation time 74637533 ps
CPU time 1.75 seconds
Started Sep 11 09:57:32 AM UTC 24
Finished Sep 11 09:57:35 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583316983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 73.edn_alert.1583316983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/73.edn_err.2512672040
Short name T191
Test name
Test status
Simulation time 22523453 ps
CPU time 1.22 seconds
Started Sep 11 09:57:32 AM UTC 24
Finished Sep 11 09:57:34 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512672040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.2512672040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/73.edn_genbits.1157827218
Short name T631
Test name
Test status
Simulation time 75624585 ps
CPU time 2.05 seconds
Started Sep 11 09:57:32 AM UTC 24
Finished Sep 11 09:57:35 AM UTC 24
Peak memory 231752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157827218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1157827218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/74.edn_alert.384150133
Short name T150
Test name
Test status
Simulation time 53517099 ps
CPU time 1.77 seconds
Started Sep 11 09:57:33 AM UTC 24
Finished Sep 11 09:57:36 AM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384150133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 74.edn_alert.384150133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/74.edn_err.1837937851
Short name T184
Test name
Test status
Simulation time 44853027 ps
CPU time 1.23 seconds
Started Sep 11 09:57:34 AM UTC 24
Finished Sep 11 09:57:36 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837937851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.1837937851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/74.edn_genbits.3457452259
Short name T324
Test name
Test status
Simulation time 71740189 ps
CPU time 2.08 seconds
Started Sep 11 09:57:33 AM UTC 24
Finished Sep 11 09:57:36 AM UTC 24
Peak memory 231816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457452259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3457452259
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/75.edn_alert.4242503961
Short name T632
Test name
Test status
Simulation time 44162404 ps
CPU time 1.71 seconds
Started Sep 11 09:57:34 AM UTC 24
Finished Sep 11 09:57:37 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242503961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 75.edn_alert.4242503961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/75.edn_err.3133854951
Short name T635
Test name
Test status
Simulation time 23581551 ps
CPU time 1.39 seconds
Started Sep 11 09:57:35 AM UTC 24
Finished Sep 11 09:57:38 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133854951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.3133854951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/75.edn_genbits.2341564541
Short name T634
Test name
Test status
Simulation time 72604331 ps
CPU time 2.13 seconds
Started Sep 11 09:57:34 AM UTC 24
Finished Sep 11 09:57:37 AM UTC 24
Peak memory 229448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341564541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2341564541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/76.edn_alert.3477245104
Short name T187
Test name
Test status
Simulation time 21947081 ps
CPU time 1.52 seconds
Started Sep 11 09:57:36 AM UTC 24
Finished Sep 11 09:57:39 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477245104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.3477245104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/76.edn_err.2211811056
Short name T147
Test name
Test status
Simulation time 24274097 ps
CPU time 1.8 seconds
Started Sep 11 09:57:36 AM UTC 24
Finished Sep 11 09:57:39 AM UTC 24
Peak memory 244028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211811056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.2211811056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/76.edn_genbits.2594571379
Short name T636
Test name
Test status
Simulation time 20216456 ps
CPU time 1.63 seconds
Started Sep 11 09:57:35 AM UTC 24
Finished Sep 11 09:57:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594571379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2594571379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/77.edn_alert.4276224600
Short name T133
Test name
Test status
Simulation time 41863362 ps
CPU time 1.69 seconds
Started Sep 11 09:57:36 AM UTC 24
Finished Sep 11 09:57:39 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276224600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.4276224600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/77.edn_err.4270998651
Short name T637
Test name
Test status
Simulation time 21518702 ps
CPU time 1.34 seconds
Started Sep 11 09:57:37 AM UTC 24
Finished Sep 11 09:57:40 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270998651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.4270998651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/77.edn_genbits.2592268748
Short name T340
Test name
Test status
Simulation time 74797342 ps
CPU time 1.61 seconds
Started Sep 11 09:57:36 AM UTC 24
Finished Sep 11 09:57:39 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592268748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2592268748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/78.edn_alert.532389548
Short name T638
Test name
Test status
Simulation time 50886242 ps
CPU time 1.75 seconds
Started Sep 11 09:57:38 AM UTC 24
Finished Sep 11 09:57:40 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532389548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 78.edn_alert.532389548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/78.edn_err.526438056
Short name T166
Test name
Test status
Simulation time 25172396 ps
CPU time 1.51 seconds
Started Sep 11 09:57:39 AM UTC 24
Finished Sep 11 09:57:41 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526438056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 78.edn_err.526438056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/78.edn_genbits.1967978429
Short name T641
Test name
Test status
Simulation time 232670751 ps
CPU time 3.04 seconds
Started Sep 11 09:57:37 AM UTC 24
Finished Sep 11 09:57:42 AM UTC 24
Peak memory 231536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967978429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1967978429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/79.edn_alert.3789263953
Short name T640
Test name
Test status
Simulation time 66417895 ps
CPU time 1.68 seconds
Started Sep 11 09:57:39 AM UTC 24
Finished Sep 11 09:57:41 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789263953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.3789263953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/79.edn_err.4224794573
Short name T643
Test name
Test status
Simulation time 91042665 ps
CPU time 1.95 seconds
Started Sep 11 09:57:40 AM UTC 24
Finished Sep 11 09:57:43 AM UTC 24
Peak memory 242768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224794573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.4224794573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/79.edn_genbits.775165777
Short name T639
Test name
Test status
Simulation time 60587674 ps
CPU time 1.54 seconds
Started Sep 11 09:57:39 AM UTC 24
Finished Sep 11 09:57:41 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775165777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 79.edn_genbits.775165777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_alert_test.2216544058
Short name T285
Test name
Test status
Simulation time 19788390 ps
CPU time 1.53 seconds
Started Sep 11 09:52:00 AM UTC 24
Finished Sep 11 09:52:03 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216544058 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2216544058
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.4053961896
Short name T113
Test name
Test status
Simulation time 40153684 ps
CPU time 1.37 seconds
Started Sep 11 09:51:59 AM UTC 24
Finished Sep 11 09:52:01 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053961896 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.4053961896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_err.3494550918
Short name T64
Test name
Test status
Simulation time 80108764 ps
CPU time 1.53 seconds
Started Sep 11 09:51:57 AM UTC 24
Finished Sep 11 09:51:59 AM UTC 24
Peak memory 242060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494550918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.3494550918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_intr.2208743778
Short name T63
Test name
Test status
Simulation time 40626242 ps
CPU time 1.61 seconds
Started Sep 11 09:51:53 AM UTC 24
Finished Sep 11 09:51:56 AM UTC 24
Peak memory 236692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208743778 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.2208743778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_regwen.1814034532
Short name T249
Test name
Test status
Simulation time 19793828 ps
CPU time 1.36 seconds
Started Sep 11 09:51:51 AM UTC 24
Finished Sep 11 09:51:53 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814034532 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.1814034532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_smoke.1570080315
Short name T351
Test name
Test status
Simulation time 14416289 ps
CPU time 1.1 seconds
Started Sep 11 09:51:50 AM UTC 24
Finished Sep 11 09:51:52 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570080315 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.1570080315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_stress_all.2228473885
Short name T109
Test name
Test status
Simulation time 994747565 ps
CPU time 6.48 seconds
Started Sep 11 09:51:52 AM UTC 24
Finished Sep 11 09:52:00 AM UTC 24
Peak memory 229716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228473885 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2228473885
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.378264823
Short name T235
Test name
Test status
Simulation time 8421355968 ps
CPU time 140.02 seconds
Started Sep 11 09:51:52 AM UTC 24
Finished Sep 11 09:54:15 AM UTC 24
Peak memory 229716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=378264823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_w
ith_rand_reset.378264823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/80.edn_alert.1958154849
Short name T598
Test name
Test status
Simulation time 55551569 ps
CPU time 1.52 seconds
Started Sep 11 09:57:40 AM UTC 24
Finished Sep 11 09:57:42 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958154849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.1958154849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/80.edn_err.1214230506
Short name T642
Test name
Test status
Simulation time 31986369 ps
CPU time 1.3 seconds
Started Sep 11 09:57:40 AM UTC 24
Finished Sep 11 09:57:42 AM UTC 24
Peak memory 228292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214230506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.1214230506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/80.edn_genbits.2162436078
Short name T585
Test name
Test status
Simulation time 58139213 ps
CPU time 1.38 seconds
Started Sep 11 09:57:40 AM UTC 24
Finished Sep 11 09:57:42 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162436078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2162436078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/81.edn_alert.3599318034
Short name T644
Test name
Test status
Simulation time 46917849 ps
CPU time 1.54 seconds
Started Sep 11 09:57:41 AM UTC 24
Finished Sep 11 09:57:43 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599318034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 81.edn_alert.3599318034
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/81.edn_err.2165175268
Short name T646
Test name
Test status
Simulation time 22069079 ps
CPU time 1.2 seconds
Started Sep 11 09:57:42 AM UTC 24
Finished Sep 11 09:57:44 AM UTC 24
Peak memory 237152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165175268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.2165175268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/81.edn_genbits.3378378979
Short name T645
Test name
Test status
Simulation time 50271588 ps
CPU time 1.58 seconds
Started Sep 11 09:57:41 AM UTC 24
Finished Sep 11 09:57:44 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378378979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3378378979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/82.edn_alert.1432447349
Short name T188
Test name
Test status
Simulation time 28979398 ps
CPU time 1.69 seconds
Started Sep 11 09:57:42 AM UTC 24
Finished Sep 11 09:57:45 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432447349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.1432447349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/82.edn_err.1415699516
Short name T647
Test name
Test status
Simulation time 33033114 ps
CPU time 1.08 seconds
Started Sep 11 09:57:42 AM UTC 24
Finished Sep 11 09:57:44 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415699516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.1415699516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/82.edn_genbits.2893461548
Short name T648
Test name
Test status
Simulation time 71750923 ps
CPU time 2.04 seconds
Started Sep 11 09:57:42 AM UTC 24
Finished Sep 11 09:57:45 AM UTC 24
Peak memory 231916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893461548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2893461548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/83.edn_alert.568294770
Short name T650
Test name
Test status
Simulation time 84129641 ps
CPU time 1.62 seconds
Started Sep 11 09:57:43 AM UTC 24
Finished Sep 11 09:57:46 AM UTC 24
Peak memory 228400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568294770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 83.edn_alert.568294770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/83.edn_err.4082403739
Short name T649
Test name
Test status
Simulation time 29160071 ps
CPU time 1.13 seconds
Started Sep 11 09:57:44 AM UTC 24
Finished Sep 11 09:57:46 AM UTC 24
Peak memory 228280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082403739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.4082403739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/83.edn_genbits.1613727318
Short name T655
Test name
Test status
Simulation time 81695687 ps
CPU time 3.99 seconds
Started Sep 11 09:57:43 AM UTC 24
Finished Sep 11 09:57:48 AM UTC 24
Peak memory 229432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613727318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1613727318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/84.edn_alert.2586932239
Short name T654
Test name
Test status
Simulation time 330704881 ps
CPU time 1.77 seconds
Started Sep 11 09:57:45 AM UTC 24
Finished Sep 11 09:57:47 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586932239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.2586932239
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/84.edn_err.2231556336
Short name T652
Test name
Test status
Simulation time 18412932 ps
CPU time 1.49 seconds
Started Sep 11 09:57:45 AM UTC 24
Finished Sep 11 09:57:47 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231556336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.2231556336
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/84.edn_genbits.3876900698
Short name T651
Test name
Test status
Simulation time 49938546 ps
CPU time 2.51 seconds
Started Sep 11 09:57:44 AM UTC 24
Finished Sep 11 09:57:47 AM UTC 24
Peak memory 229460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876900698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3876900698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/85.edn_alert.2579580862
Short name T656
Test name
Test status
Simulation time 77111164 ps
CPU time 1.77 seconds
Started Sep 11 09:57:46 AM UTC 24
Finished Sep 11 09:57:49 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579580862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.2579580862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/85.edn_err.3736525812
Short name T199
Test name
Test status
Simulation time 36266821 ps
CPU time 1.13 seconds
Started Sep 11 09:57:46 AM UTC 24
Finished Sep 11 09:57:48 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736525812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.3736525812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/85.edn_genbits.4156650070
Short name T658
Test name
Test status
Simulation time 55555082 ps
CPU time 2.16 seconds
Started Sep 11 09:57:46 AM UTC 24
Finished Sep 11 09:57:49 AM UTC 24
Peak memory 228768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156650070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4156650070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/86.edn_alert.1288939616
Short name T660
Test name
Test status
Simulation time 78491166 ps
CPU time 1.51 seconds
Started Sep 11 09:57:47 AM UTC 24
Finished Sep 11 09:57:50 AM UTC 24
Peak memory 230480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288939616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.1288939616
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/86.edn_err.176292399
Short name T659
Test name
Test status
Simulation time 46678629 ps
CPU time 1.06 seconds
Started Sep 11 09:57:47 AM UTC 24
Finished Sep 11 09:57:49 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176292399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 86.edn_err.176292399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/86.edn_genbits.1852499918
Short name T657
Test name
Test status
Simulation time 50610138 ps
CPU time 1.74 seconds
Started Sep 11 09:57:46 AM UTC 24
Finished Sep 11 09:57:49 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852499918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1852499918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/87.edn_alert.1518332088
Short name T661
Test name
Test status
Simulation time 39623927 ps
CPU time 1.38 seconds
Started Sep 11 09:57:48 AM UTC 24
Finished Sep 11 09:57:51 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518332088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.1518332088
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/87.edn_err.3460607986
Short name T142
Test name
Test status
Simulation time 35471006 ps
CPU time 1.69 seconds
Started Sep 11 09:57:48 AM UTC 24
Finished Sep 11 09:57:51 AM UTC 24
Peak memory 244268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460607986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 87.edn_err.3460607986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/87.edn_genbits.3852815779
Short name T663
Test name
Test status
Simulation time 34493610 ps
CPU time 1.75 seconds
Started Sep 11 09:57:48 AM UTC 24
Finished Sep 11 09:57:51 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852815779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3852815779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/88.edn_alert.3523912020
Short name T665
Test name
Test status
Simulation time 68258376 ps
CPU time 1.49 seconds
Started Sep 11 09:57:49 AM UTC 24
Finished Sep 11 09:57:52 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523912020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.3523912020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/88.edn_err.2887498095
Short name T664
Test name
Test status
Simulation time 42743113 ps
CPU time 1.35 seconds
Started Sep 11 09:57:49 AM UTC 24
Finished Sep 11 09:57:52 AM UTC 24
Peak memory 242232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887498095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.2887498095
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/88.edn_genbits.901330862
Short name T662
Test name
Test status
Simulation time 65589095 ps
CPU time 1.34 seconds
Started Sep 11 09:57:48 AM UTC 24
Finished Sep 11 09:57:51 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901330862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 88.edn_genbits.901330862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/89.edn_alert.1211161956
Short name T667
Test name
Test status
Simulation time 77272035 ps
CPU time 1.66 seconds
Started Sep 11 09:57:49 AM UTC 24
Finished Sep 11 09:57:52 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211161956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.1211161956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/89.edn_err.3389389350
Short name T152
Test name
Test status
Simulation time 25441296 ps
CPU time 1.93 seconds
Started Sep 11 09:57:51 AM UTC 24
Finished Sep 11 09:57:54 AM UTC 24
Peak memory 246616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389389350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 89.edn_err.3389389350
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/89.edn_genbits.2654599055
Short name T666
Test name
Test status
Simulation time 64917435 ps
CPU time 1.57 seconds
Started Sep 11 09:57:49 AM UTC 24
Finished Sep 11 09:57:52 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654599055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2654599055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_alert.2679604179
Short name T134
Test name
Test status
Simulation time 184644893 ps
CPU time 1.39 seconds
Started Sep 11 09:52:05 AM UTC 24
Finished Sep 11 09:52:07 AM UTC 24
Peak memory 228420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679604179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.2679604179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_alert_test.3171025096
Short name T241
Test name
Test status
Simulation time 15553728 ps
CPU time 1.41 seconds
Started Sep 11 09:52:08 AM UTC 24
Finished Sep 11 09:52:10 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171025096 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3171025096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_disable.1794450501
Short name T79
Test name
Test status
Simulation time 27710742 ps
CPU time 1.14 seconds
Started Sep 11 09:52:08 AM UTC 24
Finished Sep 11 09:52:10 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794450501 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1794450501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.845218831
Short name T27
Test name
Test status
Simulation time 37489319 ps
CPU time 1.38 seconds
Started Sep 11 09:52:08 AM UTC 24
Finished Sep 11 09:52:10 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845218831 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.845218831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_err.1173038382
Short name T240
Test name
Test status
Simulation time 20358087 ps
CPU time 1.51 seconds
Started Sep 11 09:52:08 AM UTC 24
Finished Sep 11 09:52:10 AM UTC 24
Peak memory 226304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173038382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.1173038382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_genbits.1752696962
Short name T54
Test name
Test status
Simulation time 84069576 ps
CPU time 1.74 seconds
Started Sep 11 09:52:03 AM UTC 24
Finished Sep 11 09:52:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752696962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1752696962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_intr.3841049559
Short name T238
Test name
Test status
Simulation time 25665306 ps
CPU time 1.22 seconds
Started Sep 11 09:52:05 AM UTC 24
Finished Sep 11 09:52:07 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841049559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.3841049559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_regwen.3788372797
Short name T287
Test name
Test status
Simulation time 25446286 ps
CPU time 1.48 seconds
Started Sep 11 09:52:01 AM UTC 24
Finished Sep 11 09:52:04 AM UTC 24
Peak memory 216012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788372797 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.3788372797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_smoke.2228086912
Short name T286
Test name
Test status
Simulation time 22954161 ps
CPU time 1.3 seconds
Started Sep 11 09:52:01 AM UTC 24
Finished Sep 11 09:52:04 AM UTC 24
Peak memory 226252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228086912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.2228086912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/9.edn_stress_all.3887882313
Short name T209
Test name
Test status
Simulation time 157529597 ps
CPU time 1.83 seconds
Started Sep 11 09:52:03 AM UTC 24
Finished Sep 11 09:52:06 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887882313 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3887882313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/90.edn_alert.2145497693
Short name T668
Test name
Test status
Simulation time 61565348 ps
CPU time 1.46 seconds
Started Sep 11 09:57:51 AM UTC 24
Finished Sep 11 09:57:54 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145497693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.2145497693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/90.edn_err.2826452328
Short name T671
Test name
Test status
Simulation time 19814415 ps
CPU time 1.79 seconds
Started Sep 11 09:57:52 AM UTC 24
Finished Sep 11 09:57:55 AM UTC 24
Peak memory 237332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826452328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 90.edn_err.2826452328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/90.edn_genbits.599068890
Short name T672
Test name
Test status
Simulation time 196121855 ps
CPU time 2.64 seconds
Started Sep 11 09:57:51 AM UTC 24
Finished Sep 11 09:57:55 AM UTC 24
Peak memory 231500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599068890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 90.edn_genbits.599068890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/91.edn_alert.848214888
Short name T669
Test name
Test status
Simulation time 23954495 ps
CPU time 1.37 seconds
Started Sep 11 09:57:52 AM UTC 24
Finished Sep 11 09:57:54 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848214888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 91.edn_alert.848214888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/91.edn_err.247050667
Short name T675
Test name
Test status
Simulation time 29949261 ps
CPU time 1.68 seconds
Started Sep 11 09:57:53 AM UTC 24
Finished Sep 11 09:57:56 AM UTC 24
Peak memory 230372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247050667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 91.edn_err.247050667
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/91.edn_genbits.1476052469
Short name T670
Test name
Test status
Simulation time 22777145 ps
CPU time 1.66 seconds
Started Sep 11 09:57:52 AM UTC 24
Finished Sep 11 09:57:54 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476052469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1476052469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/92.edn_alert.363840780
Short name T674
Test name
Test status
Simulation time 78456243 ps
CPU time 1.58 seconds
Started Sep 11 09:57:53 AM UTC 24
Finished Sep 11 09:57:56 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363840780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 92.edn_alert.363840780
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/92.edn_err.192995134
Short name T673
Test name
Test status
Simulation time 32974623 ps
CPU time 1.32 seconds
Started Sep 11 09:57:53 AM UTC 24
Finished Sep 11 09:57:56 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192995134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 92.edn_err.192995134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/92.edn_genbits.3138601346
Short name T676
Test name
Test status
Simulation time 55204040 ps
CPU time 1.7 seconds
Started Sep 11 09:57:53 AM UTC 24
Finished Sep 11 09:57:56 AM UTC 24
Peak memory 228324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138601346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3138601346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/93.edn_alert.1021464880
Short name T678
Test name
Test status
Simulation time 183447089 ps
CPU time 1.62 seconds
Started Sep 11 09:57:54 AM UTC 24
Finished Sep 11 09:57:57 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021464880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.1021464880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/93.edn_err.1172052556
Short name T679
Test name
Test status
Simulation time 88000315 ps
CPU time 1.2 seconds
Started Sep 11 09:57:55 AM UTC 24
Finished Sep 11 09:57:57 AM UTC 24
Peak memory 228352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172052556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.1172052556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/93.edn_genbits.4127283435
Short name T677
Test name
Test status
Simulation time 82218017 ps
CPU time 1.69 seconds
Started Sep 11 09:57:53 AM UTC 24
Finished Sep 11 09:57:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127283435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4127283435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/94.edn_alert.3354067614
Short name T192
Test name
Test status
Simulation time 43142768 ps
CPU time 1.64 seconds
Started Sep 11 09:57:55 AM UTC 24
Finished Sep 11 09:57:58 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354067614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.3354067614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/94.edn_err.2137742221
Short name T225
Test name
Test status
Simulation time 23544098 ps
CPU time 1.54 seconds
Started Sep 11 09:57:55 AM UTC 24
Finished Sep 11 09:57:58 AM UTC 24
Peak memory 236952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137742221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.2137742221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/94.edn_genbits.59052735
Short name T680
Test name
Test status
Simulation time 38708937 ps
CPU time 1.28 seconds
Started Sep 11 09:57:55 AM UTC 24
Finished Sep 11 09:57:58 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59052735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 94.edn_genbits.59052735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/95.edn_alert.1193001913
Short name T682
Test name
Test status
Simulation time 41638568 ps
CPU time 1.43 seconds
Started Sep 11 09:57:57 AM UTC 24
Finished Sep 11 09:57:59 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193001913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.1193001913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/95.edn_err.786672906
Short name T683
Test name
Test status
Simulation time 19211443 ps
CPU time 1.68 seconds
Started Sep 11 09:57:57 AM UTC 24
Finished Sep 11 09:57:59 AM UTC 24
Peak memory 236956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786672906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 95.edn_err.786672906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/95.edn_genbits.2305076623
Short name T681
Test name
Test status
Simulation time 75502701 ps
CPU time 1.43 seconds
Started Sep 11 09:57:55 AM UTC 24
Finished Sep 11 09:57:58 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305076623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2305076623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/96.edn_alert.1531053488
Short name T684
Test name
Test status
Simulation time 38859735 ps
CPU time 1.73 seconds
Started Sep 11 09:57:57 AM UTC 24
Finished Sep 11 09:57:59 AM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531053488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.1531053488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/96.edn_err.974738859
Short name T224
Test name
Test status
Simulation time 45774096 ps
CPU time 1.1 seconds
Started Sep 11 09:57:57 AM UTC 24
Finished Sep 11 09:57:59 AM UTC 24
Peak memory 228356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974738859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 96.edn_err.974738859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/96.edn_genbits.2877602986
Short name T685
Test name
Test status
Simulation time 196725831 ps
CPU time 1.97 seconds
Started Sep 11 09:57:57 AM UTC 24
Finished Sep 11 09:58:00 AM UTC 24
Peak memory 230408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877602986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2877602986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/97.edn_alert.3491516352
Short name T687
Test name
Test status
Simulation time 236823313 ps
CPU time 1.66 seconds
Started Sep 11 09:57:58 AM UTC 24
Finished Sep 11 09:58:00 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491516352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.3491516352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/97.edn_err.2274521226
Short name T148
Test name
Test status
Simulation time 24151035 ps
CPU time 1.5 seconds
Started Sep 11 09:57:59 AM UTC 24
Finished Sep 11 09:58:02 AM UTC 24
Peak memory 244268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274521226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 97.edn_err.2274521226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/97.edn_genbits.3200509173
Short name T686
Test name
Test status
Simulation time 100219153 ps
CPU time 1.18 seconds
Started Sep 11 09:57:58 AM UTC 24
Finished Sep 11 09:58:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200509173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3200509173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/98.edn_alert.477798906
Short name T688
Test name
Test status
Simulation time 66328421 ps
CPU time 1.76 seconds
Started Sep 11 09:57:59 AM UTC 24
Finished Sep 11 09:58:02 AM UTC 24
Peak memory 228416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477798906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 98.edn_alert.477798906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/98.edn_err.1390373010
Short name T139
Test name
Test status
Simulation time 32321314 ps
CPU time 1.46 seconds
Started Sep 11 09:57:59 AM UTC 24
Finished Sep 11 09:58:02 AM UTC 24
Peak memory 243788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390373010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.1390373010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/98.edn_genbits.3307819854
Short name T690
Test name
Test status
Simulation time 103728173 ps
CPU time 2.22 seconds
Started Sep 11 09:57:59 AM UTC 24
Finished Sep 11 09:58:03 AM UTC 24
Peak memory 231576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307819854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3307819854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/99.edn_alert.3355132426
Short name T693
Test name
Test status
Simulation time 122421283 ps
CPU time 1.79 seconds
Started Sep 11 09:58:00 AM UTC 24
Finished Sep 11 09:58:03 AM UTC 24
Peak memory 226368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355132426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 99.edn_alert.3355132426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/99.edn_err.3846261809
Short name T689
Test name
Test status
Simulation time 76137340 ps
CPU time 1.18 seconds
Started Sep 11 09:58:00 AM UTC 24
Finished Sep 11 09:58:02 AM UTC 24
Peak memory 230404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846261809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.3846261809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/default/99.edn_genbits.927636355
Short name T691
Test name
Test status
Simulation time 25584284 ps
CPU time 1.59 seconds
Started Sep 11 09:58:00 AM UTC 24
Finished Sep 11 09:58:03 AM UTC 24
Peak memory 228360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927636355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 99.edn_genbits.927636355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/99.edn_genbits/latest
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