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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.64 98.23 93.97 97.07 91.28 96.33 99.77 92.80


Total test records in report: 1116
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T1008 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.730325949 Sep 18 12:50:18 PM UTC 24 Sep 18 12:50:24 PM UTC 24 87033365 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.3827673184 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:26 PM UTC 24 658489023 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.1018958804 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 23762148 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.248021070 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 27717490 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2197246355 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 108983414 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.2860295721 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 70174667 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.252553038 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 24284266 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2073970814 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 43937668 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1971347573 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:28 PM UTC 24 65164180 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1938249964 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:29 PM UTC 24 50295151 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3222440016 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:29 PM UTC 24 28778007 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.3252658799 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:29 PM UTC 24 179815369 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4104487853 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:29 PM UTC 24 136316732 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.3281138016 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:29 PM UTC 24 49575375 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2845606268 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:29 PM UTC 24 111939677 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.4099169639 Sep 18 12:50:25 PM UTC 24 Sep 18 12:50:29 PM UTC 24 13649359 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2682575226 Sep 18 12:50:16 PM UTC 24 Sep 18 12:50:30 PM UTC 24 208505259 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3934477975 Sep 18 12:50:25 PM UTC 24 Sep 18 12:50:30 PM UTC 24 25933651 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3296279163 Sep 18 12:50:25 PM UTC 24 Sep 18 12:50:30 PM UTC 24 34412410 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3339000228 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:30 PM UTC 24 13148979 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3188147869 Sep 18 12:50:25 PM UTC 24 Sep 18 12:50:30 PM UTC 24 120653754 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.566339592 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:30 PM UTC 24 23346563 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.240971620 Sep 18 12:50:27 PM UTC 24 Sep 18 12:50:30 PM UTC 24 113249287 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.771926480 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:31 PM UTC 24 110947723 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1833390117 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:31 PM UTC 24 19079231 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1718956841 Sep 18 12:50:25 PM UTC 24 Sep 18 12:50:31 PM UTC 24 84474608 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.714941689 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:31 PM UTC 24 134454306 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.2380102541 Sep 18 12:50:25 PM UTC 24 Sep 18 12:50:31 PM UTC 24 90600333 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.957815600 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:31 PM UTC 24 782881999 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.2720610742 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:32 PM UTC 24 261741953 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.732292339 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:33 PM UTC 24 153765390 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.4270714729 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:33 PM UTC 24 17326874 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1902135984 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:33 PM UTC 24 18053091 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.2437304044 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:33 PM UTC 24 11164286 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.911919383 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:33 PM UTC 24 120356268 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1650256849 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:33 PM UTC 24 50114469 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.2006298494 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:33 PM UTC 24 14934897 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.1641362637 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:34 PM UTC 24 24126609 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2446860458 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:34 PM UTC 24 56360003 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1140614990 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:34 PM UTC 24 20358683 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1242462505 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:34 PM UTC 24 34016451 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1766665507 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:34 PM UTC 24 44048822 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.23527286 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:34 PM UTC 24 30018123 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.561595941 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:34 PM UTC 24 50322843 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.855235114 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:35 PM UTC 24 117313949 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.2958820011 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:35 PM UTC 24 577613587 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3151397637 Sep 18 12:50:20 PM UTC 24 Sep 18 12:50:35 PM UTC 24 335959026 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2068843958 Sep 18 12:50:31 PM UTC 24 Sep 18 12:50:36 PM UTC 24 163054318 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.177593761 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:38 PM UTC 24 20701475 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.3630923574 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:38 PM UTC 24 13985440 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4274819125 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:38 PM UTC 24 88734033 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3349581973 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:39 PM UTC 24 41994627 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.4198370165 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:39 PM UTC 24 21568660 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3290876218 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:39 PM UTC 24 44823615 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.69762485 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:39 PM UTC 24 70509324 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.2869756095 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:39 PM UTC 24 55575792 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.442267799 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 18119458 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.4154487529 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:39 PM UTC 24 81690481 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3319160330 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:39 PM UTC 24 20597805 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3669431808 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 36494439 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.380129120 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 41195991 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.3373725570 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 25226626 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4015183319 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 93669041 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.4210862183 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 47689518 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2512722215 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 65828871 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.4134613206 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:39 PM UTC 24 44841846 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.4253371389 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:40 PM UTC 24 110730597 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2251535404 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:40 PM UTC 24 58751145 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.325141294 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:40 PM UTC 24 48971067 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3162489868 Sep 18 12:50:37 PM UTC 24 Sep 18 12:50:40 PM UTC 24 154522513 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.180155405 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:40 PM UTC 24 466690362 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.402046701 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:40 PM UTC 24 416262201 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1965122759 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:40 PM UTC 24 19524847 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.465384220 Sep 18 12:50:34 PM UTC 24 Sep 18 12:50:41 PM UTC 24 45852298 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1113194412 Sep 18 12:50:21 PM UTC 24 Sep 18 12:50:41 PM UTC 24 69738632 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3946153468 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:41 PM UTC 24 28325085 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2607485217 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:41 PM UTC 24 49826763 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.3972449169 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:41 PM UTC 24 42013969 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.2316835661 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:41 PM UTC 24 15193190 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.356455909 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:41 PM UTC 24 12408034 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.1779302144 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:41 PM UTC 24 19843063 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1194577904 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:41 PM UTC 24 52177213 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1437170991 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:41 PM UTC 24 22835162 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.23474828 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:42 PM UTC 24 97762337 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2971662744 Sep 18 12:50:23 PM UTC 24 Sep 18 12:50:42 PM UTC 24 71062255 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1803562517 Sep 18 12:50:29 PM UTC 24 Sep 18 12:50:42 PM UTC 24 897206560 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.1665109063 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:42 PM UTC 24 30350813 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3978371940 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:42 PM UTC 24 63417021 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4184462421 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:42 PM UTC 24 64807972 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.176754241 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:42 PM UTC 24 41606847 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.301816930 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:42 PM UTC 24 17151855 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1408225210 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 100114811 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3699703315 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 40935896 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.4174690338 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 27467305 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3571996194 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 26500976 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.4137874093 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 12433714 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.4091618892 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 14152035 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.2380985567 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 55022463 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2066512656 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 173958181 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3731189292 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 32085501 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.321335932 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 20482704 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.3610621033 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 51392080 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.195899724 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 12676848 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3928899603 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 13888463 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.2664279480 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 20559083 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.920760822 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 18727593 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1256382684 Sep 18 12:50:41 PM UTC 24 Sep 18 12:50:43 PM UTC 24 12331458 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2184344768 Sep 18 12:50:42 PM UTC 24 Sep 18 12:50:45 PM UTC 24 74400009 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.945512816 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:45 PM UTC 24 49132592 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.2821240923 Sep 18 12:50:32 PM UTC 24 Sep 18 12:50:45 PM UTC 24 942670950 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.4031246550 Sep 18 12:50:42 PM UTC 24 Sep 18 12:50:45 PM UTC 24 42408859 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1924693452 Sep 18 12:50:42 PM UTC 24 Sep 18 12:50:45 PM UTC 24 14714153 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.402789745 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:45 PM UTC 24 24674230 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.1377836161 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:45 PM UTC 24 17352358 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.1801545130 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:45 PM UTC 24 19604908 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.201809447 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:45 PM UTC 24 30535889 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_alert.3083228558
Short name T20
Test name
Test status
Simulation time 65732646 ps
CPU time 1.46 seconds
Started Sep 18 09:39:13 AM UTC 24
Finished Sep 18 09:39:15 AM UTC 24
Peak memory 230880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083228558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.3083228558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_genbits.740296484
Short name T14
Test name
Test status
Simulation time 83850515 ps
CPU time 2.29 seconds
Started Sep 18 09:39:25 AM UTC 24
Finished Sep 18 09:39:28 AM UTC 24
Peak memory 232088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740296484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_genbits.740296484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_sec_cm.1239429015
Short name T16
Test name
Test status
Simulation time 7716695589 ps
CPU time 11.77 seconds
Started Sep 18 09:39:22 AM UTC 24
Finished Sep 18 09:39:35 AM UTC 24
Peak memory 260812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239429015 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1239429015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_genbits.1422184138
Short name T36
Test name
Test status
Simulation time 32832708 ps
CPU time 1.78 seconds
Started Sep 18 09:39:18 AM UTC 24
Finished Sep 18 09:39:21 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422184138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1422184138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_stress_all.2471765534
Short name T52
Test name
Test status
Simulation time 832644652 ps
CPU time 6.04 seconds
Started Sep 18 09:39:27 AM UTC 24
Finished Sep 18 09:39:34 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471765534 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2471765534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.3093756913
Short name T33
Test name
Test status
Simulation time 5433192677 ps
CPU time 34.84 seconds
Started Sep 18 09:39:38 AM UTC 24
Finished Sep 18 09:40:14 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3093756913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.3093756913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_alert.2402912112
Short name T93
Test name
Test status
Simulation time 79411097 ps
CPU time 1.63 seconds
Started Sep 18 09:39:55 AM UTC 24
Finished Sep 18 09:39:58 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402912112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.2402912112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_sec_cm.4189463378
Short name T55
Test name
Test status
Simulation time 253349052 ps
CPU time 6.35 seconds
Started Sep 18 09:39:51 AM UTC 24
Finished Sep 18 09:39:59 AM UTC 24
Peak memory 258672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189463378 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4189463378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_stress_all.2459071102
Short name T120
Test name
Test status
Simulation time 298290864 ps
CPU time 5.53 seconds
Started Sep 18 09:40:02 AM UTC 24
Finished Sep 18 09:40:08 AM UTC 24
Peak memory 230160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459071102 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2459071102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.3197112080
Short name T9
Test name
Test status
Simulation time 37499280 ps
CPU time 2 seconds
Started Sep 18 09:39:17 AM UTC 24
Finished Sep 18 09:39:20 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197112080 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.3197112080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_alert.3513727387
Short name T130
Test name
Test status
Simulation time 53615846 ps
CPU time 1.8 seconds
Started Sep 18 09:41:47 AM UTC 24
Finished Sep 18 09:41:50 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513727387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_alert.3513727387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_alert.4255234735
Short name T67
Test name
Test status
Simulation time 79999030 ps
CPU time 1.72 seconds
Started Sep 18 09:40:16 AM UTC 24
Finished Sep 18 09:40:18 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255234735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.4255234735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_regwen.2198002074
Short name T2
Test name
Test status
Simulation time 46645564 ps
CPU time 1.3 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:39:15 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198002074 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.2198002074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_alert.2553233879
Short name T82
Test name
Test status
Simulation time 53189546 ps
CPU time 1.56 seconds
Started Sep 18 09:41:11 AM UTC 24
Finished Sep 18 09:41:14 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553233879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_alert.2553233879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_disable.2593546504
Short name T38
Test name
Test status
Simulation time 26063126 ps
CPU time 1.1 seconds
Started Sep 18 09:39:29 AM UTC 24
Finished Sep 18 09:39:34 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593546504 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2593546504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.1690072517
Short name T127
Test name
Test status
Simulation time 4685048069 ps
CPU time 34.12 seconds
Started Sep 18 09:40:09 AM UTC 24
Finished Sep 18 09:40:44 AM UTC 24
Peak memory 230228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1690072517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_
with_rand_reset.1690072517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.4136457059
Short name T144
Test name
Test status
Simulation time 84830168 ps
CPU time 1.69 seconds
Started Sep 18 09:41:44 AM UTC 24
Finished Sep 18 09:41:47 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136457059 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.4136457059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.65488623
Short name T290
Test name
Test status
Simulation time 256541287 ps
CPU time 1.85 seconds
Started Sep 18 12:50:06 PM UTC 24
Finished Sep 18 12:50:09 PM UTC 24
Peak memory 212848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65488623 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.65488623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_disable.3814460649
Short name T105
Test name
Test status
Simulation time 72006126 ps
CPU time 1.15 seconds
Started Sep 18 09:42:42 AM UTC 24
Finished Sep 18 09:42:44 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814460649 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3814460649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_disable.1084224400
Short name T71
Test name
Test status
Simulation time 58189688 ps
CPU time 1.13 seconds
Started Sep 18 09:40:54 AM UTC 24
Finished Sep 18 09:40:56 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084224400 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1084224400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_err.931726623
Short name T195
Test name
Test status
Simulation time 27267699 ps
CPU time 1.3 seconds
Started Sep 18 09:41:21 AM UTC 24
Finished Sep 18 09:41:23 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931726623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.edn_err.931726623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_disable.2098838460
Short name T102
Test name
Test status
Simulation time 13399330 ps
CPU time 1.3 seconds
Started Sep 18 09:41:39 AM UTC 24
Finished Sep 18 09:41:41 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098838460 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2098838460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/134.edn_alert.2501336010
Short name T177
Test name
Test status
Simulation time 111771505 ps
CPU time 1.57 seconds
Started Sep 18 09:45:29 AM UTC 24
Finished Sep 18 09:45:32 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501336010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.2501336010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_intr.2670193017
Short name T330
Test name
Test status
Simulation time 37058100 ps
CPU time 1.25 seconds
Started Sep 18 09:41:29 AM UTC 24
Finished Sep 18 09:41:31 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670193017 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.2670193017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.1807470854
Short name T262
Test name
Test status
Simulation time 17623062 ps
CPU time 0.96 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807470854 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1807470854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_intr.2989940906
Short name T28
Test name
Test status
Simulation time 22586479 ps
CPU time 1.41 seconds
Started Sep 18 09:39:18 AM UTC 24
Finished Sep 18 09:39:20 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989940906 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.2989940906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_genbits.3276956396
Short name T308
Test name
Test status
Simulation time 50495391 ps
CPU time 1.88 seconds
Started Sep 18 09:41:37 AM UTC 24
Finished Sep 18 09:41:40 AM UTC 24
Peak memory 228956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276956396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3276956396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.1513519181
Short name T34
Test name
Test status
Simulation time 1494107383 ps
CPU time 39.57 seconds
Started Sep 18 09:39:55 AM UTC 24
Finished Sep 18 09:40:36 AM UTC 24
Peak memory 232340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1513519181 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.1513519181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_alert.2145388796
Short name T88
Test name
Test status
Simulation time 41268013 ps
CPU time 1.51 seconds
Started Sep 18 09:40:24 AM UTC 24
Finished Sep 18 09:40:26 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145388796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.2145388796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_alert.3770519288
Short name T152
Test name
Test status
Simulation time 28941976 ps
CPU time 1.73 seconds
Started Sep 18 09:40:49 AM UTC 24
Finished Sep 18 09:40:52 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770519288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.3770519288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_alert.101876823
Short name T198
Test name
Test status
Simulation time 27757329 ps
CPU time 1.88 seconds
Started Sep 18 09:41:17 AM UTC 24
Finished Sep 18 09:41:20 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101876823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_alert.101876823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_alert.67414437
Short name T168
Test name
Test status
Simulation time 69678683 ps
CPU time 1.43 seconds
Started Sep 18 09:43:03 AM UTC 24
Finished Sep 18 09:43:06 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67414437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_alert.67414437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/61.edn_alert.4000558903
Short name T148
Test name
Test status
Simulation time 104038208 ps
CPU time 1.95 seconds
Started Sep 18 09:44:30 AM UTC 24
Finished Sep 18 09:44:33 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000558903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.4000558903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_intr.693186896
Short name T31
Test name
Test status
Simulation time 26367112 ps
CPU time 1.35 seconds
Started Sep 18 09:40:15 AM UTC 24
Finished Sep 18 09:40:17 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693186896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.693186896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/147.edn_alert.1899517595
Short name T785
Test name
Test status
Simulation time 27066320 ps
CPU time 1.56 seconds
Started Sep 18 09:45:36 AM UTC 24
Finished Sep 18 09:45:39 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899517595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.1899517595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.2576681341
Short name T10
Test name
Test status
Simulation time 143979597 ps
CPU time 1.71 seconds
Started Sep 18 09:39:22 AM UTC 24
Finished Sep 18 09:39:25 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576681341 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.2576681341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.2269427895
Short name T101
Test name
Test status
Simulation time 60821182 ps
CPU time 1.59 seconds
Started Sep 18 09:41:26 AM UTC 24
Finished Sep 18 09:41:29 AM UTC 24
Peak memory 231000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269427895 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.2269427895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_alert.3457553073
Short name T51
Test name
Test status
Simulation time 356145294 ps
CPU time 1.62 seconds
Started Sep 18 09:39:40 AM UTC 24
Finished Sep 18 09:39:43 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457553073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.3457553073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_alert.1528786181
Short name T26
Test name
Test status
Simulation time 37479915 ps
CPU time 1.48 seconds
Started Sep 18 09:39:20 AM UTC 24
Finished Sep 18 09:39:23 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528786181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.1528786181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.1460583864
Short name T175
Test name
Test status
Simulation time 89324115 ps
CPU time 1.5 seconds
Started Sep 18 09:40:25 AM UTC 24
Finished Sep 18 09:40:28 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460583864 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.1460583864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_err.2215590122
Short name T207
Test name
Test status
Simulation time 34835503 ps
CPU time 1.3 seconds
Started Sep 18 09:40:24 AM UTC 24
Finished Sep 18 09:40:26 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215590122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.2215590122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_alert.1885125431
Short name T129
Test name
Test status
Simulation time 125641072 ps
CPU time 1.52 seconds
Started Sep 18 09:40:40 AM UTC 24
Finished Sep 18 09:40:42 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885125431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.1885125431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/131.edn_alert.85568830
Short name T158
Test name
Test status
Simulation time 28679318 ps
CPU time 1.71 seconds
Started Sep 18 09:45:28 AM UTC 24
Finished Sep 18 09:45:31 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85568830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 131.edn_alert.85568830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_disable.2077228677
Short name T96
Test name
Test status
Simulation time 11201087 ps
CPU time 1.17 seconds
Started Sep 18 09:41:23 AM UTC 24
Finished Sep 18 09:41:25 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077228677 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2077228677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_disable.2020324485
Short name T210
Test name
Test status
Simulation time 11206349 ps
CPU time 1.35 seconds
Started Sep 18 09:43:13 AM UTC 24
Finished Sep 18 09:43:16 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020324485 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2020324485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_disable.4036961908
Short name T220
Test name
Test status
Simulation time 22262944 ps
CPU time 1.36 seconds
Started Sep 18 09:43:27 AM UTC 24
Finished Sep 18 09:43:30 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036961908 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4036961908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_genbits.2510200659
Short name T12
Test name
Test status
Simulation time 116872312 ps
CPU time 1.88 seconds
Started Sep 18 09:42:33 AM UTC 24
Finished Sep 18 09:42:36 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510200659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2510200659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_genbits.1169268612
Short name T310
Test name
Test status
Simulation time 158102053 ps
CPU time 3.22 seconds
Started Sep 18 09:42:22 AM UTC 24
Finished Sep 18 09:42:26 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169268612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1169268612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_alert_test.2759282103
Short name T22
Test name
Test status
Simulation time 28335081 ps
CPU time 1.3 seconds
Started Sep 18 09:39:17 AM UTC 24
Finished Sep 18 09:39:19 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759282103 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2759282103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.213580435
Short name T269
Test name
Test status
Simulation time 107226641 ps
CPU time 0.86 seconds
Started Sep 18 12:50:18 PM UTC 24
Finished Sep 18 12:50:23 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213580435 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.213580435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/117.edn_alert.4080151081
Short name T304
Test name
Test status
Simulation time 23405018 ps
CPU time 1.58 seconds
Started Sep 18 09:45:18 AM UTC 24
Finished Sep 18 09:45:22 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080151081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.4080151081
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_genbits.115101096
Short name T42
Test name
Test status
Simulation time 68478857 ps
CPU time 2.96 seconds
Started Sep 18 09:39:35 AM UTC 24
Finished Sep 18 09:39:40 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115101096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_genbits.115101096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/125.edn_genbits.2268408983
Short name T743
Test name
Test status
Simulation time 48005808 ps
CPU time 1.89 seconds
Started Sep 18 09:45:23 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268408983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2268408983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.1101704242
Short name T235
Test name
Test status
Simulation time 6107460940 ps
CPU time 38.75 seconds
Started Sep 18 09:40:28 AM UTC 24
Finished Sep 18 09:41:09 AM UTC 24
Peak memory 228212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1101704242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all
_with_rand_reset.1101704242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_intr.2274679690
Short name T109
Test name
Test status
Simulation time 52241416 ps
CPU time 1.26 seconds
Started Sep 18 09:40:58 AM UTC 24
Finished Sep 18 09:41:01 AM UTC 24
Peak memory 228768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274679690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.2274679690
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.2852224363
Short name T291
Test name
Test status
Simulation time 72420895 ps
CPU time 1.38 seconds
Started Sep 18 12:50:09 PM UTC 24
Finished Sep 18 12:50:13 PM UTC 24
Peak memory 214452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852224363 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2852224363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_smoke.1416961107
Short name T1
Test name
Test status
Simulation time 126635222 ps
CPU time 1.35 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:39:15 AM UTC 24
Peak memory 227576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416961107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_smoke.1416961107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/129.edn_genbits.3391957673
Short name T316
Test name
Test status
Simulation time 91699306 ps
CPU time 2.2 seconds
Started Sep 18 09:45:27 AM UTC 24
Finished Sep 18 09:45:30 AM UTC 24
Peak memory 230048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391957673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3391957673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/133.edn_genbits.2498347729
Short name T760
Test name
Test status
Simulation time 53471078 ps
CPU time 1.73 seconds
Started Sep 18 09:45:29 AM UTC 24
Finished Sep 18 09:45:32 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498347729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2498347729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/160.edn_genbits.2384154593
Short name T320
Test name
Test status
Simulation time 53103326 ps
CPU time 1.92 seconds
Started Sep 18 09:45:43 AM UTC 24
Finished Sep 18 09:45:46 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384154593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2384154593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/188.edn_genbits.258719195
Short name T315
Test name
Test status
Simulation time 58347012 ps
CPU time 1.42 seconds
Started Sep 18 09:45:58 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 231252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258719195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 188.edn_genbits.258719195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/196.edn_genbits.3537269712
Short name T322
Test name
Test status
Simulation time 72952041 ps
CPU time 1.52 seconds
Started Sep 18 09:46:02 AM UTC 24
Finished Sep 18 09:46:04 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537269712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3537269712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/284.edn_genbits.3236068282
Short name T321
Test name
Test status
Simulation time 45974203 ps
CPU time 1.42 seconds
Started Sep 18 09:46:24 AM UTC 24
Finished Sep 18 09:46:26 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236068282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3236068282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_intr.3483978277
Short name T3
Test name
Test status
Simulation time 33617090 ps
CPU time 1.21 seconds
Started Sep 18 09:39:13 AM UTC 24
Finished Sep 18 09:39:15 AM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483978277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.3483978277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_err.2181142193
Short name T7
Test name
Test status
Simulation time 115258049 ps
CPU time 1.33 seconds
Started Sep 18 09:39:29 AM UTC 24
Finished Sep 18 09:39:34 AM UTC 24
Peak memory 230892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181142193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.2181142193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/126.edn_alert.2712756295
Short name T749
Test name
Test status
Simulation time 23913938 ps
CPU time 1.7 seconds
Started Sep 18 09:45:25 AM UTC 24
Finished Sep 18 09:45:28 AM UTC 24
Peak memory 230928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712756295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.2712756295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_disable.2122181660
Short name T229
Test name
Test status
Simulation time 12387721 ps
CPU time 1.19 seconds
Started Sep 18 09:41:17 AM UTC 24
Finished Sep 18 09:41:19 AM UTC 24
Peak memory 216780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122181660 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2122181660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_alert.2487266016
Short name T137
Test name
Test status
Simulation time 100615539 ps
CPU time 1.8 seconds
Started Sep 18 09:42:35 AM UTC 24
Finished Sep 18 09:42:38 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487266016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.2487266016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/278.edn_genbits.3089547731
Short name T959
Test name
Test status
Simulation time 158721603 ps
CPU time 1.92 seconds
Started Sep 18 09:46:22 AM UTC 24
Finished Sep 18 09:46:25 AM UTC 24
Peak memory 229260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089547731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3089547731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/93.edn_genbits.2174935859
Short name T338
Test name
Test status
Simulation time 39833122 ps
CPU time 2.35 seconds
Started Sep 18 09:45:02 AM UTC 24
Finished Sep 18 09:45:07 AM UTC 24
Peak memory 230200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174935859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2174935859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.538001151
Short name T260
Test name
Test status
Simulation time 23815846 ps
CPU time 1.16 seconds
Started Sep 18 12:50:08 PM UTC 24
Finished Sep 18 12:50:10 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538001151 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.538001151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.1603349571
Short name T987
Test name
Test status
Simulation time 158204367 ps
CPU time 2.13 seconds
Started Sep 18 12:50:08 PM UTC 24
Finished Sep 18 12:50:11 PM UTC 24
Peak memory 216848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603349571 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1603349571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.743616225
Short name T983
Test name
Test status
Simulation time 31671802 ps
CPU time 0.85 seconds
Started Sep 18 12:50:06 PM UTC 24
Finished Sep 18 12:50:08 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743616225 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.743616225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1337907700
Short name T985
Test name
Test status
Simulation time 37136276 ps
CPU time 1.17 seconds
Started Sep 18 12:50:08 PM UTC 24
Finished Sep 18 12:50:10 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1337907700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1337907700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.4148080775
Short name T984
Test name
Test status
Simulation time 15218425 ps
CPU time 0.85 seconds
Started Sep 18 12:50:08 PM UTC 24
Finished Sep 18 12:50:10 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148080775 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4148080775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.1473819060
Short name T982
Test name
Test status
Simulation time 23070266 ps
CPU time 0.74 seconds
Started Sep 18 12:50:06 PM UTC 24
Finished Sep 18 12:50:08 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473819060 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1473819060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.2114289481
Short name T275
Test name
Test status
Simulation time 21076985 ps
CPU time 1.09 seconds
Started Sep 18 12:50:08 PM UTC 24
Finished Sep 18 12:50:10 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114289481 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2114289481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.3876844553
Short name T986
Test name
Test status
Simulation time 193848288 ps
CPU time 3.46 seconds
Started Sep 18 12:50:06 PM UTC 24
Finished Sep 18 12:50:11 PM UTC 24
Peak memory 225028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876844553 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3876844553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.1959525859
Short name T993
Test name
Test status
Simulation time 136662681 ps
CPU time 3.02 seconds
Started Sep 18 12:50:10 PM UTC 24
Finished Sep 18 12:50:15 PM UTC 24
Peak memory 217100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959525859 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1959525859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.277039165
Short name T261
Test name
Test status
Simulation time 20832862 ps
CPU time 0.99 seconds
Started Sep 18 12:50:09 PM UTC 24
Finished Sep 18 12:50:12 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277039165 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.277039165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.824342201
Short name T989
Test name
Test status
Simulation time 48892672 ps
CPU time 0.87 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=824342201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.824342201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.3200256599
Short name T276
Test name
Test status
Simulation time 22981300 ps
CPU time 0.89 seconds
Started Sep 18 12:50:09 PM UTC 24
Finished Sep 18 12:50:13 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200256599 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3200256599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.313073299
Short name T988
Test name
Test status
Simulation time 18598771 ps
CPU time 0.81 seconds
Started Sep 18 12:50:09 PM UTC 24
Finished Sep 18 12:50:12 PM UTC 24
Peak memory 214348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313073299 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.313073299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.2819614106
Short name T277
Test name
Test status
Simulation time 17388006 ps
CPU time 1.02 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819614106 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.2819614106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.566676032
Short name T991
Test name
Test status
Simulation time 162423196 ps
CPU time 2.66 seconds
Started Sep 18 12:50:09 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 227160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566676032 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.566676032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1113194412
Short name T1075
Test name
Test status
Simulation time 69738632 ps
CPU time 0.96 seconds
Started Sep 18 12:50:21 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1113194412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1113194412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2446860458
Short name T272
Test name
Test status
Simulation time 56360003 ps
CPU time 0.86 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446860458 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2446860458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.1641362637
Short name T1040
Test name
Test status
Simulation time 24126609 ps
CPU time 0.91 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 214016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641362637 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1641362637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.23527286
Short name T1044
Test name
Test status
Simulation time 30018123 ps
CPU time 1.22 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23527286 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.23527286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.2958820011
Short name T1047
Test name
Test status
Simulation time 577613587 ps
CPU time 2.33 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:35 PM UTC 24
Peak memory 226716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958820011 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2958820011
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3151397637
Short name T1048
Test name
Test status
Simulation time 335959026 ps
CPU time 2.3 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:35 PM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151397637 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3151397637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3296279163
Short name T1023
Test name
Test status
Simulation time 34412410 ps
CPU time 0.92 seconds
Started Sep 18 12:50:25 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3296279163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3296279163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3934477975
Short name T1022
Test name
Test status
Simulation time 25933651 ps
CPU time 0.83 seconds
Started Sep 18 12:50:25 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934477975 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3934477975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.4099169639
Short name T1020
Test name
Test status
Simulation time 13649359 ps
CPU time 0.8 seconds
Started Sep 18 12:50:25 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099169639 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4099169639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3188147869
Short name T1025
Test name
Test status
Simulation time 120653754 ps
CPU time 1.21 seconds
Started Sep 18 12:50:25 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188147869 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.3188147869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2971662744
Short name T1085
Test name
Test status
Simulation time 71062255 ps
CPU time 1.3 seconds
Started Sep 18 12:50:23 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 229084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971662744 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2971662744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1718956841
Short name T297
Test name
Test status
Simulation time 84474608 ps
CPU time 2.15 seconds
Started Sep 18 12:50:25 PM UTC 24
Finished Sep 18 12:50:31 PM UTC 24
Peak memory 227084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718956841 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1718956841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.23474828
Short name T1084
Test name
Test status
Simulation time 97762337 ps
CPU time 1.37 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 224992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=23474828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.23474828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.2316835661
Short name T1079
Test name
Test status
Simulation time 15193190 ps
CPU time 0.92 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316835661 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2316835661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.356455909
Short name T1080
Test name
Test status
Simulation time 12408034 ps
CPU time 0.92 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356455909 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.356455909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1437170991
Short name T1083
Test name
Test status
Simulation time 22835162 ps
CPU time 1.19 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 214772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437170991 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.1437170991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.2380102541
Short name T1031
Test name
Test status
Simulation time 90600333 ps
CPU time 2.49 seconds
Started Sep 18 12:50:25 PM UTC 24
Finished Sep 18 12:50:31 PM UTC 24
Peak memory 227148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380102541 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2380102541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.240971620
Short name T1027
Test name
Test status
Simulation time 113249287 ps
CPU time 2.53 seconds
Started Sep 18 12:50:27 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 227352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240971620 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.240971620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1650256849
Short name T1038
Test name
Test status
Simulation time 50114469 ps
CPU time 1.02 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1650256849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1650256849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.177593761
Short name T1050
Test name
Test status
Simulation time 20701475 ps
CPU time 0.74 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:38 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177593761 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.177593761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.3630923574
Short name T1051
Test name
Test status
Simulation time 13985440 ps
CPU time 0.82 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:38 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630923574 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3630923574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.911919383
Short name T1037
Test name
Test status
Simulation time 120356268 ps
CPU time 1.12 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911919383 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.911919383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1803562517
Short name T1086
Test name
Test status
Simulation time 897206560 ps
CPU time 4.95 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 227212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803562517 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1803562517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.2869756095
Short name T1057
Test name
Test status
Simulation time 55575792 ps
CPU time 1.64 seconds
Started Sep 18 12:50:29 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869756095 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2869756095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1242462505
Short name T1042
Test name
Test status
Simulation time 34016451 ps
CPU time 1.22 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1242462505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1242462505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.4270714729
Short name T271
Test name
Test status
Simulation time 17326874 ps
CPU time 0.78 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 213908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270714729 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4270714729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.732292339
Short name T1034
Test name
Test status
Simulation time 153765390 ps
CPU time 0.77 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732292339 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.732292339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1140614990
Short name T1041
Test name
Test status
Simulation time 20358683 ps
CPU time 1.12 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140614990 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.1140614990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1766665507
Short name T1043
Test name
Test status
Simulation time 44048822 ps
CPU time 1.46 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766665507 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1766665507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2068843958
Short name T1049
Test name
Test status
Simulation time 163054318 ps
CPU time 3.27 seconds
Started Sep 18 12:50:31 PM UTC 24
Finished Sep 18 12:50:36 PM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068843958 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2068843958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2607485217
Short name T1077
Test name
Test status
Simulation time 49826763 ps
CPU time 1.06 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 224656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2607485217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2607485217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1965122759
Short name T1073
Test name
Test status
Simulation time 19524847 ps
CPU time 0.76 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965122759 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1965122759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1902135984
Short name T1035
Test name
Test status
Simulation time 18053091 ps
CPU time 0.75 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902135984 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1902135984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.3972449169
Short name T1078
Test name
Test status
Simulation time 42013969 ps
CPU time 1.01 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 214280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972449169 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.3972449169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.855235114
Short name T1046
Test name
Test status
Simulation time 117313949 ps
CPU time 2.04 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:35 PM UTC 24
Peak memory 227144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855235114 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.855235114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.2821240923
Short name T1110
Test name
Test status
Simulation time 942670950 ps
CPU time 5.1 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 217036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821240923 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2821240923
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4015183319
Short name T1063
Test name
Test status
Simulation time 93669041 ps
CPU time 1.08 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4015183319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4015183319
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.442267799
Short name T274
Test name
Test status
Simulation time 18119458 ps
CPU time 0.81 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442267799 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.442267799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3946153468
Short name T1076
Test name
Test status
Simulation time 28325085 ps
CPU time 0.72 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946153468 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3946153468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.4253371389
Short name T1067
Test name
Test status
Simulation time 110730597 ps
CPU time 1.32 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253371389 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.4253371389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.1779302144
Short name T1081
Test name
Test status
Simulation time 19843063 ps
CPU time 1.28 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779302144 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1779302144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1194577904
Short name T1082
Test name
Test status
Simulation time 52177213 ps
CPU time 1.47 seconds
Started Sep 18 12:50:32 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194577904 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1194577904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2512722215
Short name T1065
Test name
Test status
Simulation time 65828871 ps
CPU time 1 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2512722215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2512722215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.3373725570
Short name T1062
Test name
Test status
Simulation time 25226626 ps
CPU time 0.85 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373725570 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3373725570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3669431808
Short name T1060
Test name
Test status
Simulation time 36494439 ps
CPU time 0.84 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669431808 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3669431808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.4134613206
Short name T1066
Test name
Test status
Simulation time 44841846 ps
CPU time 1.05 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134613206 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.4134613206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.402046701
Short name T1072
Test name
Test status
Simulation time 416262201 ps
CPU time 2.28 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402046701 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.402046701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.325141294
Short name T1069
Test name
Test status
Simulation time 48971067 ps
CPU time 1.58 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325141294 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.325141294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4274819125
Short name T1052
Test name
Test status
Simulation time 88734033 ps
CPU time 0.86 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:38 PM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4274819125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4274819125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.4210862183
Short name T1064
Test name
Test status
Simulation time 47689518 ps
CPU time 0.81 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210862183 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.4210862183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.380129120
Short name T1061
Test name
Test status
Simulation time 41195991 ps
CPU time 0.83 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380129120 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.380129120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.4198370165
Short name T1054
Test name
Test status
Simulation time 21568660 ps
CPU time 1.01 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 216068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198370165 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.4198370165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.465384220
Short name T1074
Test name
Test status
Simulation time 45852298 ps
CPU time 2.12 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:41 PM UTC 24
Peak memory 227088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465384220 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.465384220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.180155405
Short name T1071
Test name
Test status
Simulation time 466690362 ps
CPU time 1.65 seconds
Started Sep 18 12:50:34 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180155405 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.180155405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3319160330
Short name T1059
Test name
Test status
Simulation time 20597805 ps
CPU time 1.12 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3319160330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3319160330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3349581973
Short name T1053
Test name
Test status
Simulation time 41994627 ps
CPU time 0.72 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349581973 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3349581973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3290876218
Short name T1055
Test name
Test status
Simulation time 44823615 ps
CPU time 0.79 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290876218 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3290876218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.4154487529
Short name T1058
Test name
Test status
Simulation time 81690481 ps
CPU time 1.02 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154487529 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.4154487529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2251535404
Short name T1068
Test name
Test status
Simulation time 58751145 ps
CPU time 2.03 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251535404 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2251535404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3162489868
Short name T1070
Test name
Test status
Simulation time 154522513 ps
CPU time 2.22 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:40 PM UTC 24
Peak memory 227352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162489868 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3162489868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.345022980
Short name T264
Test name
Test status
Simulation time 26334166 ps
CPU time 1.17 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345022980 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.345022980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.274680261
Short name T995
Test name
Test status
Simulation time 543511659 ps
CPU time 2.65 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:16 PM UTC 24
Peak memory 216972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274680261 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.274680261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.1904624089
Short name T992
Test name
Test status
Simulation time 18026719 ps
CPU time 0.88 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904624089 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1904624089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1241363644
Short name T997
Test name
Test status
Simulation time 64494234 ps
CPU time 1.02 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1241363644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1241363644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.3452606117
Short name T263
Test name
Test status
Simulation time 14607406 ps
CPU time 0.91 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452606117 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3452606117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.2152602125
Short name T990
Test name
Test status
Simulation time 29588029 ps
CPU time 0.79 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:14 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152602125 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2152602125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.2272065453
Short name T278
Test name
Test status
Simulation time 51646107 ps
CPU time 1.24 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272065453 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.2272065453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.1964542370
Short name T994
Test name
Test status
Simulation time 357655631 ps
CPU time 2.01 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:15 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964542370 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1964542370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.1297015566
Short name T292
Test name
Test status
Simulation time 90054320 ps
CPU time 1.48 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:15 PM UTC 24
Peak memory 225052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297015566 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1297015566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.69762485
Short name T1056
Test name
Test status
Simulation time 70509324 ps
CPU time 0.75 seconds
Started Sep 18 12:50:37 PM UTC 24
Finished Sep 18 12:50:39 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69762485 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.69762485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4184462421
Short name T1089
Test name
Test status
Simulation time 64807972 ps
CPU time 0.83 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 214484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184462421 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4184462421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.1665109063
Short name T1087
Test name
Test status
Simulation time 30350813 ps
CPU time 0.76 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 214356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665109063 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1665109063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3978371940
Short name T1088
Test name
Test status
Simulation time 63417021 ps
CPU time 0.83 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978371940 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3978371940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3571996194
Short name T1095
Test name
Test status
Simulation time 26500976 ps
CPU time 1.03 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571996194 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3571996194
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.176754241
Short name T1090
Test name
Test status
Simulation time 41606847 ps
CPU time 0.8 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176754241 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.176754241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.301816930
Short name T1091
Test name
Test status
Simulation time 17151855 ps
CPU time 0.77 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:42 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301816930 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.301816930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1408225210
Short name T1092
Test name
Test status
Simulation time 100114811 ps
CPU time 0.81 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408225210 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1408225210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.4174690338
Short name T1094
Test name
Test status
Simulation time 27467305 ps
CPU time 0.98 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174690338 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4174690338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3699703315
Short name T1093
Test name
Test status
Simulation time 40935896 ps
CPU time 0.88 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699703315 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3699703315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.4290510538
Short name T267
Test name
Test status
Simulation time 44399034 ps
CPU time 0.97 seconds
Started Sep 18 12:50:13 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290510538 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4290510538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.1078299040
Short name T1004
Test name
Test status
Simulation time 34290786 ps
CPU time 1.89 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:19 PM UTC 24
Peak memory 214808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078299040 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1078299040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.559434034
Short name T266
Test name
Test status
Simulation time 13442605 ps
CPU time 0.87 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559434034 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.559434034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2068980494
Short name T1002
Test name
Test status
Simulation time 22466559 ps
CPU time 1.31 seconds
Started Sep 18 12:50:13 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 227044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2068980494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2068980494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2603838151
Short name T265
Test name
Test status
Simulation time 14799481 ps
CPU time 0.91 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603838151 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2603838151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.21506881
Short name T996
Test name
Test status
Simulation time 16873124 ps
CPU time 0.9 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21506881 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.21506881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1446540680
Short name T279
Test name
Test status
Simulation time 203474216 ps
CPU time 1.05 seconds
Started Sep 18 12:50:13 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446540680 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1446540680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.2856768729
Short name T999
Test name
Test status
Simulation time 72627862 ps
CPU time 1.3 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856768729 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2856768729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2897083576
Short name T298
Test name
Test status
Simulation time 134128287 ps
CPU time 1.42 seconds
Started Sep 18 12:50:12 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897083576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2897083576
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2066512656
Short name T1099
Test name
Test status
Simulation time 173958181 ps
CPU time 1 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066512656 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2066512656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.4137874093
Short name T1096
Test name
Test status
Simulation time 12433714 ps
CPU time 0.86 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137874093 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4137874093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3731189292
Short name T1100
Test name
Test status
Simulation time 32085501 ps
CPU time 0.95 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731189292 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3731189292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.2380985567
Short name T1098
Test name
Test status
Simulation time 55022463 ps
CPU time 0.85 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380985567 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2380985567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.4091618892
Short name T1097
Test name
Test status
Simulation time 14152035 ps
CPU time 0.86 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091618892 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4091618892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.321335932
Short name T1101
Test name
Test status
Simulation time 20482704 ps
CPU time 0.87 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321335932 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.321335932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3928899603
Short name T1104
Test name
Test status
Simulation time 13888463 ps
CPU time 0.93 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928899603 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3928899603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.3610621033
Short name T1102
Test name
Test status
Simulation time 51392080 ps
CPU time 0.9 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610621033 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3610621033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.195899724
Short name T1103
Test name
Test status
Simulation time 12676848 ps
CPU time 0.8 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195899724 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.195899724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.2664279480
Short name T1105
Test name
Test status
Simulation time 20559083 ps
CPU time 0.85 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664279480 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2664279480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.804464976
Short name T1003
Test name
Test status
Simulation time 25258616 ps
CPU time 1.34 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804464976 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.804464976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.262205609
Short name T273
Test name
Test status
Simulation time 229169586 ps
CPU time 3.04 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:20 PM UTC 24
Peak memory 216788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262205609 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.262205609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.936311470
Short name T268
Test name
Test status
Simulation time 36223061 ps
CPU time 0.83 seconds
Started Sep 18 12:50:15 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936311470 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.936311470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2073970814
Short name T1013
Test name
Test status
Simulation time 43937668 ps
CPU time 1.26 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2073970814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2073970814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.1631672266
Short name T1000
Test name
Test status
Simulation time 17054353 ps
CPU time 0.91 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631672266 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1631672266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.177351013
Short name T998
Test name
Test status
Simulation time 25298622 ps
CPU time 0.72 seconds
Started Sep 18 12:50:15 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177351013 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.177351013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3151709161
Short name T280
Test name
Test status
Simulation time 132113955 ps
CPU time 1.04 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151709161 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3151709161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.1592902315
Short name T1001
Test name
Test status
Simulation time 66607038 ps
CPU time 1.13 seconds
Started Sep 18 12:50:13 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592902315 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1592902315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.593789356
Short name T296
Test name
Test status
Simulation time 59914699 ps
CPU time 1.66 seconds
Started Sep 18 12:50:13 PM UTC 24
Finished Sep 18 12:50:18 PM UTC 24
Peak memory 224928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593789356 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.593789356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.920760822
Short name T1106
Test name
Test status
Simulation time 18727593 ps
CPU time 1 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920760822 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.920760822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1256382684
Short name T1107
Test name
Test status
Simulation time 12331458 ps
CPU time 0.85 seconds
Started Sep 18 12:50:41 PM UTC 24
Finished Sep 18 12:50:43 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256382684 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1256382684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2184344768
Short name T1108
Test name
Test status
Simulation time 74400009 ps
CPU time 0.83 seconds
Started Sep 18 12:50:42 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184344768 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2184344768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.4031246550
Short name T1111
Test name
Test status
Simulation time 42408859 ps
CPU time 0.89 seconds
Started Sep 18 12:50:42 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031246550 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4031246550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1924693452
Short name T1112
Test name
Test status
Simulation time 14714153 ps
CPU time 0.85 seconds
Started Sep 18 12:50:42 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924693452 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1924693452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.402789745
Short name T1113
Test name
Test status
Simulation time 24674230 ps
CPU time 0.83 seconds
Started Sep 18 12:50:43 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402789745 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.402789745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.945512816
Short name T1109
Test name
Test status
Simulation time 49132592 ps
CPU time 0.77 seconds
Started Sep 18 12:50:43 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945512816 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.945512816
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.1377836161
Short name T1114
Test name
Test status
Simulation time 17352358 ps
CPU time 0.84 seconds
Started Sep 18 12:50:43 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377836161 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1377836161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.1801545130
Short name T1115
Test name
Test status
Simulation time 19604908 ps
CPU time 0.9 seconds
Started Sep 18 12:50:43 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801545130 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1801545130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.201809447
Short name T1116
Test name
Test status
Simulation time 30535889 ps
CPU time 0.88 seconds
Started Sep 18 12:50:43 PM UTC 24
Finished Sep 18 12:50:45 PM UTC 24
Peak memory 214728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201809447 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.201809447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1938249964
Short name T1015
Test name
Test status
Simulation time 50295151 ps
CPU time 1.26 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1938249964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1938249964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.1018958804
Short name T282
Test name
Test status
Simulation time 23762148 ps
CPU time 0.82 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018958804 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1018958804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.248021070
Short name T1010
Test name
Test status
Simulation time 27717490 ps
CPU time 0.84 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248021070 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.248021070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.2860295721
Short name T1012
Test name
Test status
Simulation time 70174667 ps
CPU time 0.94 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860295721 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.2860295721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.3281138016
Short name T1018
Test name
Test status
Simulation time 49575375 ps
CPU time 1.69 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 224928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281138016 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3281138016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.3252658799
Short name T1017
Test name
Test status
Simulation time 179815369 ps
CPU time 1.52 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 224992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252658799 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3252658799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1971347573
Short name T1014
Test name
Test status
Simulation time 65164180 ps
CPU time 0.88 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1971347573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1971347573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.252553038
Short name T270
Test name
Test status
Simulation time 24284266 ps
CPU time 0.83 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252553038 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.252553038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2197246355
Short name T1011
Test name
Test status
Simulation time 108983414 ps
CPU time 0.78 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:28 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197246355 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2197246355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3222440016
Short name T1016
Test name
Test status
Simulation time 28778007 ps
CPU time 1.23 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222440016 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.3222440016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2682575226
Short name T1021
Test name
Test status
Simulation time 208505259 ps
CPU time 2.28 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682575226 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2682575226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4104487853
Short name T299
Test name
Test status
Simulation time 136316732 ps
CPU time 1.39 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 214640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104487853 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4104487853
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1320412098
Short name T1007
Test name
Test status
Simulation time 35901705 ps
CPU time 1.18 seconds
Started Sep 18 12:50:18 PM UTC 24
Finished Sep 18 12:50:23 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1320412098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1320412098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.2904154219
Short name T1005
Test name
Test status
Simulation time 14763467 ps
CPU time 0.78 seconds
Started Sep 18 12:50:18 PM UTC 24
Finished Sep 18 12:50:23 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904154219 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2904154219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2088187518
Short name T281
Test name
Test status
Simulation time 124325064 ps
CPU time 1.25 seconds
Started Sep 18 12:50:18 PM UTC 24
Finished Sep 18 12:50:23 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088187518 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.2088187518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2845606268
Short name T1019
Test name
Test status
Simulation time 111939677 ps
CPU time 1.82 seconds
Started Sep 18 12:50:16 PM UTC 24
Finished Sep 18 12:50:29 PM UTC 24
Peak memory 224928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845606268 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2845606268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.730325949
Short name T1008
Test name
Test status
Simulation time 87033365 ps
CPU time 2.27 seconds
Started Sep 18 12:50:18 PM UTC 24
Finished Sep 18 12:50:24 PM UTC 24
Peak memory 216784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730325949 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.730325949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1833390117
Short name T1029
Test name
Test status
Simulation time 19079231 ps
CPU time 1.27 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:31 PM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1833390117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1833390117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3339000228
Short name T1024
Test name
Test status
Simulation time 13148979 ps
CPU time 0.8 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339000228 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3339000228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.3265480352
Short name T1006
Test name
Test status
Simulation time 12597357 ps
CPU time 0.8 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:23 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265480352 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3265480352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.771926480
Short name T1028
Test name
Test status
Simulation time 110947723 ps
CPU time 1.19 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:31 PM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771926480 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.771926480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.3827673184
Short name T1009
Test name
Test status
Simulation time 658489023 ps
CPU time 3.64 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:26 PM UTC 24
Peak memory 227212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827673184 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3827673184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.714941689
Short name T1030
Test name
Test status
Simulation time 134454306 ps
CPU time 1.68 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:31 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714941689 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.714941689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.561595941
Short name T1045
Test name
Test status
Simulation time 50322843 ps
CPU time 1.49 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:34 PM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=561595941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.561595941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.2437304044
Short name T1036
Test name
Test status
Simulation time 11164286 ps
CPU time 0.96 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437304044 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2437304044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.566339592
Short name T1026
Test name
Test status
Simulation time 23346563 ps
CPU time 0.8 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:30 PM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566339592 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.566339592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.2006298494
Short name T1039
Test name
Test status
Simulation time 14934897 ps
CPU time 0.96 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:33 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006298494 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.2006298494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.2720610742
Short name T1033
Test name
Test status
Simulation time 261741953 ps
CPU time 2.4 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:32 PM UTC 24
Peak memory 226888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720610742 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2720610742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.957815600
Short name T1032
Test name
Test status
Simulation time 782881999 ps
CPU time 2.06 seconds
Started Sep 18 12:50:20 PM UTC 24
Finished Sep 18 12:50:31 PM UTC 24
Peak memory 216852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957815600 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.957815600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_disable.102889407
Short name T19
Test name
Test status
Simulation time 50967091 ps
CPU time 1.2 seconds
Started Sep 18 09:39:13 AM UTC 24
Finished Sep 18 09:39:15 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102889407 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.102889407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_err.3679105190
Short name T4
Test name
Test status
Simulation time 22545899 ps
CPU time 1.48 seconds
Started Sep 18 09:39:13 AM UTC 24
Finished Sep 18 09:39:15 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679105190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.3679105190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_genbits.2284591003
Short name T21
Test name
Test status
Simulation time 47795266 ps
CPU time 1.85 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:39:16 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284591003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2284591003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_sec_cm.596302918
Short name T15
Test name
Test status
Simulation time 2667286755 ps
CPU time 11.02 seconds
Started Sep 18 09:39:17 AM UTC 24
Finished Sep 18 09:39:29 AM UTC 24
Peak memory 260860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596302918 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.596302918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_stress_all.3145922288
Short name T5
Test name
Test status
Simulation time 111266996 ps
CPU time 3.4 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:39:17 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145922288 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3145922288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.544402896
Short name T233
Test name
Test status
Simulation time 4592186312 ps
CPU time 102.5 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:40:58 AM UTC 24
Peak memory 230296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=544402896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_w
ith_rand_reset.544402896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_alert_test.1214321308
Short name T61
Test name
Test status
Simulation time 41017793 ps
CPU time 1.16 seconds
Started Sep 18 09:39:22 AM UTC 24
Finished Sep 18 09:39:25 AM UTC 24
Peak memory 227556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214321308 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1214321308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_disable.3174402975
Short name T37
Test name
Test status
Simulation time 37264962 ps
CPU time 1.21 seconds
Started Sep 18 09:39:20 AM UTC 24
Finished Sep 18 09:39:23 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174402975 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3174402975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_err.879193531
Short name T6
Test name
Test status
Simulation time 25679974 ps
CPU time 1.27 seconds
Started Sep 18 09:39:20 AM UTC 24
Finished Sep 18 09:39:22 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879193531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.edn_err.879193531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_regwen.3679518227
Short name T24
Test name
Test status
Simulation time 19117636 ps
CPU time 1.52 seconds
Started Sep 18 09:39:18 AM UTC 24
Finished Sep 18 09:39:20 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679518227 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.3679518227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_smoke.651477844
Short name T23
Test name
Test status
Simulation time 17029237 ps
CPU time 1.36 seconds
Started Sep 18 09:39:17 AM UTC 24
Finished Sep 18 09:39:19 AM UTC 24
Peak memory 226860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651477844 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.edn_smoke.651477844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_stress_all.1588022301
Short name T39
Test name
Test status
Simulation time 2065590882 ps
CPU time 5.54 seconds
Started Sep 18 09:39:18 AM UTC 24
Finished Sep 18 09:39:25 AM UTC 24
Peak memory 228060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588022301 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1588022301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.1661767794
Short name T212
Test name
Test status
Simulation time 32746052924 ps
CPU time 95.5 seconds
Started Sep 18 09:39:18 AM UTC 24
Finished Sep 18 09:40:56 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1661767794 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_
with_rand_reset.1661767794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_alert_test.4093110317
Short name T352
Test name
Test status
Simulation time 73002155 ps
CPU time 1.27 seconds
Started Sep 18 09:40:26 AM UTC 24
Finished Sep 18 09:40:29 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093110317 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4093110317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_disable.3873661683
Short name T80
Test name
Test status
Simulation time 34871311 ps
CPU time 1.14 seconds
Started Sep 18 09:40:25 AM UTC 24
Finished Sep 18 09:40:27 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873661683 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3873661683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_genbits.3094694491
Short name T74
Test name
Test status
Simulation time 62568379 ps
CPU time 1.65 seconds
Started Sep 18 09:40:23 AM UTC 24
Finished Sep 18 09:40:25 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094694491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3094694491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_intr.1134498854
Short name T68
Test name
Test status
Simulation time 25287374 ps
CPU time 1.36 seconds
Started Sep 18 09:40:23 AM UTC 24
Finished Sep 18 09:40:25 AM UTC 24
Peak memory 229136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134498854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.1134498854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_smoke.3905631964
Short name T121
Test name
Test status
Simulation time 55233467 ps
CPU time 1.24 seconds
Started Sep 18 09:40:22 AM UTC 24
Finished Sep 18 09:40:24 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905631964 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.3905631964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_stress_all.554306003
Short name T122
Test name
Test status
Simulation time 654004682 ps
CPU time 4.91 seconds
Started Sep 18 09:40:23 AM UTC 24
Finished Sep 18 09:40:29 AM UTC 24
Peak memory 228180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554306003 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.554306003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.3959049147
Short name T237
Test name
Test status
Simulation time 2237370245 ps
CPU time 58.7 seconds
Started Sep 18 09:40:23 AM UTC 24
Finished Sep 18 09:41:23 AM UTC 24
Peak memory 230280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3959049147 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all
_with_rand_reset.3959049147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/100.edn_alert.298905646
Short name T700
Test name
Test status
Simulation time 50947662 ps
CPU time 1.69 seconds
Started Sep 18 09:45:08 AM UTC 24
Finished Sep 18 09:45:11 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298905646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 100.edn_alert.298905646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/100.edn_genbits.2319100657
Short name T701
Test name
Test status
Simulation time 35186603 ps
CPU time 1.76 seconds
Started Sep 18 09:45:08 AM UTC 24
Finished Sep 18 09:45:11 AM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319100657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2319100657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/101.edn_alert.3711919693
Short name T704
Test name
Test status
Simulation time 22364348 ps
CPU time 1.6 seconds
Started Sep 18 09:45:10 AM UTC 24
Finished Sep 18 09:45:12 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711919693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 101.edn_alert.3711919693
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/101.edn_genbits.727906685
Short name T702
Test name
Test status
Simulation time 44027025 ps
CPU time 1.81 seconds
Started Sep 18 09:45:08 AM UTC 24
Finished Sep 18 09:45:11 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727906685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 101.edn_genbits.727906685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/102.edn_alert.4250838573
Short name T705
Test name
Test status
Simulation time 28952948 ps
CPU time 1.66 seconds
Started Sep 18 09:45:10 AM UTC 24
Finished Sep 18 09:45:12 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250838573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.4250838573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/102.edn_genbits.2729908806
Short name T703
Test name
Test status
Simulation time 41223451 ps
CPU time 1.37 seconds
Started Sep 18 09:45:10 AM UTC 24
Finished Sep 18 09:45:12 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729908806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2729908806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/103.edn_alert.2637247542
Short name T708
Test name
Test status
Simulation time 30510481 ps
CPU time 2.03 seconds
Started Sep 18 09:45:11 AM UTC 24
Finished Sep 18 09:45:14 AM UTC 24
Peak memory 232644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637247542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.2637247542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/103.edn_genbits.2180312993
Short name T706
Test name
Test status
Simulation time 61794293 ps
CPU time 1.61 seconds
Started Sep 18 09:45:11 AM UTC 24
Finished Sep 18 09:45:14 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180312993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2180312993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/104.edn_alert.575350929
Short name T707
Test name
Test status
Simulation time 61139158 ps
CPU time 1.55 seconds
Started Sep 18 09:45:11 AM UTC 24
Finished Sep 18 09:45:14 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575350929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 104.edn_alert.575350929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/104.edn_genbits.2958263045
Short name T710
Test name
Test status
Simulation time 63601359 ps
CPU time 1.96 seconds
Started Sep 18 09:45:11 AM UTC 24
Finished Sep 18 09:45:14 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958263045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2958263045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/105.edn_alert.2107147730
Short name T711
Test name
Test status
Simulation time 58815766 ps
CPU time 1.23 seconds
Started Sep 18 09:45:12 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107147730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 105.edn_alert.2107147730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/105.edn_genbits.3122320369
Short name T714
Test name
Test status
Simulation time 159928237 ps
CPU time 2.93 seconds
Started Sep 18 09:45:11 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122320369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3122320369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/106.edn_alert.1609906448
Short name T712
Test name
Test status
Simulation time 22928702 ps
CPU time 1.48 seconds
Started Sep 18 09:45:12 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 232200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609906448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.1609906448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/106.edn_genbits.1079380863
Short name T715
Test name
Test status
Simulation time 30294487 ps
CPU time 1.76 seconds
Started Sep 18 09:45:12 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 228560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079380863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1079380863
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/107.edn_alert.660962045
Short name T713
Test name
Test status
Simulation time 78428774 ps
CPU time 1.37 seconds
Started Sep 18 09:45:12 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660962045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 107.edn_alert.660962045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/107.edn_genbits.1528692977
Short name T717
Test name
Test status
Simulation time 69420810 ps
CPU time 1.75 seconds
Started Sep 18 09:45:12 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528692977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1528692977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/108.edn_alert.4098154289
Short name T719
Test name
Test status
Simulation time 40261481 ps
CPU time 1.55 seconds
Started Sep 18 09:45:13 AM UTC 24
Finished Sep 18 09:45:17 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098154289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.edn_alert.4098154289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/108.edn_genbits.738010870
Short name T716
Test name
Test status
Simulation time 42122984 ps
CPU time 1.59 seconds
Started Sep 18 09:45:12 AM UTC 24
Finished Sep 18 09:45:15 AM UTC 24
Peak memory 229204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738010870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 108.edn_genbits.738010870
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/109.edn_alert.2977686053
Short name T718
Test name
Test status
Simulation time 109114616 ps
CPU time 1.27 seconds
Started Sep 18 09:45:13 AM UTC 24
Finished Sep 18 09:45:17 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977686053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.2977686053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/109.edn_genbits.3547178216
Short name T659
Test name
Test status
Simulation time 48154469 ps
CPU time 2.36 seconds
Started Sep 18 09:45:13 AM UTC 24
Finished Sep 18 09:45:18 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547178216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3547178216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_alert.1092843099
Short name T75
Test name
Test status
Simulation time 36878825 ps
CPU time 1.3 seconds
Started Sep 18 09:40:30 AM UTC 24
Finished Sep 18 09:40:32 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092843099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.1092843099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_alert_test.1458574589
Short name T355
Test name
Test status
Simulation time 19504809 ps
CPU time 1.47 seconds
Started Sep 18 09:40:32 AM UTC 24
Finished Sep 18 09:40:34 AM UTC 24
Peak memory 227388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458574589 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1458574589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_disable.2671875583
Short name T95
Test name
Test status
Simulation time 33895094 ps
CPU time 1.15 seconds
Started Sep 18 09:40:30 AM UTC 24
Finished Sep 18 09:40:32 AM UTC 24
Peak memory 226728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671875583 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2671875583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3583759042
Short name T356
Test name
Test status
Simulation time 61508029 ps
CPU time 1.7 seconds
Started Sep 18 09:40:32 AM UTC 24
Finished Sep 18 09:40:35 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583759042 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3583759042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_err.232533784
Short name T183
Test name
Test status
Simulation time 23818757 ps
CPU time 1.43 seconds
Started Sep 18 09:40:30 AM UTC 24
Finished Sep 18 09:40:32 AM UTC 24
Peak memory 238220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232533784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 11.edn_err.232533784
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_genbits.3009716785
Short name T118
Test name
Test status
Simulation time 45592373 ps
CPU time 2.15 seconds
Started Sep 18 09:40:27 AM UTC 24
Finished Sep 18 09:40:31 AM UTC 24
Peak memory 230284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009716785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3009716785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_intr.1545087722
Short name T98
Test name
Test status
Simulation time 36858473 ps
CPU time 1.31 seconds
Started Sep 18 09:40:29 AM UTC 24
Finished Sep 18 09:40:31 AM UTC 24
Peak memory 226840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545087722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.1545087722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_smoke.3330585220
Short name T353
Test name
Test status
Simulation time 52992005 ps
CPU time 1.38 seconds
Started Sep 18 09:40:26 AM UTC 24
Finished Sep 18 09:40:29 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330585220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.3330585220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/11.edn_stress_all.1546171921
Short name T319
Test name
Test status
Simulation time 270459445 ps
CPU time 6.29 seconds
Started Sep 18 09:40:27 AM UTC 24
Finished Sep 18 09:40:35 AM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546171921 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1546171921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/110.edn_alert.3121939217
Short name T721
Test name
Test status
Simulation time 37438306 ps
CPU time 1.46 seconds
Started Sep 18 09:45:15 AM UTC 24
Finished Sep 18 09:45:17 AM UTC 24
Peak memory 231052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121939217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.3121939217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/110.edn_genbits.2176862059
Short name T720
Test name
Test status
Simulation time 47897641 ps
CPU time 1.43 seconds
Started Sep 18 09:45:14 AM UTC 24
Finished Sep 18 09:45:17 AM UTC 24
Peak memory 229184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176862059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2176862059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/111.edn_alert.2247812773
Short name T722
Test name
Test status
Simulation time 75844071 ps
CPU time 1.7 seconds
Started Sep 18 09:45:15 AM UTC 24
Finished Sep 18 09:45:18 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247812773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.2247812773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/111.edn_genbits.4074788210
Short name T727
Test name
Test status
Simulation time 410057857 ps
CPU time 5.09 seconds
Started Sep 18 09:45:15 AM UTC 24
Finished Sep 18 09:45:21 AM UTC 24
Peak memory 232164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074788210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4074788210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/112.edn_alert.1104947398
Short name T723
Test name
Test status
Simulation time 50408817 ps
CPU time 1.67 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:20 AM UTC 24
Peak memory 229000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104947398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.1104947398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/112.edn_genbits.723501267
Short name T709
Test name
Test status
Simulation time 96728809 ps
CPU time 1.57 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:20 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723501267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 112.edn_genbits.723501267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/113.edn_alert.3798894871
Short name T724
Test name
Test status
Simulation time 97633005 ps
CPU time 1.77 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:20 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798894871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.3798894871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/113.edn_genbits.401624835
Short name T655
Test name
Test status
Simulation time 23190120 ps
CPU time 1.47 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:20 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401624835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 113.edn_genbits.401624835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/114.edn_alert.1739251809
Short name T193
Test name
Test status
Simulation time 30852814 ps
CPU time 1.56 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:20 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739251809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.1739251809
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/114.edn_genbits.633826184
Short name T725
Test name
Test status
Simulation time 60064527 ps
CPU time 2.06 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:20 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633826184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 114.edn_genbits.633826184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/115.edn_alert.3459712046
Short name T730
Test name
Test status
Simulation time 29006717 ps
CPU time 1.89 seconds
Started Sep 18 09:45:18 AM UTC 24
Finished Sep 18 09:45:22 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459712046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.3459712046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/115.edn_genbits.3144712593
Short name T726
Test name
Test status
Simulation time 291132547 ps
CPU time 2.53 seconds
Started Sep 18 09:45:17 AM UTC 24
Finished Sep 18 09:45:21 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144712593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3144712593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/116.edn_alert.2026056496
Short name T728
Test name
Test status
Simulation time 35963600 ps
CPU time 1.49 seconds
Started Sep 18 09:45:18 AM UTC 24
Finished Sep 18 09:45:21 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026056496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.2026056496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/116.edn_genbits.2637418635
Short name T731
Test name
Test status
Simulation time 226073187 ps
CPU time 1.97 seconds
Started Sep 18 09:45:18 AM UTC 24
Finished Sep 18 09:45:22 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637418635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2637418635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/117.edn_genbits.1778223431
Short name T729
Test name
Test status
Simulation time 185180605 ps
CPU time 1.68 seconds
Started Sep 18 09:45:18 AM UTC 24
Finished Sep 18 09:45:22 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778223431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1778223431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/118.edn_alert.1704817796
Short name T285
Test name
Test status
Simulation time 285476942 ps
CPU time 1.51 seconds
Started Sep 18 09:45:20 AM UTC 24
Finished Sep 18 09:45:23 AM UTC 24
Peak memory 228992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704817796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.1704817796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/118.edn_genbits.2263952899
Short name T732
Test name
Test status
Simulation time 24917240 ps
CPU time 1.6 seconds
Started Sep 18 09:45:19 AM UTC 24
Finished Sep 18 09:45:22 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263952899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2263952899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/119.edn_alert.977248092
Short name T734
Test name
Test status
Simulation time 25669020 ps
CPU time 1.64 seconds
Started Sep 18 09:45:21 AM UTC 24
Finished Sep 18 09:45:24 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977248092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 119.edn_alert.977248092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/119.edn_genbits.2685331760
Short name T733
Test name
Test status
Simulation time 180021780 ps
CPU time 1.51 seconds
Started Sep 18 09:45:20 AM UTC 24
Finished Sep 18 09:45:24 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685331760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2685331760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_alert.2321475211
Short name T133
Test name
Test status
Simulation time 29063800 ps
CPU time 1.68 seconds
Started Sep 18 09:40:35 AM UTC 24
Finished Sep 18 09:40:38 AM UTC 24
Peak memory 228924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321475211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.2321475211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_alert_test.3847694155
Short name T358
Test name
Test status
Simulation time 17473477 ps
CPU time 1.18 seconds
Started Sep 18 09:40:38 AM UTC 24
Finished Sep 18 09:40:40 AM UTC 24
Peak memory 216900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847694155 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3847694155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_disable.91121090
Short name T70
Test name
Test status
Simulation time 96503880 ps
CPU time 1.39 seconds
Started Sep 18 09:40:35 AM UTC 24
Finished Sep 18 09:40:38 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91121090 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.91121090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.1997274313
Short name T172
Test name
Test status
Simulation time 84985044 ps
CPU time 1.49 seconds
Started Sep 18 09:40:36 AM UTC 24
Finished Sep 18 09:40:39 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997274313 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.1997274313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_err.2459099013
Short name T211
Test name
Test status
Simulation time 23647756 ps
CPU time 1.44 seconds
Started Sep 18 09:40:35 AM UTC 24
Finished Sep 18 09:40:38 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459099013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.2459099013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_genbits.3004817277
Short name T69
Test name
Test status
Simulation time 57395309 ps
CPU time 1.94 seconds
Started Sep 18 09:40:33 AM UTC 24
Finished Sep 18 09:40:36 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004817277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3004817277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_intr.3849008178
Short name T357
Test name
Test status
Simulation time 21985605 ps
CPU time 1.61 seconds
Started Sep 18 09:40:35 AM UTC 24
Finished Sep 18 09:40:38 AM UTC 24
Peak memory 226852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849008178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.3849008178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_smoke.448835408
Short name T354
Test name
Test status
Simulation time 15336735 ps
CPU time 1.36 seconds
Started Sep 18 09:40:32 AM UTC 24
Finished Sep 18 09:40:34 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448835408 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.edn_smoke.448835408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/12.edn_stress_all.108151301
Short name T335
Test name
Test status
Simulation time 630530734 ps
CPU time 5.7 seconds
Started Sep 18 09:40:33 AM UTC 24
Finished Sep 18 09:40:40 AM UTC 24
Peak memory 228168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108151301 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.108151301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/120.edn_alert.1971124236
Short name T735
Test name
Test status
Simulation time 90263077 ps
CPU time 1.65 seconds
Started Sep 18 09:45:21 AM UTC 24
Finished Sep 18 09:45:24 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971124236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.1971124236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/120.edn_genbits.1982917672
Short name T739
Test name
Test status
Simulation time 161495824 ps
CPU time 3.6 seconds
Started Sep 18 09:45:21 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 232140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982917672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1982917672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/121.edn_alert.3864707348
Short name T738
Test name
Test status
Simulation time 22510100 ps
CPU time 1.54 seconds
Started Sep 18 09:45:22 AM UTC 24
Finished Sep 18 09:45:24 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864707348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.3864707348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/121.edn_genbits.1730953691
Short name T736
Test name
Test status
Simulation time 51074304 ps
CPU time 1.4 seconds
Started Sep 18 09:45:22 AM UTC 24
Finished Sep 18 09:45:24 AM UTC 24
Peak memory 229312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730953691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1730953691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/122.edn_alert.888252744
Short name T741
Test name
Test status
Simulation time 28978713 ps
CPU time 1.84 seconds
Started Sep 18 09:45:23 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888252744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 122.edn_alert.888252744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/122.edn_genbits.2064206303
Short name T737
Test name
Test status
Simulation time 76163604 ps
CPU time 1.34 seconds
Started Sep 18 09:45:22 AM UTC 24
Finished Sep 18 09:45:24 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064206303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2064206303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/123.edn_alert.1171306193
Short name T258
Test name
Test status
Simulation time 77035077 ps
CPU time 1.8 seconds
Started Sep 18 09:45:23 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 228992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171306193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.1171306193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/123.edn_genbits.3434143661
Short name T744
Test name
Test status
Simulation time 102828609 ps
CPU time 2.16 seconds
Started Sep 18 09:45:23 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434143661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3434143661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/124.edn_alert.3633298233
Short name T740
Test name
Test status
Simulation time 65541992 ps
CPU time 1.57 seconds
Started Sep 18 09:45:23 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633298233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.3633298233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/124.edn_genbits.1282985780
Short name T742
Test name
Test status
Simulation time 57595251 ps
CPU time 1.92 seconds
Started Sep 18 09:45:23 AM UTC 24
Finished Sep 18 09:45:26 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282985780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1282985780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/125.edn_alert.374871073
Short name T747
Test name
Test status
Simulation time 77702473 ps
CPU time 1.54 seconds
Started Sep 18 09:45:25 AM UTC 24
Finished Sep 18 09:45:28 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374871073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 125.edn_alert.374871073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/126.edn_genbits.4282786133
Short name T755
Test name
Test status
Simulation time 188370621 ps
CPU time 3.36 seconds
Started Sep 18 09:45:25 AM UTC 24
Finished Sep 18 09:45:30 AM UTC 24
Peak memory 232092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282786133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4282786133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/127.edn_alert.2312740905
Short name T745
Test name
Test status
Simulation time 24133629 ps
CPU time 1.26 seconds
Started Sep 18 09:45:25 AM UTC 24
Finished Sep 18 09:45:28 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312740905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.2312740905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/127.edn_genbits.2481184040
Short name T746
Test name
Test status
Simulation time 63508794 ps
CPU time 1.35 seconds
Started Sep 18 09:45:25 AM UTC 24
Finished Sep 18 09:45:28 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481184040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2481184040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/128.edn_alert.1821968439
Short name T750
Test name
Test status
Simulation time 64429900 ps
CPU time 1.49 seconds
Started Sep 18 09:45:26 AM UTC 24
Finished Sep 18 09:45:28 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821968439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.1821968439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/128.edn_genbits.2397237494
Short name T748
Test name
Test status
Simulation time 128817519 ps
CPU time 1.52 seconds
Started Sep 18 09:45:25 AM UTC 24
Finished Sep 18 09:45:28 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397237494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2397237494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/129.edn_alert.3163455705
Short name T752
Test name
Test status
Simulation time 144472297 ps
CPU time 1.46 seconds
Started Sep 18 09:45:27 AM UTC 24
Finished Sep 18 09:45:29 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163455705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 129.edn_alert.3163455705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_alert_test.2721509691
Short name T360
Test name
Test status
Simulation time 69555614 ps
CPU time 1.15 seconds
Started Sep 18 09:40:42 AM UTC 24
Finished Sep 18 09:40:44 AM UTC 24
Peak memory 216460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721509691 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2721509691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_disable.1159347814
Short name T89
Test name
Test status
Simulation time 18017346 ps
CPU time 1.27 seconds
Started Sep 18 09:40:41 AM UTC 24
Finished Sep 18 09:40:43 AM UTC 24
Peak memory 216780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159347814 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1159347814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2003820254
Short name T361
Test name
Test status
Simulation time 45088654 ps
CPU time 1.86 seconds
Started Sep 18 09:40:42 AM UTC 24
Finished Sep 18 09:40:45 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003820254 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2003820254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_err.4040079797
Short name T186
Test name
Test status
Simulation time 39111598 ps
CPU time 1.63 seconds
Started Sep 18 09:40:41 AM UTC 24
Finished Sep 18 09:40:44 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040079797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.4040079797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_genbits.2344222076
Short name T334
Test name
Test status
Simulation time 20027217 ps
CPU time 1.16 seconds
Started Sep 18 09:40:39 AM UTC 24
Finished Sep 18 09:40:41 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344222076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2344222076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_intr.3907331210
Short name T136
Test name
Test status
Simulation time 34831172 ps
CPU time 1.23 seconds
Started Sep 18 09:40:40 AM UTC 24
Finished Sep 18 09:40:42 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907331210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.3907331210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_smoke.2609144066
Short name T359
Test name
Test status
Simulation time 15463544 ps
CPU time 1.46 seconds
Started Sep 18 09:40:39 AM UTC 24
Finished Sep 18 09:40:41 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609144066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.2609144066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_stress_all.1375680020
Short name T123
Test name
Test status
Simulation time 563914807 ps
CPU time 4.74 seconds
Started Sep 18 09:40:39 AM UTC 24
Finished Sep 18 09:40:44 AM UTC 24
Peak memory 230084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375680020 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1375680020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.1507466502
Short name T453
Test name
Test status
Simulation time 4381048730 ps
CPU time 94.68 seconds
Started Sep 18 09:40:39 AM UTC 24
Finished Sep 18 09:42:15 AM UTC 24
Peak memory 230360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1507466502 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all
_with_rand_reset.1507466502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/130.edn_alert.747730456
Short name T754
Test name
Test status
Simulation time 26348784 ps
CPU time 1.55 seconds
Started Sep 18 09:45:27 AM UTC 24
Finished Sep 18 09:45:29 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747730456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 130.edn_alert.747730456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/130.edn_genbits.1003047872
Short name T753
Test name
Test status
Simulation time 57792669 ps
CPU time 1.41 seconds
Started Sep 18 09:45:27 AM UTC 24
Finished Sep 18 09:45:29 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003047872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1003047872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/131.edn_genbits.375337162
Short name T751
Test name
Test status
Simulation time 33463499 ps
CPU time 1.33 seconds
Started Sep 18 09:45:27 AM UTC 24
Finished Sep 18 09:45:29 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375337162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 131.edn_genbits.375337162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/132.edn_alert.494656455
Short name T757
Test name
Test status
Simulation time 29964697 ps
CPU time 1.3 seconds
Started Sep 18 09:45:29 AM UTC 24
Finished Sep 18 09:45:31 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494656455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 132.edn_alert.494656455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/132.edn_genbits.1464768009
Short name T756
Test name
Test status
Simulation time 39739912 ps
CPU time 1.24 seconds
Started Sep 18 09:45:28 AM UTC 24
Finished Sep 18 09:45:31 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464768009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1464768009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/133.edn_alert.638549161
Short name T759
Test name
Test status
Simulation time 81797606 ps
CPU time 1.61 seconds
Started Sep 18 09:45:29 AM UTC 24
Finished Sep 18 09:45:32 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638549161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 133.edn_alert.638549161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/134.edn_genbits.823221449
Short name T761
Test name
Test status
Simulation time 30716076 ps
CPU time 1.7 seconds
Started Sep 18 09:45:29 AM UTC 24
Finished Sep 18 09:45:32 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823221449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 134.edn_genbits.823221449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/135.edn_alert.2427762266
Short name T762
Test name
Test status
Simulation time 80228120 ps
CPU time 1.25 seconds
Started Sep 18 09:45:30 AM UTC 24
Finished Sep 18 09:45:32 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427762266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.2427762266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/135.edn_genbits.1602116037
Short name T758
Test name
Test status
Simulation time 68221186 ps
CPU time 1.33 seconds
Started Sep 18 09:45:29 AM UTC 24
Finished Sep 18 09:45:31 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602116037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1602116037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/136.edn_alert.17688320
Short name T764
Test name
Test status
Simulation time 92904268 ps
CPU time 1.61 seconds
Started Sep 18 09:45:30 AM UTC 24
Finished Sep 18 09:45:33 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17688320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 136.edn_alert.17688320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/136.edn_genbits.564024510
Short name T765
Test name
Test status
Simulation time 36987607 ps
CPU time 1.76 seconds
Started Sep 18 09:45:30 AM UTC 24
Finished Sep 18 09:45:33 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564024510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 136.edn_genbits.564024510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/137.edn_alert.3873885107
Short name T766
Test name
Test status
Simulation time 32225793 ps
CPU time 1.61 seconds
Started Sep 18 09:45:30 AM UTC 24
Finished Sep 18 09:45:33 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873885107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.3873885107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/137.edn_genbits.4163746663
Short name T763
Test name
Test status
Simulation time 78443405 ps
CPU time 1.56 seconds
Started Sep 18 09:45:30 AM UTC 24
Finished Sep 18 09:45:33 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163746663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4163746663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/138.edn_alert.3057571161
Short name T767
Test name
Test status
Simulation time 64021030 ps
CPU time 1.28 seconds
Started Sep 18 09:45:31 AM UTC 24
Finished Sep 18 09:45:34 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057571161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.3057571161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/138.edn_genbits.3102021488
Short name T768
Test name
Test status
Simulation time 85966963 ps
CPU time 1.81 seconds
Started Sep 18 09:45:31 AM UTC 24
Finished Sep 18 09:45:34 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102021488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3102021488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/139.edn_alert.1479503419
Short name T771
Test name
Test status
Simulation time 38936024 ps
CPU time 1.5 seconds
Started Sep 18 09:45:33 AM UTC 24
Finished Sep 18 09:45:35 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479503419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.1479503419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/139.edn_genbits.452976365
Short name T769
Test name
Test status
Simulation time 41107149 ps
CPU time 2.14 seconds
Started Sep 18 09:45:32 AM UTC 24
Finished Sep 18 09:45:35 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452976365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 139.edn_genbits.452976365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_alert.1533999157
Short name T146
Test name
Test status
Simulation time 78225054 ps
CPU time 1.72 seconds
Started Sep 18 09:40:46 AM UTC 24
Finished Sep 18 09:40:48 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533999157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.1533999157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_alert_test.3480474807
Short name T366
Test name
Test status
Simulation time 24492418 ps
CPU time 1.28 seconds
Started Sep 18 09:40:47 AM UTC 24
Finished Sep 18 09:40:49 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480474807 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3480474807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_disable.3673879872
Short name T81
Test name
Test status
Simulation time 26775991 ps
CPU time 1.07 seconds
Started Sep 18 09:40:46 AM UTC 24
Finished Sep 18 09:40:48 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673879872 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3673879872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.519937994
Short name T76
Test name
Test status
Simulation time 128088911 ps
CPU time 1.26 seconds
Started Sep 18 09:40:46 AM UTC 24
Finished Sep 18 09:40:48 AM UTC 24
Peak memory 227100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519937994 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.519937994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_err.3830849483
Short name T364
Test name
Test status
Simulation time 40900884 ps
CPU time 1.49 seconds
Started Sep 18 09:40:46 AM UTC 24
Finished Sep 18 09:40:48 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830849483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.3830849483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_genbits.552112723
Short name T363
Test name
Test status
Simulation time 126121197 ps
CPU time 1.64 seconds
Started Sep 18 09:40:43 AM UTC 24
Finished Sep 18 09:40:46 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552112723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_genbits.552112723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_intr.417132286
Short name T32
Test name
Test status
Simulation time 32416539 ps
CPU time 1.24 seconds
Started Sep 18 09:40:44 AM UTC 24
Finished Sep 18 09:40:47 AM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417132286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.417132286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_smoke.4078870987
Short name T362
Test name
Test status
Simulation time 27775112 ps
CPU time 1.09 seconds
Started Sep 18 09:40:43 AM UTC 24
Finished Sep 18 09:40:45 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078870987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.4078870987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_stress_all.651086688
Short name T307
Test name
Test status
Simulation time 64359836 ps
CPU time 1.99 seconds
Started Sep 18 09:40:44 AM UTC 24
Finished Sep 18 09:40:47 AM UTC 24
Peak memory 228944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651086688 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.651086688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.703713123
Short name T415
Test name
Test status
Simulation time 3378095540 ps
CPU time 48.65 seconds
Started Sep 18 09:40:44 AM UTC 24
Finished Sep 18 09:41:35 AM UTC 24
Peak memory 232092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=703713123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_
with_rand_reset.703713123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/140.edn_alert.670986689
Short name T772
Test name
Test status
Simulation time 22301751 ps
CPU time 1.71 seconds
Started Sep 18 09:45:33 AM UTC 24
Finished Sep 18 09:45:35 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670986689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 140.edn_alert.670986689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/140.edn_genbits.2746834464
Short name T770
Test name
Test status
Simulation time 76170849 ps
CPU time 1.36 seconds
Started Sep 18 09:45:33 AM UTC 24
Finished Sep 18 09:45:35 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746834464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2746834464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/141.edn_alert.4274731774
Short name T773
Test name
Test status
Simulation time 31809416 ps
CPU time 1.68 seconds
Started Sep 18 09:45:33 AM UTC 24
Finished Sep 18 09:45:35 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274731774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 141.edn_alert.4274731774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/141.edn_genbits.2436877724
Short name T775
Test name
Test status
Simulation time 33123247 ps
CPU time 2.13 seconds
Started Sep 18 09:45:33 AM UTC 24
Finished Sep 18 09:45:36 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436877724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2436877724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/142.edn_alert.1959392447
Short name T779
Test name
Test status
Simulation time 30249268 ps
CPU time 1.69 seconds
Started Sep 18 09:45:34 AM UTC 24
Finished Sep 18 09:45:37 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959392447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.1959392447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/142.edn_genbits.1012094794
Short name T774
Test name
Test status
Simulation time 61482256 ps
CPU time 1.68 seconds
Started Sep 18 09:45:33 AM UTC 24
Finished Sep 18 09:45:35 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012094794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1012094794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/143.edn_alert.1965455187
Short name T777
Test name
Test status
Simulation time 77977059 ps
CPU time 1.57 seconds
Started Sep 18 09:45:34 AM UTC 24
Finished Sep 18 09:45:37 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965455187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.1965455187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/143.edn_genbits.209037211
Short name T778
Test name
Test status
Simulation time 67630775 ps
CPU time 1.52 seconds
Started Sep 18 09:45:34 AM UTC 24
Finished Sep 18 09:45:37 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209037211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 143.edn_genbits.209037211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/144.edn_alert.2570464364
Short name T776
Test name
Test status
Simulation time 66968483 ps
CPU time 1.34 seconds
Started Sep 18 09:45:34 AM UTC 24
Finished Sep 18 09:45:36 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570464364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.2570464364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/144.edn_genbits.201786515
Short name T780
Test name
Test status
Simulation time 42004687 ps
CPU time 1.97 seconds
Started Sep 18 09:45:34 AM UTC 24
Finished Sep 18 09:45:37 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201786515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 144.edn_genbits.201786515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/145.edn_alert.658022291
Short name T782
Test name
Test status
Simulation time 27216491 ps
CPU time 1.61 seconds
Started Sep 18 09:45:35 AM UTC 24
Finished Sep 18 09:45:38 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658022291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 145.edn_alert.658022291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/145.edn_genbits.2493109650
Short name T783
Test name
Test status
Simulation time 41973595 ps
CPU time 1.87 seconds
Started Sep 18 09:45:35 AM UTC 24
Finished Sep 18 09:45:38 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493109650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2493109650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/146.edn_alert.3790268179
Short name T286
Test name
Test status
Simulation time 76795297 ps
CPU time 1.63 seconds
Started Sep 18 09:45:36 AM UTC 24
Finished Sep 18 09:45:39 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790268179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.3790268179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/146.edn_genbits.703159380
Short name T789
Test name
Test status
Simulation time 135628317 ps
CPU time 3.67 seconds
Started Sep 18 09:45:35 AM UTC 24
Finished Sep 18 09:45:40 AM UTC 24
Peak memory 232096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703159380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 146.edn_genbits.703159380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/147.edn_genbits.3844254140
Short name T787
Test name
Test status
Simulation time 42187696 ps
CPU time 1.81 seconds
Started Sep 18 09:45:36 AM UTC 24
Finished Sep 18 09:45:39 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844254140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3844254140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/148.edn_alert.2915293095
Short name T786
Test name
Test status
Simulation time 27518478 ps
CPU time 1.5 seconds
Started Sep 18 09:45:36 AM UTC 24
Finished Sep 18 09:45:39 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915293095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.2915293095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/148.edn_genbits.2001395211
Short name T784
Test name
Test status
Simulation time 86877730 ps
CPU time 1.39 seconds
Started Sep 18 09:45:36 AM UTC 24
Finished Sep 18 09:45:39 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001395211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2001395211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/149.edn_alert.3920484643
Short name T790
Test name
Test status
Simulation time 73861700 ps
CPU time 1.42 seconds
Started Sep 18 09:45:38 AM UTC 24
Finished Sep 18 09:45:40 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920484643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.3920484643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/149.edn_genbits.2574516049
Short name T788
Test name
Test status
Simulation time 92535602 ps
CPU time 1.77 seconds
Started Sep 18 09:45:37 AM UTC 24
Finished Sep 18 09:45:39 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574516049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2574516049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_alert_test.1719039543
Short name T369
Test name
Test status
Simulation time 112074702 ps
CPU time 1.15 seconds
Started Sep 18 09:40:50 AM UTC 24
Finished Sep 18 09:40:53 AM UTC 24
Peak memory 227180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719039543 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1719039543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_disable.3985082907
Short name T90
Test name
Test status
Simulation time 38817474 ps
CPU time 1.16 seconds
Started Sep 18 09:40:49 AM UTC 24
Finished Sep 18 09:40:51 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985082907 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3985082907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.1314865707
Short name T99
Test name
Test status
Simulation time 71127391 ps
CPU time 1.37 seconds
Started Sep 18 09:40:50 AM UTC 24
Finished Sep 18 09:40:53 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314865707 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.1314865707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_err.643516917
Short name T368
Test name
Test status
Simulation time 39053562 ps
CPU time 1.77 seconds
Started Sep 18 09:40:49 AM UTC 24
Finished Sep 18 09:40:52 AM UTC 24
Peak memory 242780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643516917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.edn_err.643516917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_genbits.2905857604
Short name T294
Test name
Test status
Simulation time 44377080 ps
CPU time 1.54 seconds
Started Sep 18 09:40:47 AM UTC 24
Finished Sep 18 09:40:49 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905857604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2905857604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_intr.2069741382
Short name T367
Test name
Test status
Simulation time 20660326 ps
CPU time 1.61 seconds
Started Sep 18 09:40:48 AM UTC 24
Finished Sep 18 09:40:51 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069741382 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.2069741382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_smoke.2984924852
Short name T365
Test name
Test status
Simulation time 31505118 ps
CPU time 1.21 seconds
Started Sep 18 09:40:47 AM UTC 24
Finished Sep 18 09:40:49 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984924852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.2984924852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_stress_all.3917870794
Short name T373
Test name
Test status
Simulation time 287661296 ps
CPU time 8.24 seconds
Started Sep 18 09:40:48 AM UTC 24
Finished Sep 18 09:40:57 AM UTC 24
Peak memory 230084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917870794 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3917870794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.4291011542
Short name T246
Test name
Test status
Simulation time 3943173127 ps
CPU time 106.83 seconds
Started Sep 18 09:40:48 AM UTC 24
Finished Sep 18 09:42:37 AM UTC 24
Peak memory 230300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4291011542 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all
_with_rand_reset.4291011542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/150.edn_alert.2089917101
Short name T287
Test name
Test status
Simulation time 77629135 ps
CPU time 1.63 seconds
Started Sep 18 09:45:38 AM UTC 24
Finished Sep 18 09:45:41 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089917101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.2089917101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/150.edn_genbits.1209200828
Short name T793
Test name
Test status
Simulation time 58769078 ps
CPU time 2.04 seconds
Started Sep 18 09:45:38 AM UTC 24
Finished Sep 18 09:45:41 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209200828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1209200828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/151.edn_alert.1379028180
Short name T792
Test name
Test status
Simulation time 84477582 ps
CPU time 1.6 seconds
Started Sep 18 09:45:38 AM UTC 24
Finished Sep 18 09:45:41 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379028180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.1379028180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/151.edn_genbits.3831659152
Short name T791
Test name
Test status
Simulation time 84138071 ps
CPU time 1.39 seconds
Started Sep 18 09:45:38 AM UTC 24
Finished Sep 18 09:45:40 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831659152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3831659152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/152.edn_alert.4094404871
Short name T794
Test name
Test status
Simulation time 83676671 ps
CPU time 1.68 seconds
Started Sep 18 09:45:39 AM UTC 24
Finished Sep 18 09:45:42 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094404871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.4094404871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/152.edn_genbits.133199784
Short name T796
Test name
Test status
Simulation time 66243767 ps
CPU time 2.22 seconds
Started Sep 18 09:45:39 AM UTC 24
Finished Sep 18 09:45:42 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133199784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 152.edn_genbits.133199784
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/153.edn_alert.199452509
Short name T797
Test name
Test status
Simulation time 83025286 ps
CPU time 1.52 seconds
Started Sep 18 09:45:40 AM UTC 24
Finished Sep 18 09:45:43 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199452509 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 153.edn_alert.199452509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/153.edn_genbits.3393138267
Short name T795
Test name
Test status
Simulation time 63615646 ps
CPU time 1.75 seconds
Started Sep 18 09:45:39 AM UTC 24
Finished Sep 18 09:45:42 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393138267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3393138267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/154.edn_alert.4100167198
Short name T798
Test name
Test status
Simulation time 70071897 ps
CPU time 1.72 seconds
Started Sep 18 09:45:40 AM UTC 24
Finished Sep 18 09:45:43 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100167198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 154.edn_alert.4100167198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/154.edn_genbits.1316244077
Short name T800
Test name
Test status
Simulation time 29635784 ps
CPU time 1.9 seconds
Started Sep 18 09:45:40 AM UTC 24
Finished Sep 18 09:45:43 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316244077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1316244077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/155.edn_alert.859852420
Short name T288
Test name
Test status
Simulation time 140768617 ps
CPU time 1.53 seconds
Started Sep 18 09:45:40 AM UTC 24
Finished Sep 18 09:45:43 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859852420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 155.edn_alert.859852420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/155.edn_genbits.1202269950
Short name T802
Test name
Test status
Simulation time 46926383 ps
CPU time 2.27 seconds
Started Sep 18 09:45:40 AM UTC 24
Finished Sep 18 09:45:44 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202269950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1202269950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/156.edn_alert.2296656704
Short name T803
Test name
Test status
Simulation time 24711669 ps
CPU time 1.56 seconds
Started Sep 18 09:45:41 AM UTC 24
Finished Sep 18 09:45:44 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296656704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.2296656704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/156.edn_genbits.1348022162
Short name T801
Test name
Test status
Simulation time 36016612 ps
CPU time 1.78 seconds
Started Sep 18 09:45:40 AM UTC 24
Finished Sep 18 09:45:43 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348022162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1348022162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/157.edn_alert.2445915564
Short name T289
Test name
Test status
Simulation time 43860977 ps
CPU time 1.82 seconds
Started Sep 18 09:45:41 AM UTC 24
Finished Sep 18 09:45:44 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445915564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.2445915564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/157.edn_genbits.3308689589
Short name T805
Test name
Test status
Simulation time 43299324 ps
CPU time 1.76 seconds
Started Sep 18 09:45:41 AM UTC 24
Finished Sep 18 09:45:44 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308689589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3308689589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/158.edn_alert.3374653613
Short name T259
Test name
Test status
Simulation time 48603659 ps
CPU time 1.61 seconds
Started Sep 18 09:45:42 AM UTC 24
Finished Sep 18 09:45:44 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374653613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.3374653613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/158.edn_genbits.223440534
Short name T806
Test name
Test status
Simulation time 45876471 ps
CPU time 1.99 seconds
Started Sep 18 09:45:42 AM UTC 24
Finished Sep 18 09:45:45 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223440534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 158.edn_genbits.223440534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/159.edn_alert.823244597
Short name T807
Test name
Test status
Simulation time 44365143 ps
CPU time 1.62 seconds
Started Sep 18 09:45:43 AM UTC 24
Finished Sep 18 09:45:45 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823244597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 159.edn_alert.823244597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/159.edn_genbits.3548834268
Short name T804
Test name
Test status
Simulation time 174863446 ps
CPU time 1.47 seconds
Started Sep 18 09:45:42 AM UTC 24
Finished Sep 18 09:45:44 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548834268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3548834268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_alert.2239876899
Short name T91
Test name
Test status
Simulation time 150512632 ps
CPU time 1.49 seconds
Started Sep 18 09:40:54 AM UTC 24
Finished Sep 18 09:40:56 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239876899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.2239876899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_alert_test.1342200176
Short name T375
Test name
Test status
Simulation time 55728786 ps
CPU time 1.49 seconds
Started Sep 18 09:40:56 AM UTC 24
Finished Sep 18 09:40:58 AM UTC 24
Peak memory 216944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342200176 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1342200176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.3377010167
Short name T230
Test name
Test status
Simulation time 208639357 ps
CPU time 1.46 seconds
Started Sep 18 09:40:55 AM UTC 24
Finished Sep 18 09:40:57 AM UTC 24
Peak memory 231000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377010167 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.3377010167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_err.1804838240
Short name T213
Test name
Test status
Simulation time 34311137 ps
CPU time 1.64 seconds
Started Sep 18 09:40:54 AM UTC 24
Finished Sep 18 09:40:56 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804838240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.1804838240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_genbits.2613299407
Short name T77
Test name
Test status
Simulation time 82370549 ps
CPU time 1.53 seconds
Started Sep 18 09:40:52 AM UTC 24
Finished Sep 18 09:40:54 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613299407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2613299407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_intr.2155437317
Short name T371
Test name
Test status
Simulation time 83738126 ps
CPU time 1.28 seconds
Started Sep 18 09:40:53 AM UTC 24
Finished Sep 18 09:40:55 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155437317 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.2155437317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_smoke.261924138
Short name T370
Test name
Test status
Simulation time 19719636 ps
CPU time 1.54 seconds
Started Sep 18 09:40:50 AM UTC 24
Finished Sep 18 09:40:53 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261924138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.edn_smoke.261924138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_stress_all.2795266211
Short name T372
Test name
Test status
Simulation time 85339426 ps
CPU time 3.35 seconds
Started Sep 18 09:40:53 AM UTC 24
Finished Sep 18 09:40:57 AM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795266211 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2795266211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/16.edn_stress_all_with_rand_reset.2471518811
Short name T418
Test name
Test status
Simulation time 1279358518 ps
CPU time 42.8 seconds
Started Sep 18 09:40:53 AM UTC 24
Finished Sep 18 09:41:37 AM UTC 24
Peak memory 230280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2471518811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all
_with_rand_reset.2471518811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/16.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/160.edn_alert.2844918049
Short name T808
Test name
Test status
Simulation time 93639185 ps
CPU time 1.67 seconds
Started Sep 18 09:45:43 AM UTC 24
Finished Sep 18 09:45:45 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844918049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.2844918049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/161.edn_alert.2243562338
Short name T809
Test name
Test status
Simulation time 229075954 ps
CPU time 1.27 seconds
Started Sep 18 09:45:44 AM UTC 24
Finished Sep 18 09:45:46 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243562338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.2243562338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/161.edn_genbits.484090013
Short name T824
Test name
Test status
Simulation time 208717548 ps
CPU time 4.52 seconds
Started Sep 18 09:45:44 AM UTC 24
Finished Sep 18 09:45:49 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484090013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.edn_genbits.484090013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/162.edn_alert.20638907
Short name T799
Test name
Test status
Simulation time 149662921 ps
CPU time 1.74 seconds
Started Sep 18 09:45:44 AM UTC 24
Finished Sep 18 09:45:47 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20638907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 162.edn_alert.20638907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/162.edn_genbits.3946958954
Short name T810
Test name
Test status
Simulation time 39587337 ps
CPU time 1.75 seconds
Started Sep 18 09:45:44 AM UTC 24
Finished Sep 18 09:45:47 AM UTC 24
Peak memory 229212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946958954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3946958954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/163.edn_alert.2400197960
Short name T812
Test name
Test status
Simulation time 26169392 ps
CPU time 1.43 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:48 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400197960 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.2400197960
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/163.edn_genbits.3681153442
Short name T811
Test name
Test status
Simulation time 35491449 ps
CPU time 1.88 seconds
Started Sep 18 09:45:44 AM UTC 24
Finished Sep 18 09:45:47 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681153442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3681153442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/164.edn_alert.1293190053
Short name T813
Test name
Test status
Simulation time 47017763 ps
CPU time 1.61 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:48 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293190053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.1293190053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/164.edn_genbits.1611113588
Short name T814
Test name
Test status
Simulation time 87404015 ps
CPU time 1.66 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:48 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611113588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1611113588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/165.edn_alert.884557111
Short name T817
Test name
Test status
Simulation time 153580408 ps
CPU time 1.96 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:48 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884557111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 165.edn_alert.884557111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/165.edn_genbits.1169444927
Short name T820
Test name
Test status
Simulation time 239377636 ps
CPU time 2.66 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:49 AM UTC 24
Peak memory 230188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169444927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1169444927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/166.edn_alert.2219313108
Short name T819
Test name
Test status
Simulation time 149730961 ps
CPU time 1.92 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:48 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219313108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.2219313108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/166.edn_genbits.3111362197
Short name T815
Test name
Test status
Simulation time 52074844 ps
CPU time 1.55 seconds
Started Sep 18 09:45:45 AM UTC 24
Finished Sep 18 09:45:48 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111362197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3111362197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/167.edn_alert.1342864367
Short name T823
Test name
Test status
Simulation time 88945028 ps
CPU time 1.79 seconds
Started Sep 18 09:45:47 AM UTC 24
Finished Sep 18 09:45:49 AM UTC 24
Peak memory 230944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342864367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.1342864367
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/167.edn_genbits.1787215653
Short name T821
Test name
Test status
Simulation time 84660747 ps
CPU time 1.5 seconds
Started Sep 18 09:45:47 AM UTC 24
Finished Sep 18 09:45:49 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787215653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1787215653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/168.edn_alert.353742807
Short name T822
Test name
Test status
Simulation time 103705271 ps
CPU time 1.66 seconds
Started Sep 18 09:45:47 AM UTC 24
Finished Sep 18 09:45:49 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353742807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 168.edn_alert.353742807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/168.edn_genbits.231217406
Short name T827
Test name
Test status
Simulation time 92124323 ps
CPU time 3.75 seconds
Started Sep 18 09:45:47 AM UTC 24
Finished Sep 18 09:45:51 AM UTC 24
Peak memory 232160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231217406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 168.edn_genbits.231217406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/169.edn_alert.655475083
Short name T825
Test name
Test status
Simulation time 42553239 ps
CPU time 1.47 seconds
Started Sep 18 09:45:48 AM UTC 24
Finished Sep 18 09:45:51 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655475083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 169.edn_alert.655475083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/169.edn_genbits.262915994
Short name T834
Test name
Test status
Simulation time 215948951 ps
CPU time 3.69 seconds
Started Sep 18 09:45:48 AM UTC 24
Finished Sep 18 09:45:53 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262915994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.edn_genbits.262915994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_alert.3585963299
Short name T376
Test name
Test status
Simulation time 40853262 ps
CPU time 1.7 seconds
Started Sep 18 09:40:58 AM UTC 24
Finished Sep 18 09:41:01 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585963299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.3585963299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_alert_test.2427617493
Short name T377
Test name
Test status
Simulation time 13514501 ps
CPU time 1.28 seconds
Started Sep 18 09:41:00 AM UTC 24
Finished Sep 18 09:41:02 AM UTC 24
Peak memory 217068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427617493 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2427617493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_disable.3372967719
Short name T228
Test name
Test status
Simulation time 46157761 ps
CPU time 1.2 seconds
Started Sep 18 09:40:59 AM UTC 24
Finished Sep 18 09:41:01 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372967719 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3372967719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.2008780548
Short name T378
Test name
Test status
Simulation time 71263531 ps
CPU time 1.65 seconds
Started Sep 18 09:41:00 AM UTC 24
Finished Sep 18 09:41:02 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008780548 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.2008780548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_err.992084138
Short name T179
Test name
Test status
Simulation time 24201687 ps
CPU time 1.4 seconds
Started Sep 18 09:40:59 AM UTC 24
Finished Sep 18 09:41:01 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992084138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.edn_err.992084138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_genbits.3332332232
Short name T92
Test name
Test status
Simulation time 44548484 ps
CPU time 1.72 seconds
Started Sep 18 09:40:57 AM UTC 24
Finished Sep 18 09:41:00 AM UTC 24
Peak memory 226960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332332232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3332332232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_smoke.3482635358
Short name T374
Test name
Test status
Simulation time 43537611 ps
CPU time 1.19 seconds
Started Sep 18 09:40:56 AM UTC 24
Finished Sep 18 09:40:58 AM UTC 24
Peak memory 216612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482635358 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.3482635358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/17.edn_stress_all.2626424317
Short name T380
Test name
Test status
Simulation time 986143992 ps
CPU time 5.94 seconds
Started Sep 18 09:40:57 AM UTC 24
Finished Sep 18 09:41:04 AM UTC 24
Peak memory 228164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626424317 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2626424317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/170.edn_alert.4017510334
Short name T828
Test name
Test status
Simulation time 22791027 ps
CPU time 1.62 seconds
Started Sep 18 09:45:49 AM UTC 24
Finished Sep 18 09:45:52 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017510334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.4017510334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/170.edn_genbits.1782526734
Short name T826
Test name
Test status
Simulation time 87325097 ps
CPU time 1.77 seconds
Started Sep 18 09:45:48 AM UTC 24
Finished Sep 18 09:45:51 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782526734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1782526734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/171.edn_alert.1356019928
Short name T831
Test name
Test status
Simulation time 50159458 ps
CPU time 1.92 seconds
Started Sep 18 09:45:49 AM UTC 24
Finished Sep 18 09:45:52 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356019928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.1356019928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/171.edn_genbits.819096114
Short name T832
Test name
Test status
Simulation time 36278444 ps
CPU time 2.16 seconds
Started Sep 18 09:45:49 AM UTC 24
Finished Sep 18 09:45:52 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819096114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 171.edn_genbits.819096114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/172.edn_alert.3388019334
Short name T830
Test name
Test status
Simulation time 38659524 ps
CPU time 1.73 seconds
Started Sep 18 09:45:49 AM UTC 24
Finished Sep 18 09:45:52 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388019334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.3388019334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/172.edn_genbits.144114854
Short name T829
Test name
Test status
Simulation time 47476482 ps
CPU time 1.67 seconds
Started Sep 18 09:45:49 AM UTC 24
Finished Sep 18 09:45:52 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144114854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 172.edn_genbits.144114854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/173.edn_alert.2770639667
Short name T836
Test name
Test status
Simulation time 35157419 ps
CPU time 1.6 seconds
Started Sep 18 09:45:50 AM UTC 24
Finished Sep 18 09:45:53 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770639667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.2770639667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/173.edn_genbits.275657777
Short name T833
Test name
Test status
Simulation time 54580293 ps
CPU time 1.92 seconds
Started Sep 18 09:45:49 AM UTC 24
Finished Sep 18 09:45:52 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275657777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 173.edn_genbits.275657777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/174.edn_alert.780836182
Short name T837
Test name
Test status
Simulation time 43516502 ps
CPU time 1.58 seconds
Started Sep 18 09:45:50 AM UTC 24
Finished Sep 18 09:45:54 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780836182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 174.edn_alert.780836182
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/174.edn_genbits.1913522333
Short name T841
Test name
Test status
Simulation time 108011683 ps
CPU time 3.19 seconds
Started Sep 18 09:45:50 AM UTC 24
Finished Sep 18 09:45:55 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913522333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1913522333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/175.edn_alert.2693168623
Short name T838
Test name
Test status
Simulation time 30008181 ps
CPU time 1.5 seconds
Started Sep 18 09:45:51 AM UTC 24
Finished Sep 18 09:45:54 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693168623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.2693168623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/175.edn_genbits.725520787
Short name T835
Test name
Test status
Simulation time 20099829 ps
CPU time 1.46 seconds
Started Sep 18 09:45:50 AM UTC 24
Finished Sep 18 09:45:53 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725520787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 175.edn_genbits.725520787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/176.edn_alert.646733003
Short name T840
Test name
Test status
Simulation time 25343651 ps
CPU time 1.58 seconds
Started Sep 18 09:45:52 AM UTC 24
Finished Sep 18 09:45:54 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646733003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 176.edn_alert.646733003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/176.edn_genbits.2299289099
Short name T839
Test name
Test status
Simulation time 81873761 ps
CPU time 1.54 seconds
Started Sep 18 09:45:52 AM UTC 24
Finished Sep 18 09:45:54 AM UTC 24
Peak memory 228912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299289099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2299289099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/177.edn_alert.2916818861
Short name T842
Test name
Test status
Simulation time 76033016 ps
CPU time 1.45 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:55 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916818861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 177.edn_alert.2916818861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/177.edn_genbits.1713275782
Short name T848
Test name
Test status
Simulation time 50818062 ps
CPU time 2.43 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:56 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713275782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1713275782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/178.edn_alert.3126164526
Short name T847
Test name
Test status
Simulation time 201927447 ps
CPU time 1.87 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:56 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126164526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.3126164526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/178.edn_genbits.693628855
Short name T843
Test name
Test status
Simulation time 27426558 ps
CPU time 1.61 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:56 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693628855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 178.edn_genbits.693628855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/179.edn_alert.792630336
Short name T846
Test name
Test status
Simulation time 33225849 ps
CPU time 1.71 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:56 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792630336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 179.edn_alert.792630336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/179.edn_genbits.1138477945
Short name T845
Test name
Test status
Simulation time 25155303 ps
CPU time 1.76 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:56 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138477945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1138477945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_alert.3830657586
Short name T184
Test name
Test status
Simulation time 71378891 ps
CPU time 1.36 seconds
Started Sep 18 09:41:03 AM UTC 24
Finished Sep 18 09:41:05 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830657586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.3830657586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_alert_test.1164489928
Short name T385
Test name
Test status
Simulation time 35375432 ps
CPU time 1.13 seconds
Started Sep 18 09:41:05 AM UTC 24
Finished Sep 18 09:41:07 AM UTC 24
Peak memory 227712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164489928 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1164489928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_disable.50908149
Short name T383
Test name
Test status
Simulation time 14120472 ps
CPU time 1.39 seconds
Started Sep 18 09:41:04 AM UTC 24
Finished Sep 18 09:41:07 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50908149 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.50908149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.2557404986
Short name T384
Test name
Test status
Simulation time 73620219 ps
CPU time 1.35 seconds
Started Sep 18 09:41:04 AM UTC 24
Finished Sep 18 09:41:07 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557404986 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.2557404986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_err.3431164524
Short name T382
Test name
Test status
Simulation time 18755297 ps
CPU time 1.48 seconds
Started Sep 18 09:41:03 AM UTC 24
Finished Sep 18 09:41:06 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431164524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.3431164524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_genbits.1459974976
Short name T11
Test name
Test status
Simulation time 63809607 ps
CPU time 1.67 seconds
Started Sep 18 09:41:02 AM UTC 24
Finished Sep 18 09:41:04 AM UTC 24
Peak memory 231252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459974976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1459974976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_intr.2507227204
Short name T381
Test name
Test status
Simulation time 48501455 ps
CPU time 1.38 seconds
Started Sep 18 09:41:02 AM UTC 24
Finished Sep 18 09:41:04 AM UTC 24
Peak memory 237172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507227204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.2507227204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_smoke.3020711892
Short name T379
Test name
Test status
Simulation time 77469113 ps
CPU time 1.41 seconds
Started Sep 18 09:41:01 AM UTC 24
Finished Sep 18 09:41:03 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020711892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.3020711892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/18.edn_stress_all.200091274
Short name T252
Test name
Test status
Simulation time 349006262 ps
CPU time 3.87 seconds
Started Sep 18 09:41:02 AM UTC 24
Finished Sep 18 09:41:07 AM UTC 24
Peak memory 232276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200091274 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.200091274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/180.edn_alert.4089417933
Short name T849
Test name
Test status
Simulation time 46366391 ps
CPU time 1.55 seconds
Started Sep 18 09:45:54 AM UTC 24
Finished Sep 18 09:45:57 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089417933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.edn_alert.4089417933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/180.edn_genbits.2360382973
Short name T844
Test name
Test status
Simulation time 78879603 ps
CPU time 1.6 seconds
Started Sep 18 09:45:53 AM UTC 24
Finished Sep 18 09:45:56 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360382973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2360382973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/181.edn_alert.910888716
Short name T851
Test name
Test status
Simulation time 25077744 ps
CPU time 1.6 seconds
Started Sep 18 09:45:54 AM UTC 24
Finished Sep 18 09:45:57 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910888716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 181.edn_alert.910888716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/181.edn_genbits.1177140244
Short name T850
Test name
Test status
Simulation time 45619834 ps
CPU time 1.61 seconds
Started Sep 18 09:45:54 AM UTC 24
Finished Sep 18 09:45:57 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177140244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1177140244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/182.edn_alert.1380035110
Short name T852
Test name
Test status
Simulation time 101473628 ps
CPU time 1.46 seconds
Started Sep 18 09:45:54 AM UTC 24
Finished Sep 18 09:45:57 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380035110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.1380035110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/182.edn_genbits.3025593454
Short name T853
Test name
Test status
Simulation time 82648931 ps
CPU time 1.66 seconds
Started Sep 18 09:45:54 AM UTC 24
Finished Sep 18 09:45:57 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025593454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3025593454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/183.edn_alert.4119015531
Short name T854
Test name
Test status
Simulation time 48568659 ps
CPU time 1.33 seconds
Started Sep 18 09:45:55 AM UTC 24
Finished Sep 18 09:45:58 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119015531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.4119015531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/183.edn_genbits.1847835960
Short name T855
Test name
Test status
Simulation time 38595285 ps
CPU time 2.26 seconds
Started Sep 18 09:45:55 AM UTC 24
Finished Sep 18 09:45:59 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847835960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1847835960
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/184.edn_alert.83855613
Short name T858
Test name
Test status
Simulation time 28892541 ps
CPU time 1.69 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:45:59 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83855613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 184.edn_alert.83855613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/184.edn_genbits.1847275094
Short name T863
Test name
Test status
Simulation time 36703827 ps
CPU time 2.27 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847275094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1847275094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/185.edn_alert.2171191180
Short name T857
Test name
Test status
Simulation time 36045653 ps
CPU time 1.46 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:45:59 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171191180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 185.edn_alert.2171191180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/185.edn_genbits.862917893
Short name T856
Test name
Test status
Simulation time 30582122 ps
CPU time 1.35 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:45:59 AM UTC 24
Peak memory 229204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862917893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 185.edn_genbits.862917893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/186.edn_alert.2997536438
Short name T859
Test name
Test status
Simulation time 42436367 ps
CPU time 1.52 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997536438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.2997536438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/186.edn_genbits.292583904
Short name T860
Test name
Test status
Simulation time 67016428 ps
CPU time 1.86 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292583904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.edn_genbits.292583904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/187.edn_alert.2153255021
Short name T862
Test name
Test status
Simulation time 75508227 ps
CPU time 1.68 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153255021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.2153255021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/187.edn_genbits.1512051697
Short name T861
Test name
Test status
Simulation time 53356590 ps
CPU time 1.74 seconds
Started Sep 18 09:45:57 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512051697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1512051697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/188.edn_alert.310194714
Short name T178
Test name
Test status
Simulation time 52686682 ps
CPU time 1.46 seconds
Started Sep 18 09:45:58 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310194714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 188.edn_alert.310194714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/189.edn_alert.1842508218
Short name T865
Test name
Test status
Simulation time 25890144 ps
CPU time 1.6 seconds
Started Sep 18 09:45:58 AM UTC 24
Finished Sep 18 09:46:01 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842508218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.1842508218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/189.edn_genbits.3856308772
Short name T867
Test name
Test status
Simulation time 34081917 ps
CPU time 2.39 seconds
Started Sep 18 09:45:58 AM UTC 24
Finished Sep 18 09:46:01 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856308772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3856308772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_alert.3318414295
Short name T142
Test name
Test status
Simulation time 43641001 ps
CPU time 1.57 seconds
Started Sep 18 09:41:08 AM UTC 24
Finished Sep 18 09:41:11 AM UTC 24
Peak memory 229004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318414295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.3318414295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_alert_test.3907205954
Short name T391
Test name
Test status
Simulation time 15302215 ps
CPU time 1.15 seconds
Started Sep 18 09:41:09 AM UTC 24
Finished Sep 18 09:41:11 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907205954 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3907205954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_disable.1199130998
Short name T392
Test name
Test status
Simulation time 15113983 ps
CPU time 1.37 seconds
Started Sep 18 09:41:09 AM UTC 24
Finished Sep 18 09:41:11 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199130998 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1199130998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.3648914885
Short name T161
Test name
Test status
Simulation time 30417071 ps
CPU time 1.67 seconds
Started Sep 18 09:41:09 AM UTC 24
Finished Sep 18 09:41:11 AM UTC 24
Peak memory 231000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648914885 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.3648914885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_err.426972986
Short name T390
Test name
Test status
Simulation time 24650299 ps
CPU time 1.35 seconds
Started Sep 18 09:41:08 AM UTC 24
Finished Sep 18 09:41:11 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426972986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.edn_err.426972986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_genbits.2792351424
Short name T386
Test name
Test status
Simulation time 45492754 ps
CPU time 1.26 seconds
Started Sep 18 09:41:05 AM UTC 24
Finished Sep 18 09:41:08 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792351424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2792351424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_intr.1084834274
Short name T389
Test name
Test status
Simulation time 23184731 ps
CPU time 1.36 seconds
Started Sep 18 09:41:08 AM UTC 24
Finished Sep 18 09:41:10 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084834274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.1084834274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_smoke.3218399997
Short name T387
Test name
Test status
Simulation time 18392037 ps
CPU time 1.4 seconds
Started Sep 18 09:41:05 AM UTC 24
Finished Sep 18 09:41:08 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218399997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_smoke.3218399997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/19.edn_stress_all.211703439
Short name T388
Test name
Test status
Simulation time 60514959 ps
CPU time 1.62 seconds
Started Sep 18 09:41:07 AM UTC 24
Finished Sep 18 09:41:09 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211703439 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.211703439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/190.edn_alert.2996236363
Short name T866
Test name
Test status
Simulation time 187354525 ps
CPU time 1.68 seconds
Started Sep 18 09:45:58 AM UTC 24
Finished Sep 18 09:46:01 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996236363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.2996236363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/190.edn_genbits.4227028811
Short name T864
Test name
Test status
Simulation time 33183249 ps
CPU time 1.17 seconds
Started Sep 18 09:45:58 AM UTC 24
Finished Sep 18 09:46:00 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227028811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4227028811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/191.edn_alert.3201937523
Short name T868
Test name
Test status
Simulation time 80507006 ps
CPU time 1.49 seconds
Started Sep 18 09:45:59 AM UTC 24
Finished Sep 18 09:46:02 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201937523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.3201937523
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/191.edn_genbits.2883014657
Short name T869
Test name
Test status
Simulation time 88169285 ps
CPU time 1.74 seconds
Started Sep 18 09:45:59 AM UTC 24
Finished Sep 18 09:46:02 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883014657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2883014657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/192.edn_alert.3644360449
Short name T872
Test name
Test status
Simulation time 94295626 ps
CPU time 1.69 seconds
Started Sep 18 09:46:00 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644360449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.3644360449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/192.edn_genbits.1756176416
Short name T877
Test name
Test status
Simulation time 33617094 ps
CPU time 1.96 seconds
Started Sep 18 09:46:00 AM UTC 24
Finished Sep 18 09:46:04 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756176416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1756176416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/193.edn_alert.79903271
Short name T874
Test name
Test status
Simulation time 26055867 ps
CPU time 1.74 seconds
Started Sep 18 09:46:00 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79903271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 193.edn_alert.79903271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/193.edn_genbits.327198384
Short name T871
Test name
Test status
Simulation time 41424773 ps
CPU time 1.69 seconds
Started Sep 18 09:46:00 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327198384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.edn_genbits.327198384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/194.edn_alert.3249589770
Short name T873
Test name
Test status
Simulation time 72716389 ps
CPU time 1.59 seconds
Started Sep 18 09:46:01 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249589770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.3249589770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/194.edn_genbits.3180559995
Short name T870
Test name
Test status
Simulation time 65609521 ps
CPU time 1.45 seconds
Started Sep 18 09:46:01 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180559995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3180559995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/195.edn_alert.2253324648
Short name T875
Test name
Test status
Simulation time 121297358 ps
CPU time 1.6 seconds
Started Sep 18 09:46:01 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253324648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 195.edn_alert.2253324648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/195.edn_genbits.4209084750
Short name T876
Test name
Test status
Simulation time 37840390 ps
CPU time 1.71 seconds
Started Sep 18 09:46:01 AM UTC 24
Finished Sep 18 09:46:03 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209084750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4209084750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/196.edn_alert.655134569
Short name T879
Test name
Test status
Simulation time 78315390 ps
CPU time 1.54 seconds
Started Sep 18 09:46:02 AM UTC 24
Finished Sep 18 09:46:04 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655134569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 196.edn_alert.655134569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/197.edn_alert.78411487
Short name T880
Test name
Test status
Simulation time 28058078 ps
CPU time 1.77 seconds
Started Sep 18 09:46:02 AM UTC 24
Finished Sep 18 09:46:05 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78411487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 197.edn_alert.78411487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/197.edn_genbits.1012155125
Short name T881
Test name
Test status
Simulation time 54484468 ps
CPU time 2.2 seconds
Started Sep 18 09:46:02 AM UTC 24
Finished Sep 18 09:46:05 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012155125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1012155125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/198.edn_alert.468554255
Short name T878
Test name
Test status
Simulation time 41758379 ps
CPU time 1.18 seconds
Started Sep 18 09:46:02 AM UTC 24
Finished Sep 18 09:46:04 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468554255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 198.edn_alert.468554255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/198.edn_genbits.4189059635
Short name T883
Test name
Test status
Simulation time 125179960 ps
CPU time 3 seconds
Started Sep 18 09:46:02 AM UTC 24
Finished Sep 18 09:46:06 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189059635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4189059635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/199.edn_alert.2437922254
Short name T882
Test name
Test status
Simulation time 67169980 ps
CPU time 1.45 seconds
Started Sep 18 09:46:03 AM UTC 24
Finished Sep 18 09:46:06 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437922254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.2437922254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/199.edn_genbits.45719089
Short name T884
Test name
Test status
Simulation time 55020362 ps
CPU time 2.46 seconds
Started Sep 18 09:46:03 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 228120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45719089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 199.edn_genbits.45719089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_alert.2251319897
Short name T27
Test name
Test status
Simulation time 28009204 ps
CPU time 1.78 seconds
Started Sep 18 09:39:29 AM UTC 24
Finished Sep 18 09:39:34 AM UTC 24
Peak memory 230900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251319897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_alert.2251319897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_alert_test.1093631317
Short name T59
Test name
Test status
Simulation time 21818066 ps
CPU time 1.3 seconds
Started Sep 18 09:39:35 AM UTC 24
Finished Sep 18 09:39:38 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093631317 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1093631317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.1768416502
Short name T18
Test name
Test status
Simulation time 45169441 ps
CPU time 1.81 seconds
Started Sep 18 09:39:31 AM UTC 24
Finished Sep 18 09:39:35 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768416502 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.1768416502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_intr.2967510583
Short name T29
Test name
Test status
Simulation time 24706027 ps
CPU time 1.3 seconds
Started Sep 18 09:39:27 AM UTC 24
Finished Sep 18 09:39:29 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967510583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.2967510583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_regwen.3436635970
Short name T25
Test name
Test status
Simulation time 16964478 ps
CPU time 1.39 seconds
Started Sep 18 09:39:25 AM UTC 24
Finished Sep 18 09:39:27 AM UTC 24
Peak memory 216652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436635970 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.3436635970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_sec_cm.198419167
Short name T17
Test name
Test status
Simulation time 303236154 ps
CPU time 7.09 seconds
Started Sep 18 09:39:31 AM UTC 24
Finished Sep 18 09:39:40 AM UTC 24
Peak memory 260788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198419167 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.198419167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_smoke.3560074198
Short name T62
Test name
Test status
Simulation time 15415072 ps
CPU time 1.38 seconds
Started Sep 18 09:39:25 AM UTC 24
Finished Sep 18 09:39:27 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560074198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.3560074198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.4132488498
Short name T35
Test name
Test status
Simulation time 2832920178 ps
CPU time 74.94 seconds
Started Sep 18 09:39:27 AM UTC 24
Finished Sep 18 09:40:44 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4132488498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_
with_rand_reset.4132488498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_alert_test.2257402809
Short name T397
Test name
Test status
Simulation time 106150486 ps
CPU time 1.37 seconds
Started Sep 18 09:41:14 AM UTC 24
Finished Sep 18 09:41:17 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257402809 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2257402809
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_disable.3997473794
Short name T201
Test name
Test status
Simulation time 95600675 ps
CPU time 1.15 seconds
Started Sep 18 09:41:13 AM UTC 24
Finished Sep 18 09:41:15 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997473794 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3997473794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.1627909623
Short name T396
Test name
Test status
Simulation time 29692693 ps
CPU time 1.55 seconds
Started Sep 18 09:41:13 AM UTC 24
Finished Sep 18 09:41:16 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627909623 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.1627909623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_err.385748548
Short name T395
Test name
Test status
Simulation time 18103916 ps
CPU time 1.55 seconds
Started Sep 18 09:41:12 AM UTC 24
Finished Sep 18 09:41:16 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385748548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.edn_err.385748548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_genbits.1099839038
Short name T44
Test name
Test status
Simulation time 176934998 ps
CPU time 1.6 seconds
Started Sep 18 09:41:10 AM UTC 24
Finished Sep 18 09:41:13 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099839038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1099839038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_intr.341805645
Short name T327
Test name
Test status
Simulation time 43348102 ps
CPU time 1.33 seconds
Started Sep 18 09:41:11 AM UTC 24
Finished Sep 18 09:41:14 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341805645 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.341805645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_smoke.466703240
Short name T393
Test name
Test status
Simulation time 56325030 ps
CPU time 1.13 seconds
Started Sep 18 09:41:10 AM UTC 24
Finished Sep 18 09:41:12 AM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466703240 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_smoke.466703240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_stress_all.3310985054
Short name T394
Test name
Test status
Simulation time 167251806 ps
CPU time 3.02 seconds
Started Sep 18 09:41:10 AM UTC 24
Finished Sep 18 09:41:14 AM UTC 24
Peak memory 230280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310985054 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3310985054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.3428282236
Short name T244
Test name
Test status
Simulation time 4090858650 ps
CPU time 72.31 seconds
Started Sep 18 09:41:11 AM UTC 24
Finished Sep 18 09:42:25 AM UTC 24
Peak memory 234788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3428282236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all
_with_rand_reset.3428282236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/200.edn_genbits.2759601079
Short name T887
Test name
Test status
Simulation time 51793379 ps
CPU time 1.64 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759601079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2759601079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/201.edn_genbits.3925263185
Short name T891
Test name
Test status
Simulation time 54245669 ps
CPU time 2.42 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:08 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925263185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3925263185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/202.edn_genbits.3196346553
Short name T886
Test name
Test status
Simulation time 50499949 ps
CPU time 1.45 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196346553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3196346553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/203.edn_genbits.1317001218
Short name T885
Test name
Test status
Simulation time 31298092 ps
CPU time 1.36 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317001218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1317001218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/204.edn_genbits.432355276
Short name T898
Test name
Test status
Simulation time 146478390 ps
CPU time 4.63 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:10 AM UTC 24
Peak memory 232160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432355276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 204.edn_genbits.432355276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/205.edn_genbits.1045722559
Short name T889
Test name
Test status
Simulation time 130236178 ps
CPU time 1.64 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045722559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1045722559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/206.edn_genbits.1464314406
Short name T890
Test name
Test status
Simulation time 39887176 ps
CPU time 1.75 seconds
Started Sep 18 09:46:04 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464314406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1464314406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/207.edn_genbits.3368204621
Short name T888
Test name
Test status
Simulation time 36132249 ps
CPU time 1.46 seconds
Started Sep 18 09:46:05 AM UTC 24
Finished Sep 18 09:46:07 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368204621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3368204621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/208.edn_genbits.4136508146
Short name T907
Test name
Test status
Simulation time 253390058 ps
CPU time 4.6 seconds
Started Sep 18 09:46:06 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136508146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4136508146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/209.edn_genbits.2756901358
Short name T892
Test name
Test status
Simulation time 107398840 ps
CPU time 1.76 seconds
Started Sep 18 09:46:06 AM UTC 24
Finished Sep 18 09:46:08 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756901358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2756901358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_alert_test.2032066250
Short name T399
Test name
Test status
Simulation time 13906382 ps
CPU time 1.28 seconds
Started Sep 18 09:41:19 AM UTC 24
Finished Sep 18 09:41:22 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032066250 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2032066250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.2672939510
Short name T100
Test name
Test status
Simulation time 110396658 ps
CPU time 1.74 seconds
Started Sep 18 09:41:17 AM UTC 24
Finished Sep 18 09:41:20 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672939510 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.2672939510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_err.2350934335
Short name T169
Test name
Test status
Simulation time 76973202 ps
CPU time 1.54 seconds
Started Sep 18 09:41:17 AM UTC 24
Finished Sep 18 09:41:20 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350934335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.2350934335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_genbits.904259155
Short name T332
Test name
Test status
Simulation time 78475330 ps
CPU time 1.67 seconds
Started Sep 18 09:41:15 AM UTC 24
Finished Sep 18 09:41:18 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904259155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_genbits.904259155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_intr.522131128
Short name T111
Test name
Test status
Simulation time 44122522 ps
CPU time 1.39 seconds
Started Sep 18 09:41:16 AM UTC 24
Finished Sep 18 09:41:19 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522131128 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.522131128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_smoke.3955348474
Short name T398
Test name
Test status
Simulation time 67184677 ps
CPU time 1.29 seconds
Started Sep 18 09:41:14 AM UTC 24
Finished Sep 18 09:41:17 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955348474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.3955348474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_stress_all.3352211556
Short name T250
Test name
Test status
Simulation time 199750788 ps
CPU time 3.02 seconds
Started Sep 18 09:41:15 AM UTC 24
Finished Sep 18 09:41:19 AM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352211556 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3352211556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.2131104926
Short name T484
Test name
Test status
Simulation time 11519618310 ps
CPU time 88.99 seconds
Started Sep 18 09:41:15 AM UTC 24
Finished Sep 18 09:42:46 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2131104926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.2131104926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/210.edn_genbits.2145286779
Short name T895
Test name
Test status
Simulation time 55186074 ps
CPU time 2.16 seconds
Started Sep 18 09:46:06 AM UTC 24
Finished Sep 18 09:46:09 AM UTC 24
Peak memory 230252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145286779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2145286779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/211.edn_genbits.215569462
Short name T893
Test name
Test status
Simulation time 111118137 ps
CPU time 1.8 seconds
Started Sep 18 09:46:06 AM UTC 24
Finished Sep 18 09:46:09 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215569462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 211.edn_genbits.215569462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/212.edn_genbits.1962603023
Short name T894
Test name
Test status
Simulation time 33172143 ps
CPU time 1.88 seconds
Started Sep 18 09:46:06 AM UTC 24
Finished Sep 18 09:46:09 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962603023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1962603023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/213.edn_genbits.1242775216
Short name T896
Test name
Test status
Simulation time 79501964 ps
CPU time 1.32 seconds
Started Sep 18 09:46:07 AM UTC 24
Finished Sep 18 09:46:09 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242775216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1242775216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/214.edn_genbits.684643099
Short name T897
Test name
Test status
Simulation time 41970389 ps
CPU time 1.46 seconds
Started Sep 18 09:46:07 AM UTC 24
Finished Sep 18 09:46:09 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684643099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 214.edn_genbits.684643099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/215.edn_genbits.862795196
Short name T899
Test name
Test status
Simulation time 53557404 ps
CPU time 1.3 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:10 AM UTC 24
Peak memory 228892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862795196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 215.edn_genbits.862795196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/216.edn_genbits.564975988
Short name T901
Test name
Test status
Simulation time 69853237 ps
CPU time 1.68 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564975988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.edn_genbits.564975988
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/217.edn_genbits.3349753964
Short name T903
Test name
Test status
Simulation time 118258981 ps
CPU time 1.71 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349753964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3349753964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/218.edn_genbits.821004576
Short name T905
Test name
Test status
Simulation time 31947092 ps
CPU time 1.78 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821004576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 218.edn_genbits.821004576
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/219.edn_genbits.1385223003
Short name T902
Test name
Test status
Simulation time 61669733 ps
CPU time 1.51 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385223003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1385223003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_alert.473996906
Short name T72
Test name
Test status
Simulation time 79305875 ps
CPU time 1.69 seconds
Started Sep 18 09:41:21 AM UTC 24
Finished Sep 18 09:41:23 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473996906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.edn_alert.473996906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_alert_test.1380557250
Short name T405
Test name
Test status
Simulation time 38507408 ps
CPU time 1.15 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:26 AM UTC 24
Peak memory 216900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380557250 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1380557250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.1313349821
Short name T404
Test name
Test status
Simulation time 52660046 ps
CPU time 1.32 seconds
Started Sep 18 09:41:23 AM UTC 24
Finished Sep 18 09:41:25 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313349821 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.1313349821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_genbits.2506931954
Short name T333
Test name
Test status
Simulation time 87413146 ps
CPU time 2.13 seconds
Started Sep 18 09:41:19 AM UTC 24
Finished Sep 18 09:41:23 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506931954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2506931954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_intr.1945104586
Short name T402
Test name
Test status
Simulation time 30125637 ps
CPU time 1.61 seconds
Started Sep 18 09:41:21 AM UTC 24
Finished Sep 18 09:41:23 AM UTC 24
Peak memory 238288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945104586 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.1945104586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_smoke.837568334
Short name T400
Test name
Test status
Simulation time 18589998 ps
CPU time 1.39 seconds
Started Sep 18 09:41:19 AM UTC 24
Finished Sep 18 09:41:22 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837568334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.edn_smoke.837568334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_stress_all.1029503939
Short name T401
Test name
Test status
Simulation time 42644939 ps
CPU time 1.62 seconds
Started Sep 18 09:41:20 AM UTC 24
Finished Sep 18 09:41:23 AM UTC 24
Peak memory 217332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029503939 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1029503939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.1192677218
Short name T312
Test name
Test status
Simulation time 8547581988 ps
CPU time 53.24 seconds
Started Sep 18 09:41:21 AM UTC 24
Finished Sep 18 09:42:15 AM UTC 24
Peak memory 230536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1192677218 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all
_with_rand_reset.1192677218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/220.edn_genbits.965740945
Short name T900
Test name
Test status
Simulation time 66111907 ps
CPU time 1.42 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965740945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 220.edn_genbits.965740945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/221.edn_genbits.1115768911
Short name T904
Test name
Test status
Simulation time 50131180 ps
CPU time 1.54 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:11 AM UTC 24
Peak memory 226936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115768911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1115768911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/222.edn_genbits.286567318
Short name T816
Test name
Test status
Simulation time 38317687 ps
CPU time 2.18 seconds
Started Sep 18 09:46:08 AM UTC 24
Finished Sep 18 09:46:12 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286567318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 222.edn_genbits.286567318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/223.edn_genbits.3647116070
Short name T908
Test name
Test status
Simulation time 65424591 ps
CPU time 1.79 seconds
Started Sep 18 09:46:09 AM UTC 24
Finished Sep 18 09:46:12 AM UTC 24
Peak memory 229264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647116070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3647116070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/224.edn_genbits.1950857092
Short name T818
Test name
Test status
Simulation time 23084356 ps
CPU time 1.55 seconds
Started Sep 18 09:46:09 AM UTC 24
Finished Sep 18 09:46:12 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950857092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1950857092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/225.edn_genbits.987046455
Short name T913
Test name
Test status
Simulation time 133273381 ps
CPU time 3.4 seconds
Started Sep 18 09:46:10 AM UTC 24
Finished Sep 18 09:46:14 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987046455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 225.edn_genbits.987046455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/226.edn_genbits.2486597755
Short name T906
Test name
Test status
Simulation time 86494065 ps
CPU time 1.54 seconds
Started Sep 18 09:46:10 AM UTC 24
Finished Sep 18 09:46:12 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486597755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2486597755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/227.edn_genbits.3068648570
Short name T909
Test name
Test status
Simulation time 45778313 ps
CPU time 1.71 seconds
Started Sep 18 09:46:10 AM UTC 24
Finished Sep 18 09:46:12 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068648570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3068648570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/228.edn_genbits.1131537396
Short name T912
Test name
Test status
Simulation time 103111068 ps
CPU time 3.11 seconds
Started Sep 18 09:46:10 AM UTC 24
Finished Sep 18 09:46:14 AM UTC 24
Peak memory 230080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131537396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1131537396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/229.edn_genbits.2064484741
Short name T910
Test name
Test status
Simulation time 100282022 ps
CPU time 1.59 seconds
Started Sep 18 09:46:11 AM UTC 24
Finished Sep 18 09:46:13 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064484741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2064484741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_alert.2472304984
Short name T162
Test name
Test status
Simulation time 27546461 ps
CPU time 1.94 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:27 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472304984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.2472304984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_alert_test.3493102956
Short name T409
Test name
Test status
Simulation time 22856346 ps
CPU time 1.21 seconds
Started Sep 18 09:41:28 AM UTC 24
Finished Sep 18 09:41:30 AM UTC 24
Peak memory 227556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493102956 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3493102956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_disable.2144505317
Short name T202
Test name
Test status
Simulation time 11309324 ps
CPU time 1.22 seconds
Started Sep 18 09:41:26 AM UTC 24
Finished Sep 18 09:41:29 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144505317 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2144505317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_err.3553976067
Short name T170
Test name
Test status
Simulation time 49986352 ps
CPU time 1.4 seconds
Started Sep 18 09:41:25 AM UTC 24
Finished Sep 18 09:41:28 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553976067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.edn_err.3553976067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_genbits.4102479065
Short name T78
Test name
Test status
Simulation time 266052609 ps
CPU time 1.43 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:26 AM UTC 24
Peak memory 226828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102479065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4102479065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_intr.796716949
Short name T407
Test name
Test status
Simulation time 23159804 ps
CPU time 1.64 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:27 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796716949 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.796716949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_smoke.1432986782
Short name T406
Test name
Test status
Simulation time 14296391 ps
CPU time 1.33 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:26 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432986782 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.1432986782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_stress_all.667470133
Short name T408
Test name
Test status
Simulation time 502994234 ps
CPU time 4.09 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:29 AM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667470133 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.667470133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.2927370737
Short name T424
Test name
Test status
Simulation time 394293046 ps
CPU time 14.68 seconds
Started Sep 18 09:41:24 AM UTC 24
Finished Sep 18 09:41:40 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2927370737 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all
_with_rand_reset.2927370737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/230.edn_genbits.1301550007
Short name T911
Test name
Test status
Simulation time 45839071 ps
CPU time 1.71 seconds
Started Sep 18 09:46:11 AM UTC 24
Finished Sep 18 09:46:13 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301550007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1301550007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/231.edn_genbits.3324635737
Short name T914
Test name
Test status
Simulation time 69346728 ps
CPU time 2.41 seconds
Started Sep 18 09:46:11 AM UTC 24
Finished Sep 18 09:46:14 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324635737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3324635737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/232.edn_genbits.2863013696
Short name T915
Test name
Test status
Simulation time 113367962 ps
CPU time 1.54 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:14 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863013696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2863013696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/233.edn_genbits.2692408904
Short name T921
Test name
Test status
Simulation time 59689693 ps
CPU time 2.21 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:15 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692408904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2692408904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/234.edn_genbits.2069751841
Short name T920
Test name
Test status
Simulation time 46090132 ps
CPU time 2.09 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:15 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069751841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2069751841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/235.edn_genbits.1495950492
Short name T918
Test name
Test status
Simulation time 39669397 ps
CPU time 1.98 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:15 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495950492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1495950492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/236.edn_genbits.3040292880
Short name T917
Test name
Test status
Simulation time 52335219 ps
CPU time 1.49 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:15 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040292880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3040292880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/237.edn_genbits.1161074906
Short name T919
Test name
Test status
Simulation time 50379326 ps
CPU time 1.92 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:15 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161074906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1161074906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/238.edn_genbits.3639154940
Short name T916
Test name
Test status
Simulation time 28933346 ps
CPU time 1.42 seconds
Started Sep 18 09:46:12 AM UTC 24
Finished Sep 18 09:46:15 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639154940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3639154940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/239.edn_genbits.1597872117
Short name T923
Test name
Test status
Simulation time 97079817 ps
CPU time 1.37 seconds
Started Sep 18 09:46:13 AM UTC 24
Finished Sep 18 09:46:16 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597872117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1597872117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_alert.3735916116
Short name T84
Test name
Test status
Simulation time 89294337 ps
CPU time 1.56 seconds
Started Sep 18 09:41:30 AM UTC 24
Finished Sep 18 09:41:33 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735916116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.3735916116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_alert_test.3044709568
Short name T412
Test name
Test status
Simulation time 96318581 ps
CPU time 1.29 seconds
Started Sep 18 09:41:31 AM UTC 24
Finished Sep 18 09:41:34 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044709568 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3044709568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_disable.3005411092
Short name T83
Test name
Test status
Simulation time 12743973 ps
CPU time 1.24 seconds
Started Sep 18 09:41:30 AM UTC 24
Finished Sep 18 09:41:32 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005411092 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3005411092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.1737879940
Short name T414
Test name
Test status
Simulation time 48952083 ps
CPU time 1.85 seconds
Started Sep 18 09:41:31 AM UTC 24
Finished Sep 18 09:41:34 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737879940 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.1737879940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_err.3447843414
Short name T159
Test name
Test status
Simulation time 49939668 ps
CPU time 1.41 seconds
Started Sep 18 09:41:30 AM UTC 24
Finished Sep 18 09:41:32 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447843414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.3447843414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_genbits.3823383420
Short name T305
Test name
Test status
Simulation time 40605051 ps
CPU time 1.59 seconds
Started Sep 18 09:41:28 AM UTC 24
Finished Sep 18 09:41:30 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823383420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3823383420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_smoke.1055688968
Short name T410
Test name
Test status
Simulation time 52970318 ps
CPU time 1.29 seconds
Started Sep 18 09:41:28 AM UTC 24
Finished Sep 18 09:41:30 AM UTC 24
Peak memory 226652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055688968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_smoke.1055688968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_stress_all.935910487
Short name T411
Test name
Test status
Simulation time 302905753 ps
CPU time 3.14 seconds
Started Sep 18 09:41:28 AM UTC 24
Finished Sep 18 09:41:32 AM UTC 24
Peak memory 230080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935910487 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.935910487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.1657521624
Short name T538
Test name
Test status
Simulation time 13615206420 ps
CPU time 128.8 seconds
Started Sep 18 09:41:29 AM UTC 24
Finished Sep 18 09:43:40 AM UTC 24
Peak memory 230476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1657521624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.1657521624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/240.edn_genbits.3154254658
Short name T922
Test name
Test status
Simulation time 80929927 ps
CPU time 1.21 seconds
Started Sep 18 09:46:13 AM UTC 24
Finished Sep 18 09:46:16 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154254658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3154254658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/241.edn_genbits.2411111070
Short name T924
Test name
Test status
Simulation time 81451987 ps
CPU time 1.61 seconds
Started Sep 18 09:46:13 AM UTC 24
Finished Sep 18 09:46:16 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411111070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2411111070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/242.edn_genbits.3393777262
Short name T925
Test name
Test status
Simulation time 35173532 ps
CPU time 1.57 seconds
Started Sep 18 09:46:13 AM UTC 24
Finished Sep 18 09:46:16 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393777262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3393777262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/243.edn_genbits.1428735421
Short name T318
Test name
Test status
Simulation time 2216121103 ps
CPU time 78.83 seconds
Started Sep 18 09:46:14 AM UTC 24
Finished Sep 18 09:47:34 AM UTC 24
Peak memory 230376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428735421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1428735421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/244.edn_genbits.3758754574
Short name T926
Test name
Test status
Simulation time 212758443 ps
CPU time 1.35 seconds
Started Sep 18 09:46:15 AM UTC 24
Finished Sep 18 09:46:17 AM UTC 24
Peak memory 228976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758754574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3758754574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/245.edn_genbits.3609257048
Short name T927
Test name
Test status
Simulation time 79092281 ps
CPU time 1.54 seconds
Started Sep 18 09:46:15 AM UTC 24
Finished Sep 18 09:46:17 AM UTC 24
Peak memory 226912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609257048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3609257048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/246.edn_genbits.4192768694
Short name T928
Test name
Test status
Simulation time 217226831 ps
CPU time 1.67 seconds
Started Sep 18 09:46:15 AM UTC 24
Finished Sep 18 09:46:17 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192768694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4192768694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/247.edn_genbits.1128674924
Short name T929
Test name
Test status
Simulation time 63092888 ps
CPU time 1.63 seconds
Started Sep 18 09:46:15 AM UTC 24
Finished Sep 18 09:46:17 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128674924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1128674924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/248.edn_genbits.3041517639
Short name T930
Test name
Test status
Simulation time 72988490 ps
CPU time 2.3 seconds
Started Sep 18 09:46:15 AM UTC 24
Finished Sep 18 09:46:18 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041517639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3041517639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/249.edn_genbits.4287264206
Short name T931
Test name
Test status
Simulation time 56141355 ps
CPU time 1.38 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:18 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287264206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4287264206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_alert.1573950030
Short name T199
Test name
Test status
Simulation time 23779035 ps
CPU time 1.71 seconds
Started Sep 18 09:41:34 AM UTC 24
Finished Sep 18 09:41:36 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573950030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.1573950030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_alert_test.4121460559
Short name T421
Test name
Test status
Simulation time 67771611 ps
CPU time 1.3 seconds
Started Sep 18 09:41:36 AM UTC 24
Finished Sep 18 09:41:38 AM UTC 24
Peak memory 227180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121460559 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4121460559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_disable.2421515469
Short name T417
Test name
Test status
Simulation time 20916442 ps
CPU time 1.15 seconds
Started Sep 18 09:41:35 AM UTC 24
Finished Sep 18 09:41:37 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421515469 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2421515469
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.633198709
Short name T422
Test name
Test status
Simulation time 121712267 ps
CPU time 1.71 seconds
Started Sep 18 09:41:36 AM UTC 24
Finished Sep 18 09:41:39 AM UTC 24
Peak memory 226908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633198709 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.633198709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_err.3364376239
Short name T419
Test name
Test status
Simulation time 40765143 ps
CPU time 1.61 seconds
Started Sep 18 09:41:35 AM UTC 24
Finished Sep 18 09:41:37 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364376239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.3364376239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_genbits.1916081316
Short name T295
Test name
Test status
Simulation time 39084257 ps
CPU time 1.99 seconds
Started Sep 18 09:41:32 AM UTC 24
Finished Sep 18 09:41:36 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916081316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1916081316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_intr.4216144369
Short name T416
Test name
Test status
Simulation time 27973038 ps
CPU time 1.29 seconds
Started Sep 18 09:41:33 AM UTC 24
Finished Sep 18 09:41:36 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216144369 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.4216144369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_smoke.1701697573
Short name T413
Test name
Test status
Simulation time 16817062 ps
CPU time 1.44 seconds
Started Sep 18 09:41:31 AM UTC 24
Finished Sep 18 09:41:34 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701697573 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.1701697573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_stress_all.480678933
Short name T420
Test name
Test status
Simulation time 413301189 ps
CPU time 3.52 seconds
Started Sep 18 09:41:33 AM UTC 24
Finished Sep 18 09:41:38 AM UTC 24
Peak memory 228168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480678933 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.480678933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.1188893080
Short name T531
Test name
Test status
Simulation time 5653546034 ps
CPU time 116.87 seconds
Started Sep 18 09:41:33 AM UTC 24
Finished Sep 18 09:43:33 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1188893080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.1188893080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/250.edn_genbits.762014400
Short name T937
Test name
Test status
Simulation time 67932949 ps
CPU time 2.77 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:20 AM UTC 24
Peak memory 232288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762014400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 250.edn_genbits.762014400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/251.edn_genbits.1932892583
Short name T932
Test name
Test status
Simulation time 75511245 ps
CPU time 1.51 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:18 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932892583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1932892583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/252.edn_genbits.3906791107
Short name T934
Test name
Test status
Simulation time 45190194 ps
CPU time 1.82 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:19 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906791107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3906791107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/253.edn_genbits.955653705
Short name T938
Test name
Test status
Simulation time 125103784 ps
CPU time 2.81 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:20 AM UTC 24
Peak memory 232212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955653705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 253.edn_genbits.955653705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/254.edn_genbits.3281525547
Short name T933
Test name
Test status
Simulation time 144921446 ps
CPU time 1.63 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:19 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281525547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3281525547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/255.edn_genbits.3522312608
Short name T935
Test name
Test status
Simulation time 47410150 ps
CPU time 1.76 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:19 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522312608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3522312608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/256.edn_genbits.3301069045
Short name T943
Test name
Test status
Simulation time 290809353 ps
CPU time 4.13 seconds
Started Sep 18 09:46:16 AM UTC 24
Finished Sep 18 09:46:21 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301069045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3301069045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/257.edn_genbits.1560737189
Short name T936
Test name
Test status
Simulation time 155925829 ps
CPU time 1.3 seconds
Started Sep 18 09:46:17 AM UTC 24
Finished Sep 18 09:46:19 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560737189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1560737189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/258.edn_genbits.1472054296
Short name T940
Test name
Test status
Simulation time 39078189 ps
CPU time 1.82 seconds
Started Sep 18 09:46:17 AM UTC 24
Finished Sep 18 09:46:20 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472054296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1472054296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/259.edn_genbits.1429900567
Short name T941
Test name
Test status
Simulation time 68141436 ps
CPU time 2.06 seconds
Started Sep 18 09:46:17 AM UTC 24
Finished Sep 18 09:46:20 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429900567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1429900567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_alert.3160967374
Short name T205
Test name
Test status
Simulation time 21409908 ps
CPU time 1.5 seconds
Started Sep 18 09:41:38 AM UTC 24
Finished Sep 18 09:41:41 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160967374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_alert.3160967374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_alert_test.1378540240
Short name T428
Test name
Test status
Simulation time 13541344 ps
CPU time 1.26 seconds
Started Sep 18 09:41:40 AM UTC 24
Finished Sep 18 09:41:43 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378540240 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1378540240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.3519416972
Short name T426
Test name
Test status
Simulation time 30331548 ps
CPU time 1.83 seconds
Started Sep 18 09:41:39 AM UTC 24
Finished Sep 18 09:41:42 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519416972 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.3519416972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_err.1577106218
Short name T191
Test name
Test status
Simulation time 21509465 ps
CPU time 1.28 seconds
Started Sep 18 09:41:39 AM UTC 24
Finished Sep 18 09:41:41 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577106218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.1577106218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_intr.1688817396
Short name T425
Test name
Test status
Simulation time 24966491 ps
CPU time 1.02 seconds
Started Sep 18 09:41:38 AM UTC 24
Finished Sep 18 09:41:40 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688817396 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.1688817396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_smoke.322566318
Short name T423
Test name
Test status
Simulation time 39811789 ps
CPU time 1.08 seconds
Started Sep 18 09:41:37 AM UTC 24
Finished Sep 18 09:41:39 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322566318 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.edn_smoke.322566318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_stress_all.3576867472
Short name T427
Test name
Test status
Simulation time 89965407 ps
CPU time 3.11 seconds
Started Sep 18 09:41:38 AM UTC 24
Finished Sep 18 09:41:42 AM UTC 24
Peak memory 227964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576867472 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3576867472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.2171935798
Short name T622
Test name
Test status
Simulation time 41625480861 ps
CPU time 181.88 seconds
Started Sep 18 09:41:38 AM UTC 24
Finished Sep 18 09:44:43 AM UTC 24
Peak memory 230300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2171935798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all
_with_rand_reset.2171935798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/260.edn_genbits.1158295244
Short name T939
Test name
Test status
Simulation time 29374840 ps
CPU time 1.7 seconds
Started Sep 18 09:46:17 AM UTC 24
Finished Sep 18 09:46:20 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158295244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1158295244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/261.edn_genbits.1640861372
Short name T945
Test name
Test status
Simulation time 69533369 ps
CPU time 2.29 seconds
Started Sep 18 09:46:18 AM UTC 24
Finished Sep 18 09:46:22 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640861372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1640861372
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/262.edn_genbits.1356259409
Short name T942
Test name
Test status
Simulation time 41487734 ps
CPU time 1.86 seconds
Started Sep 18 09:46:18 AM UTC 24
Finished Sep 18 09:46:21 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356259409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1356259409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/263.edn_genbits.3718330414
Short name T947
Test name
Test status
Simulation time 50575040 ps
CPU time 2.8 seconds
Started Sep 18 09:46:19 AM UTC 24
Finished Sep 18 09:46:22 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718330414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3718330414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/264.edn_genbits.3806528853
Short name T944
Test name
Test status
Simulation time 41841169 ps
CPU time 2.12 seconds
Started Sep 18 09:46:19 AM UTC 24
Finished Sep 18 09:46:22 AM UTC 24
Peak memory 232276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806528853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3806528853
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/265.edn_genbits.468712009
Short name T956
Test name
Test status
Simulation time 68531117 ps
CPU time 3.52 seconds
Started Sep 18 09:46:20 AM UTC 24
Finished Sep 18 09:46:24 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468712009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 265.edn_genbits.468712009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/266.edn_genbits.1892109469
Short name T950
Test name
Test status
Simulation time 133932321 ps
CPU time 1.93 seconds
Started Sep 18 09:46:20 AM UTC 24
Finished Sep 18 09:46:23 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892109469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1892109469
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/267.edn_genbits.2455589900
Short name T946
Test name
Test status
Simulation time 163849393 ps
CPU time 1.49 seconds
Started Sep 18 09:46:20 AM UTC 24
Finished Sep 18 09:46:22 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455589900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2455589900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/268.edn_genbits.3700843680
Short name T948
Test name
Test status
Simulation time 39687674 ps
CPU time 1.63 seconds
Started Sep 18 09:46:20 AM UTC 24
Finished Sep 18 09:46:22 AM UTC 24
Peak memory 229212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700843680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3700843680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/269.edn_genbits.3364415257
Short name T949
Test name
Test status
Simulation time 72839400 ps
CPU time 1.79 seconds
Started Sep 18 09:46:20 AM UTC 24
Finished Sep 18 09:46:23 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364415257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3364415257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_alert.1405868794
Short name T432
Test name
Test status
Simulation time 39668001 ps
CPU time 1.51 seconds
Started Sep 18 09:41:43 AM UTC 24
Finished Sep 18 09:41:45 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405868794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.1405868794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_alert_test.2632405978
Short name T433
Test name
Test status
Simulation time 32427729 ps
CPU time 1.22 seconds
Started Sep 18 09:41:44 AM UTC 24
Finished Sep 18 09:41:46 AM UTC 24
Peak memory 216896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632405978 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2632405978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_disable.1371073875
Short name T431
Test name
Test status
Simulation time 13979100 ps
CPU time 1.33 seconds
Started Sep 18 09:41:43 AM UTC 24
Finished Sep 18 09:41:45 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371073875 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1371073875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_err.1061375124
Short name T149
Test name
Test status
Simulation time 38826633 ps
CPU time 1.48 seconds
Started Sep 18 09:41:43 AM UTC 24
Finished Sep 18 09:41:45 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061375124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.1061375124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_genbits.195015819
Short name T103
Test name
Test status
Simulation time 47230180 ps
CPU time 1.72 seconds
Started Sep 18 09:41:41 AM UTC 24
Finished Sep 18 09:41:43 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195015819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_genbits.195015819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_intr.3711178152
Short name T430
Test name
Test status
Simulation time 38419580 ps
CPU time 1.21 seconds
Started Sep 18 09:41:43 AM UTC 24
Finished Sep 18 09:41:45 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711178152 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.3711178152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_smoke.643747233
Short name T429
Test name
Test status
Simulation time 24471509 ps
CPU time 1.32 seconds
Started Sep 18 09:41:40 AM UTC 24
Finished Sep 18 09:41:43 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643747233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.edn_smoke.643747233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/27.edn_stress_all.2216813475
Short name T437
Test name
Test status
Simulation time 249297201 ps
CPU time 7.58 seconds
Started Sep 18 09:41:42 AM UTC 24
Finished Sep 18 09:41:50 AM UTC 24
Peak memory 228028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216813475 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2216813475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/270.edn_genbits.3399141250
Short name T953
Test name
Test status
Simulation time 45246522 ps
CPU time 1.94 seconds
Started Sep 18 09:46:21 AM UTC 24
Finished Sep 18 09:46:24 AM UTC 24
Peak memory 229264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399141250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3399141250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/271.edn_genbits.1246020492
Short name T955
Test name
Test status
Simulation time 47955750 ps
CPU time 2.17 seconds
Started Sep 18 09:46:21 AM UTC 24
Finished Sep 18 09:46:24 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246020492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1246020492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/272.edn_genbits.1840175256
Short name T951
Test name
Test status
Simulation time 37679338 ps
CPU time 1.42 seconds
Started Sep 18 09:46:21 AM UTC 24
Finished Sep 18 09:46:23 AM UTC 24
Peak memory 229264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840175256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1840175256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/273.edn_genbits.3931168153
Short name T952
Test name
Test status
Simulation time 105595250 ps
CPU time 1.52 seconds
Started Sep 18 09:46:21 AM UTC 24
Finished Sep 18 09:46:24 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931168153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3931168153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/274.edn_genbits.828916284
Short name T954
Test name
Test status
Simulation time 96669948 ps
CPU time 1.81 seconds
Started Sep 18 09:46:21 AM UTC 24
Finished Sep 18 09:46:24 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828916284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 274.edn_genbits.828916284
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/275.edn_genbits.3021191082
Short name T960
Test name
Test status
Simulation time 113990364 ps
CPU time 3.56 seconds
Started Sep 18 09:46:21 AM UTC 24
Finished Sep 18 09:46:26 AM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021191082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3021191082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/276.edn_genbits.3071532024
Short name T957
Test name
Test status
Simulation time 52997215 ps
CPU time 1.56 seconds
Started Sep 18 09:46:22 AM UTC 24
Finished Sep 18 09:46:25 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071532024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3071532024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/277.edn_genbits.587329952
Short name T962
Test name
Test status
Simulation time 105698689 ps
CPU time 2.86 seconds
Started Sep 18 09:46:22 AM UTC 24
Finished Sep 18 09:46:26 AM UTC 24
Peak memory 232212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587329952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 277.edn_genbits.587329952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/279.edn_genbits.1552597145
Short name T958
Test name
Test status
Simulation time 85468965 ps
CPU time 1.52 seconds
Started Sep 18 09:46:22 AM UTC 24
Finished Sep 18 09:46:25 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552597145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1552597145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_alert_test.2828051614
Short name T253
Test name
Test status
Simulation time 19681478 ps
CPU time 1.19 seconds
Started Sep 18 09:41:51 AM UTC 24
Finished Sep 18 09:41:53 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828051614 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2828051614
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_disable.1739532740
Short name T223
Test name
Test status
Simulation time 87499977 ps
CPU time 1.42 seconds
Started Sep 18 09:41:48 AM UTC 24
Finished Sep 18 09:41:50 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739532740 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1739532740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.2783055010
Short name T145
Test name
Test status
Simulation time 91022738 ps
CPU time 1.91 seconds
Started Sep 18 09:41:50 AM UTC 24
Finished Sep 18 09:41:53 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783055010 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2783055010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_err.2387995786
Short name T155
Test name
Test status
Simulation time 26027971 ps
CPU time 1.73 seconds
Started Sep 18 09:41:48 AM UTC 24
Finished Sep 18 09:41:50 AM UTC 24
Peak memory 246796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387995786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.2387995786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_genbits.155944328
Short name T313
Test name
Test status
Simulation time 8770456266 ps
CPU time 131.41 seconds
Started Sep 18 09:41:46 AM UTC 24
Finished Sep 18 09:44:00 AM UTC 24
Peak memory 232220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155944328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_genbits.155944328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_intr.477180123
Short name T435
Test name
Test status
Simulation time 38369721 ps
CPU time 1.22 seconds
Started Sep 18 09:41:46 AM UTC 24
Finished Sep 18 09:41:49 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477180123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.477180123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_smoke.4167042067
Short name T434
Test name
Test status
Simulation time 51110217 ps
CPU time 1.27 seconds
Started Sep 18 09:41:44 AM UTC 24
Finished Sep 18 09:41:46 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167042067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.4167042067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_stress_all.2436194788
Short name T436
Test name
Test status
Simulation time 120609772 ps
CPU time 2.49 seconds
Started Sep 18 09:41:46 AM UTC 24
Finished Sep 18 09:41:50 AM UTC 24
Peak memory 228168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436194788 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2436194788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.2224225135
Short name T492
Test name
Test status
Simulation time 2402991134 ps
CPU time 67.93 seconds
Started Sep 18 09:41:46 AM UTC 24
Finished Sep 18 09:42:56 AM UTC 24
Peak memory 232348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2224225135 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all
_with_rand_reset.2224225135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/280.edn_genbits.2754709849
Short name T963
Test name
Test status
Simulation time 36564011 ps
CPU time 1.91 seconds
Started Sep 18 09:46:23 AM UTC 24
Finished Sep 18 09:46:26 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754709849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2754709849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/281.edn_genbits.3015335875
Short name T961
Test name
Test status
Simulation time 28752176 ps
CPU time 1.53 seconds
Started Sep 18 09:46:24 AM UTC 24
Finished Sep 18 09:46:26 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015335875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3015335875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/282.edn_genbits.2356563603
Short name T965
Test name
Test status
Simulation time 46943715 ps
CPU time 2.12 seconds
Started Sep 18 09:46:24 AM UTC 24
Finished Sep 18 09:46:27 AM UTC 24
Peak memory 228056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356563603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2356563603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/283.edn_genbits.2991952122
Short name T964
Test name
Test status
Simulation time 38362507 ps
CPU time 2.02 seconds
Started Sep 18 09:46:24 AM UTC 24
Finished Sep 18 09:46:27 AM UTC 24
Peak memory 232204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991952122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2991952122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/285.edn_genbits.1527863407
Short name T967
Test name
Test status
Simulation time 33237144 ps
CPU time 1.52 seconds
Started Sep 18 09:46:25 AM UTC 24
Finished Sep 18 09:46:27 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527863407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1527863407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/286.edn_genbits.1211226044
Short name T968
Test name
Test status
Simulation time 71876019 ps
CPU time 1.55 seconds
Started Sep 18 09:46:25 AM UTC 24
Finished Sep 18 09:46:27 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211226044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1211226044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/287.edn_genbits.2640532575
Short name T976
Test name
Test status
Simulation time 146220131 ps
CPU time 4.53 seconds
Started Sep 18 09:46:25 AM UTC 24
Finished Sep 18 09:46:30 AM UTC 24
Peak memory 230316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640532575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2640532575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/288.edn_genbits.2823579863
Short name T966
Test name
Test status
Simulation time 65008406 ps
CPU time 1.37 seconds
Started Sep 18 09:46:25 AM UTC 24
Finished Sep 18 09:46:27 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823579863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2823579863
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/289.edn_genbits.3930649057
Short name T969
Test name
Test status
Simulation time 45476675 ps
CPU time 1.5 seconds
Started Sep 18 09:46:25 AM UTC 24
Finished Sep 18 09:46:27 AM UTC 24
Peak memory 226972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930649057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3930649057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_alert.3541415935
Short name T206
Test name
Test status
Simulation time 24509943 ps
CPU time 1.63 seconds
Started Sep 18 09:41:54 AM UTC 24
Finished Sep 18 09:41:57 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541415935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.3541415935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_alert_test.3568462635
Short name T439
Test name
Test status
Simulation time 13258676 ps
CPU time 1.38 seconds
Started Sep 18 09:41:57 AM UTC 24
Finished Sep 18 09:42:00 AM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568462635 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3568462635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_disable.2246131758
Short name T256
Test name
Test status
Simulation time 29654905 ps
CPU time 1.28 seconds
Started Sep 18 09:41:54 AM UTC 24
Finished Sep 18 09:41:56 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246131758 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2246131758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.664208475
Short name T257
Test name
Test status
Simulation time 32476025 ps
CPU time 1.52 seconds
Started Sep 18 09:41:56 AM UTC 24
Finished Sep 18 09:41:59 AM UTC 24
Peak memory 226908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664208475 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.664208475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_err.3361030885
Short name T164
Test name
Test status
Simulation time 18907670 ps
CPU time 1.67 seconds
Started Sep 18 09:41:54 AM UTC 24
Finished Sep 18 09:41:57 AM UTC 24
Peak memory 238224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361030885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.3361030885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_genbits.2198175710
Short name T255
Test name
Test status
Simulation time 20687046 ps
CPU time 1.66 seconds
Started Sep 18 09:41:51 AM UTC 24
Finished Sep 18 09:41:54 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198175710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2198175710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_intr.3580977441
Short name T112
Test name
Test status
Simulation time 29000827 ps
CPU time 1.17 seconds
Started Sep 18 09:41:53 AM UTC 24
Finished Sep 18 09:41:55 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580977441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.3580977441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_smoke.2203073832
Short name T254
Test name
Test status
Simulation time 77076715 ps
CPU time 1.24 seconds
Started Sep 18 09:41:51 AM UTC 24
Finished Sep 18 09:41:53 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203073832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.2203073832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_stress_all.3027272510
Short name T438
Test name
Test status
Simulation time 504570670 ps
CPU time 6.73 seconds
Started Sep 18 09:41:51 AM UTC 24
Finished Sep 18 09:41:59 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027272510 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3027272510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.2472642519
Short name T245
Test name
Test status
Simulation time 1725595773 ps
CPU time 40.55 seconds
Started Sep 18 09:41:51 AM UTC 24
Finished Sep 18 09:42:33 AM UTC 24
Peak memory 230288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2472642519 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all
_with_rand_reset.2472642519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/290.edn_genbits.1876017760
Short name T970
Test name
Test status
Simulation time 125889284 ps
CPU time 1.6 seconds
Started Sep 18 09:46:25 AM UTC 24
Finished Sep 18 09:46:28 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876017760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1876017760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/291.edn_genbits.3144559267
Short name T975
Test name
Test status
Simulation time 274027075 ps
CPU time 3.3 seconds
Started Sep 18 09:46:26 AM UTC 24
Finished Sep 18 09:46:30 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144559267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3144559267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/292.edn_genbits.2172588919
Short name T971
Test name
Test status
Simulation time 106608301 ps
CPU time 1.98 seconds
Started Sep 18 09:46:26 AM UTC 24
Finished Sep 18 09:46:29 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172588919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2172588919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/293.edn_genbits.2369550368
Short name T972
Test name
Test status
Simulation time 53616238 ps
CPU time 2.13 seconds
Started Sep 18 09:46:26 AM UTC 24
Finished Sep 18 09:46:29 AM UTC 24
Peak memory 230280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369550368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2369550368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/294.edn_genbits.3726123251
Short name T973
Test name
Test status
Simulation time 84757408 ps
CPU time 1.66 seconds
Started Sep 18 09:46:27 AM UTC 24
Finished Sep 18 09:46:30 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726123251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3726123251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/295.edn_genbits.433465789
Short name T978
Test name
Test status
Simulation time 44716898 ps
CPU time 2.28 seconds
Started Sep 18 09:46:27 AM UTC 24
Finished Sep 18 09:46:31 AM UTC 24
Peak memory 230152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433465789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 295.edn_genbits.433465789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/296.edn_genbits.787129208
Short name T974
Test name
Test status
Simulation time 48124285 ps
CPU time 1.76 seconds
Started Sep 18 09:46:27 AM UTC 24
Finished Sep 18 09:46:30 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787129208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 296.edn_genbits.787129208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/297.edn_genbits.1748900942
Short name T977
Test name
Test status
Simulation time 70028413 ps
CPU time 2.04 seconds
Started Sep 18 09:46:27 AM UTC 24
Finished Sep 18 09:46:30 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748900942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1748900942
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/298.edn_genbits.1451468358
Short name T980
Test name
Test status
Simulation time 55414936 ps
CPU time 2.36 seconds
Started Sep 18 09:46:27 AM UTC 24
Finished Sep 18 09:46:31 AM UTC 24
Peak memory 230096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451468358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1451468358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/299.edn_genbits.3057766527
Short name T979
Test name
Test status
Simulation time 42050603 ps
CPU time 2.27 seconds
Started Sep 18 09:46:28 AM UTC 24
Finished Sep 18 09:46:31 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057766527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3057766527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_alert_test.1153428767
Short name T340
Test name
Test status
Simulation time 68571985 ps
CPU time 1.14 seconds
Started Sep 18 09:39:42 AM UTC 24
Finished Sep 18 09:39:44 AM UTC 24
Peak memory 216892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153428767 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1153428767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_disable.3419497195
Short name T47
Test name
Test status
Simulation time 42157505 ps
CPU time 1.28 seconds
Started Sep 18 09:39:40 AM UTC 24
Finished Sep 18 09:39:42 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419497195 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3419497195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.1994127384
Short name T64
Test name
Test status
Simulation time 139838863 ps
CPU time 1.34 seconds
Started Sep 18 09:39:40 AM UTC 24
Finished Sep 18 09:39:42 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994127384 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.1994127384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_err.2453339940
Short name T8
Test name
Test status
Simulation time 22468488 ps
CPU time 1.55 seconds
Started Sep 18 09:39:40 AM UTC 24
Finished Sep 18 09:39:42 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453339940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.2453339940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_intr.328451315
Short name T63
Test name
Test status
Simulation time 35000731 ps
CPU time 1.41 seconds
Started Sep 18 09:39:40 AM UTC 24
Finished Sep 18 09:39:42 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328451315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.328451315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_regwen.3204363330
Short name T251
Test name
Test status
Simulation time 108649865 ps
CPU time 1.27 seconds
Started Sep 18 09:39:35 AM UTC 24
Finished Sep 18 09:39:38 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204363330 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.3204363330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_sec_cm.2726503487
Short name T53
Test name
Test status
Simulation time 942084816 ps
CPU time 6.17 seconds
Started Sep 18 09:39:42 AM UTC 24
Finished Sep 18 09:39:49 AM UTC 24
Peak memory 256520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726503487 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2726503487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_smoke.1904624909
Short name T60
Test name
Test status
Simulation time 29648803 ps
CPU time 1.25 seconds
Started Sep 18 09:39:35 AM UTC 24
Finished Sep 18 09:39:38 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904624909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.1904624909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/3.edn_stress_all.2928491003
Short name T128
Test name
Test status
Simulation time 130391352 ps
CPU time 4.84 seconds
Started Sep 18 09:39:38 AM UTC 24
Finished Sep 18 09:39:44 AM UTC 24
Peak memory 232216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928491003 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2928491003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_alert.3381931714
Short name T200
Test name
Test status
Simulation time 22973522 ps
CPU time 1.79 seconds
Started Sep 18 09:42:01 AM UTC 24
Finished Sep 18 09:42:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381931714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.3381931714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_alert_test.1817098728
Short name T445
Test name
Test status
Simulation time 24849452 ps
CPU time 1.43 seconds
Started Sep 18 09:42:04 AM UTC 24
Finished Sep 18 09:42:06 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817098728 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1817098728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_disable.3001429
Short name T444
Test name
Test status
Simulation time 23823808 ps
CPU time 1.16 seconds
Started Sep 18 09:42:03 AM UTC 24
Finished Sep 18 09:42:05 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001429 -assert nopostproc +UVM_TESTNAME=edn_disabl
e_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3001429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1631687777
Short name T446
Test name
Test status
Simulation time 109923864 ps
CPU time 1.49 seconds
Started Sep 18 09:42:04 AM UTC 24
Finished Sep 18 09:42:06 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631687777 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1631687777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_err.1140099434
Short name T443
Test name
Test status
Simulation time 28264707 ps
CPU time 1.44 seconds
Started Sep 18 09:42:02 AM UTC 24
Finished Sep 18 09:42:04 AM UTC 24
Peak memory 237168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140099434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.1140099434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_genbits.4280057894
Short name T104
Test name
Test status
Simulation time 45041535 ps
CPU time 2.27 seconds
Started Sep 18 09:41:57 AM UTC 24
Finished Sep 18 09:42:01 AM UTC 24
Peak memory 230024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280057894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4280057894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_intr.2282568484
Short name T442
Test name
Test status
Simulation time 53940636 ps
CPU time 1.35 seconds
Started Sep 18 09:42:01 AM UTC 24
Finished Sep 18 09:42:03 AM UTC 24
Peak memory 237172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282568484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.2282568484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_smoke.3059973783
Short name T440
Test name
Test status
Simulation time 16207831 ps
CPU time 1.43 seconds
Started Sep 18 09:41:57 AM UTC 24
Finished Sep 18 09:42:00 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059973783 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_smoke.3059973783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/30.edn_stress_all.112053139
Short name T441
Test name
Test status
Simulation time 55282374 ps
CPU time 1.57 seconds
Started Sep 18 09:42:00 AM UTC 24
Finished Sep 18 09:42:02 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112053139 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.112053139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_alert.901991475
Short name T300
Test name
Test status
Simulation time 34671164 ps
CPU time 1.8 seconds
Started Sep 18 09:42:09 AM UTC 24
Finished Sep 18 09:42:12 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901991475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_alert.901991475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_alert_test.231343560
Short name T451
Test name
Test status
Simulation time 27247852 ps
CPU time 1.38 seconds
Started Sep 18 09:42:13 AM UTC 24
Finished Sep 18 09:42:15 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231343560 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.231343560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_disable.2541935129
Short name T216
Test name
Test status
Simulation time 11818654 ps
CPU time 1.2 seconds
Started Sep 18 09:42:12 AM UTC 24
Finished Sep 18 09:42:14 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541935129 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2541935129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.2368638623
Short name T452
Test name
Test status
Simulation time 98793197 ps
CPU time 1.69 seconds
Started Sep 18 09:42:13 AM UTC 24
Finished Sep 18 09:42:15 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368638623 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.2368638623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_err.1903471736
Short name T450
Test name
Test status
Simulation time 35540571 ps
CPU time 1.27 seconds
Started Sep 18 09:42:11 AM UTC 24
Finished Sep 18 09:42:14 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903471736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.1903471736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_genbits.2503054192
Short name T46
Test name
Test status
Simulation time 54953740 ps
CPU time 1.76 seconds
Started Sep 18 09:42:06 AM UTC 24
Finished Sep 18 09:42:09 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503054192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2503054192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_intr.2382611518
Short name T449
Test name
Test status
Simulation time 32194961 ps
CPU time 1.35 seconds
Started Sep 18 09:42:08 AM UTC 24
Finished Sep 18 09:42:11 AM UTC 24
Peak memory 227028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382611518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.2382611518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_smoke.1923281286
Short name T447
Test name
Test status
Simulation time 27423111 ps
CPU time 1.7 seconds
Started Sep 18 09:42:05 AM UTC 24
Finished Sep 18 09:42:08 AM UTC 24
Peak memory 227148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923281286 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.1923281286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/31.edn_stress_all.3572659376
Short name T448
Test name
Test status
Simulation time 53850489 ps
CPU time 2.26 seconds
Started Sep 18 09:42:07 AM UTC 24
Finished Sep 18 09:42:10 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572659376 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3572659376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_alert.2247885745
Short name T157
Test name
Test status
Simulation time 48006446 ps
CPU time 1.82 seconds
Started Sep 18 09:42:16 AM UTC 24
Finished Sep 18 09:42:19 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247885745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.2247885745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_alert_test.3925597713
Short name T458
Test name
Test status
Simulation time 22635485 ps
CPU time 1.37 seconds
Started Sep 18 09:42:19 AM UTC 24
Finished Sep 18 09:42:22 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925597713 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3925597713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_disable.1874526427
Short name T231
Test name
Test status
Simulation time 131263055 ps
CPU time 1.16 seconds
Started Sep 18 09:42:18 AM UTC 24
Finished Sep 18 09:42:20 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874526427 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1874526427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1328686710
Short name T459
Test name
Test status
Simulation time 173090106 ps
CPU time 1.68 seconds
Started Sep 18 09:42:19 AM UTC 24
Finished Sep 18 09:42:22 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328686710 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1328686710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_err.1912546626
Short name T165
Test name
Test status
Simulation time 45015641 ps
CPU time 1.66 seconds
Started Sep 18 09:42:18 AM UTC 24
Finished Sep 18 09:42:21 AM UTC 24
Peak memory 242836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912546626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.1912546626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_genbits.704659578
Short name T455
Test name
Test status
Simulation time 64834937 ps
CPU time 1.81 seconds
Started Sep 18 09:42:15 AM UTC 24
Finished Sep 18 09:42:18 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704659578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_genbits.704659578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_intr.3350124732
Short name T456
Test name
Test status
Simulation time 27711820 ps
CPU time 1.3 seconds
Started Sep 18 09:42:16 AM UTC 24
Finished Sep 18 09:42:18 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350124732 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.3350124732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_smoke.955091743
Short name T454
Test name
Test status
Simulation time 17646335 ps
CPU time 1.45 seconds
Started Sep 18 09:42:15 AM UTC 24
Finished Sep 18 09:42:17 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955091743 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.edn_smoke.955091743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_stress_all.3200893304
Short name T457
Test name
Test status
Simulation time 598240097 ps
CPU time 4.51 seconds
Started Sep 18 09:42:16 AM UTC 24
Finished Sep 18 09:42:21 AM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200893304 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3200893304
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.104898793
Short name T586
Test name
Test status
Simulation time 17084230370 ps
CPU time 123.7 seconds
Started Sep 18 09:42:16 AM UTC 24
Finished Sep 18 09:44:22 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=104898793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_
with_rand_reset.104898793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_alert.561168492
Short name T163
Test name
Test status
Simulation time 154350038 ps
CPU time 1.48 seconds
Started Sep 18 09:42:23 AM UTC 24
Finished Sep 18 09:42:25 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561168492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_alert.561168492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_alert_test.646451889
Short name T462
Test name
Test status
Simulation time 48671294 ps
CPU time 1.41 seconds
Started Sep 18 09:42:26 AM UTC 24
Finished Sep 18 09:42:28 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646451889 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.646451889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_disable.1932925946
Short name T232
Test name
Test status
Simulation time 33624927 ps
CPU time 0.95 seconds
Started Sep 18 09:42:26 AM UTC 24
Finished Sep 18 09:42:28 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932925946 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1932925946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.3447409751
Short name T463
Test name
Test status
Simulation time 53851235 ps
CPU time 1.7 seconds
Started Sep 18 09:42:26 AM UTC 24
Finished Sep 18 09:42:29 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447409751 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.3447409751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_err.2281961869
Short name T461
Test name
Test status
Simulation time 32266727 ps
CPU time 1.36 seconds
Started Sep 18 09:42:24 AM UTC 24
Finished Sep 18 09:42:26 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281961869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.2281961869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_intr.1735052731
Short name T113
Test name
Test status
Simulation time 20491902 ps
CPU time 1.64 seconds
Started Sep 18 09:42:23 AM UTC 24
Finished Sep 18 09:42:25 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735052731 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.1735052731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_smoke.3734629210
Short name T460
Test name
Test status
Simulation time 18095586 ps
CPU time 1.33 seconds
Started Sep 18 09:42:20 AM UTC 24
Finished Sep 18 09:42:23 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734629210 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.3734629210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/33.edn_stress_all.3590524909
Short name T464
Test name
Test status
Simulation time 519171575 ps
CPU time 7.08 seconds
Started Sep 18 09:42:22 AM UTC 24
Finished Sep 18 09:42:30 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590524909 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3590524909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_alert.78819770
Short name T153
Test name
Test status
Simulation time 66121805 ps
CPU time 1.52 seconds
Started Sep 18 09:42:29 AM UTC 24
Finished Sep 18 09:42:32 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78819770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_alert.78819770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_alert_test.4043772076
Short name T471
Test name
Test status
Simulation time 15373218 ps
CPU time 1.39 seconds
Started Sep 18 09:42:33 AM UTC 24
Finished Sep 18 09:42:35 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043772076 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4043772076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_disable.2340476986
Short name T467
Test name
Test status
Simulation time 103388115 ps
CPU time 1.1 seconds
Started Sep 18 09:42:31 AM UTC 24
Finished Sep 18 09:42:33 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340476986 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2340476986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.98716748
Short name T469
Test name
Test status
Simulation time 45231491 ps
CPU time 1.94 seconds
Started Sep 18 09:42:32 AM UTC 24
Finished Sep 18 09:42:35 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98716748 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.98716748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_err.806651578
Short name T468
Test name
Test status
Simulation time 26801324 ps
CPU time 1.4 seconds
Started Sep 18 09:42:31 AM UTC 24
Finished Sep 18 09:42:33 AM UTC 24
Peak memory 237344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806651578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.edn_err.806651578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_genbits.3737396658
Short name T336
Test name
Test status
Simulation time 259395053 ps
CPU time 2.97 seconds
Started Sep 18 09:42:27 AM UTC 24
Finished Sep 18 09:42:31 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737396658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3737396658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_intr.1774549451
Short name T328
Test name
Test status
Simulation time 25483477 ps
CPU time 1.4 seconds
Started Sep 18 09:42:29 AM UTC 24
Finished Sep 18 09:42:32 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774549451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.1774549451
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_smoke.675655557
Short name T465
Test name
Test status
Simulation time 31400079 ps
CPU time 1.52 seconds
Started Sep 18 09:42:27 AM UTC 24
Finished Sep 18 09:42:30 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675655557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_smoke.675655557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/34.edn_stress_all.1990505599
Short name T466
Test name
Test status
Simulation time 339131263 ps
CPU time 2.31 seconds
Started Sep 18 09:42:28 AM UTC 24
Finished Sep 18 09:42:32 AM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990505599 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1990505599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_alert_test.423828533
Short name T475
Test name
Test status
Simulation time 30431884 ps
CPU time 1.35 seconds
Started Sep 18 09:42:37 AM UTC 24
Finished Sep 18 09:42:40 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423828533 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.423828533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_disable.1228791836
Short name T473
Test name
Test status
Simulation time 23488456 ps
CPU time 1.13 seconds
Started Sep 18 09:42:36 AM UTC 24
Finished Sep 18 09:42:38 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228791836 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1228791836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.1167467172
Short name T474
Test name
Test status
Simulation time 65138174 ps
CPU time 1.37 seconds
Started Sep 18 09:42:36 AM UTC 24
Finished Sep 18 09:42:39 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167467172 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.1167467172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_err.2560819483
Short name T181
Test name
Test status
Simulation time 33795260 ps
CPU time 1.19 seconds
Started Sep 18 09:42:36 AM UTC 24
Finished Sep 18 09:42:38 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560819483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.2560819483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_intr.963855368
Short name T472
Test name
Test status
Simulation time 98998573 ps
CPU time 1.37 seconds
Started Sep 18 09:42:34 AM UTC 24
Finished Sep 18 09:42:36 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963855368 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.963855368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_smoke.26874701
Short name T470
Test name
Test status
Simulation time 18465994 ps
CPU time 1.32 seconds
Started Sep 18 09:42:33 AM UTC 24
Finished Sep 18 09:42:35 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26874701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_smoke.26874701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_stress_all.4047712876
Short name T482
Test name
Test status
Simulation time 387597924 ps
CPU time 11.14 seconds
Started Sep 18 09:42:34 AM UTC 24
Finished Sep 18 09:42:46 AM UTC 24
Peak memory 228160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047712876 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4047712876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.1290226346
Short name T247
Test name
Test status
Simulation time 5858852078 ps
CPU time 42.08 seconds
Started Sep 18 09:42:34 AM UTC 24
Finished Sep 18 09:43:17 AM UTC 24
Peak memory 230300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1290226346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.1290226346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_alert.3265044978
Short name T479
Test name
Test status
Simulation time 26106707 ps
CPU time 1.6 seconds
Started Sep 18 09:42:41 AM UTC 24
Finished Sep 18 09:42:43 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265044978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.3265044978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_alert_test.805353064
Short name T483
Test name
Test status
Simulation time 52144670 ps
CPU time 1.24 seconds
Started Sep 18 09:42:44 AM UTC 24
Finished Sep 18 09:42:46 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805353064 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.805353064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.3571904628
Short name T283
Test name
Test status
Simulation time 42009919 ps
CPU time 1.39 seconds
Started Sep 18 09:42:43 AM UTC 24
Finished Sep 18 09:42:45 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571904628 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.3571904628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_err.4151443588
Short name T481
Test name
Test status
Simulation time 22868103 ps
CPU time 1.61 seconds
Started Sep 18 09:42:42 AM UTC 24
Finished Sep 18 09:42:44 AM UTC 24
Peak memory 238224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151443588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.4151443588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_genbits.220782770
Short name T477
Test name
Test status
Simulation time 74772111 ps
CPU time 2.06 seconds
Started Sep 18 09:42:38 AM UTC 24
Finished Sep 18 09:42:41 AM UTC 24
Peak memory 230148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220782770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_genbits.220782770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_intr.4125600714
Short name T478
Test name
Test status
Simulation time 22436642 ps
CPU time 1.45 seconds
Started Sep 18 09:42:40 AM UTC 24
Finished Sep 18 09:42:42 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125600714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.4125600714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_smoke.718144296
Short name T476
Test name
Test status
Simulation time 78232844 ps
CPU time 1.27 seconds
Started Sep 18 09:42:38 AM UTC 24
Finished Sep 18 09:42:41 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718144296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.edn_smoke.718144296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_stress_all.757606309
Short name T480
Test name
Test status
Simulation time 332888626 ps
CPU time 3.1 seconds
Started Sep 18 09:42:40 AM UTC 24
Finished Sep 18 09:42:44 AM UTC 24
Peak memory 228208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757606309 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.757606309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.519040911
Short name T570
Test name
Test status
Simulation time 14484548545 ps
CPU time 86.59 seconds
Started Sep 18 09:42:40 AM UTC 24
Finished Sep 18 09:44:08 AM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=519040911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_
with_rand_reset.519040911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_alert.3431734592
Short name T187
Test name
Test status
Simulation time 49919050 ps
CPU time 1.47 seconds
Started Sep 18 09:42:47 AM UTC 24
Finished Sep 18 09:42:50 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431734592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.3431734592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_alert_test.334015141
Short name T489
Test name
Test status
Simulation time 40067444 ps
CPU time 1.22 seconds
Started Sep 18 09:42:50 AM UTC 24
Finished Sep 18 09:42:52 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334015141 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.334015141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_disable.1869401596
Short name T487
Test name
Test status
Simulation time 10532666 ps
CPU time 1.25 seconds
Started Sep 18 09:42:49 AM UTC 24
Finished Sep 18 09:42:51 AM UTC 24
Peak memory 226936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869401596 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1869401596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.2462214974
Short name T488
Test name
Test status
Simulation time 32377719 ps
CPU time 1.55 seconds
Started Sep 18 09:42:49 AM UTC 24
Finished Sep 18 09:42:51 AM UTC 24
Peak memory 228900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462214974 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.2462214974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_err.1504164260
Short name T208
Test name
Test status
Simulation time 24047937 ps
CPU time 1.46 seconds
Started Sep 18 09:42:48 AM UTC 24
Finished Sep 18 09:42:50 AM UTC 24
Peak memory 246616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504164260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.1504164260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_genbits.3844513510
Short name T106
Test name
Test status
Simulation time 73394789 ps
CPU time 1.58 seconds
Started Sep 18 09:42:45 AM UTC 24
Finished Sep 18 09:42:48 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844513510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3844513510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_intr.3774160288
Short name T486
Test name
Test status
Simulation time 21773196 ps
CPU time 1.65 seconds
Started Sep 18 09:42:47 AM UTC 24
Finished Sep 18 09:42:50 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774160288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.3774160288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_smoke.1126222632
Short name T485
Test name
Test status
Simulation time 18597022 ps
CPU time 1.5 seconds
Started Sep 18 09:42:45 AM UTC 24
Finished Sep 18 09:42:48 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126222632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.1126222632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/37.edn_stress_all.3792283713
Short name T306
Test name
Test status
Simulation time 133145518 ps
CPU time 2.8 seconds
Started Sep 18 09:42:45 AM UTC 24
Finished Sep 18 09:42:49 AM UTC 24
Peak memory 228028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792283713 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3792283713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_alert.4053383628
Short name T167
Test name
Test status
Simulation time 88486744 ps
CPU time 1.56 seconds
Started Sep 18 09:42:52 AM UTC 24
Finished Sep 18 09:42:55 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053383628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_alert.4053383628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_alert_test.28448158
Short name T495
Test name
Test status
Simulation time 26476378 ps
CPU time 1.38 seconds
Started Sep 18 09:42:55 AM UTC 24
Finished Sep 18 09:42:58 AM UTC 24
Peak memory 216892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28448158 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.28448158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_disable.2071696328
Short name T493
Test name
Test status
Simulation time 38983757 ps
CPU time 1.25 seconds
Started Sep 18 09:42:54 AM UTC 24
Finished Sep 18 09:42:56 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071696328 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2071696328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.3884092604
Short name T217
Test name
Test status
Simulation time 99111282 ps
CPU time 1.35 seconds
Started Sep 18 09:42:54 AM UTC 24
Finished Sep 18 09:42:57 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884092604 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.3884092604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_err.1957263225
Short name T218
Test name
Test status
Simulation time 45611377 ps
CPU time 1.63 seconds
Started Sep 18 09:42:53 AM UTC 24
Finished Sep 18 09:42:56 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957263225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.edn_err.1957263225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_genbits.280384251
Short name T107
Test name
Test status
Simulation time 102153717 ps
CPU time 1.64 seconds
Started Sep 18 09:42:51 AM UTC 24
Finished Sep 18 09:42:54 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280384251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.280384251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_intr.157228557
Short name T491
Test name
Test status
Simulation time 23892948 ps
CPU time 1.26 seconds
Started Sep 18 09:42:52 AM UTC 24
Finished Sep 18 09:42:54 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157228557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.157228557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_smoke.2820860065
Short name T490
Test name
Test status
Simulation time 42866972 ps
CPU time 1.37 seconds
Started Sep 18 09:42:51 AM UTC 24
Finished Sep 18 09:42:53 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820860065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.2820860065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/38.edn_stress_all.1634877925
Short name T494
Test name
Test status
Simulation time 616078156 ps
CPU time 5.43 seconds
Started Sep 18 09:42:51 AM UTC 24
Finished Sep 18 09:42:58 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634877925 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1634877925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_alert.2929783964
Short name T499
Test name
Test status
Simulation time 28662092 ps
CPU time 1.82 seconds
Started Sep 18 09:42:58 AM UTC 24
Finished Sep 18 09:43:01 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929783964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.2929783964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_alert_test.152465564
Short name T503
Test name
Test status
Simulation time 32655618 ps
CPU time 1.25 seconds
Started Sep 18 09:43:00 AM UTC 24
Finished Sep 18 09:43:03 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152465564 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.152465564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_disable.2209446750
Short name T500
Test name
Test status
Simulation time 13882890 ps
CPU time 1.31 seconds
Started Sep 18 09:42:59 AM UTC 24
Finished Sep 18 09:43:01 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209446750 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2209446750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.715575331
Short name T502
Test name
Test status
Simulation time 113750323 ps
CPU time 1.54 seconds
Started Sep 18 09:42:59 AM UTC 24
Finished Sep 18 09:43:01 AM UTC 24
Peak memory 231004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715575331 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.715575331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_err.2071758677
Short name T501
Test name
Test status
Simulation time 19135072 ps
CPU time 1.42 seconds
Started Sep 18 09:42:59 AM UTC 24
Finished Sep 18 09:43:01 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071758677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.2071758677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_genbits.3022046332
Short name T497
Test name
Test status
Simulation time 40479058 ps
CPU time 1.93 seconds
Started Sep 18 09:42:57 AM UTC 24
Finished Sep 18 09:42:59 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022046332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3022046332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_intr.2704726561
Short name T498
Test name
Test status
Simulation time 21273042 ps
CPU time 1.72 seconds
Started Sep 18 09:42:58 AM UTC 24
Finished Sep 18 09:43:01 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704726561 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.2704726561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_smoke.763208802
Short name T496
Test name
Test status
Simulation time 27419869 ps
CPU time 1.31 seconds
Started Sep 18 09:42:55 AM UTC 24
Finished Sep 18 09:42:58 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763208802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.edn_smoke.763208802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/39.edn_stress_all.3943851172
Short name T507
Test name
Test status
Simulation time 2233697908 ps
CPU time 7.48 seconds
Started Sep 18 09:42:57 AM UTC 24
Finished Sep 18 09:43:05 AM UTC 24
Peak memory 232196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943851172 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3943851172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_alert.3307311173
Short name T131
Test name
Test status
Simulation time 25967788 ps
CPU time 1.72 seconds
Started Sep 18 09:39:47 AM UTC 24
Finished Sep 18 09:39:49 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307311173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.3307311173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_alert_test.514895155
Short name T342
Test name
Test status
Simulation time 23918308 ps
CPU time 1.26 seconds
Started Sep 18 09:39:51 AM UTC 24
Finished Sep 18 09:39:53 AM UTC 24
Peak memory 216772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514895155 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.514895155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_disable.3476365648
Short name T40
Test name
Test status
Simulation time 20962087 ps
CPU time 1.18 seconds
Started Sep 18 09:39:49 AM UTC 24
Finished Sep 18 09:39:51 AM UTC 24
Peak memory 227016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476365648 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3476365648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.2997654196
Short name T45
Test name
Test status
Simulation time 37247229 ps
CPU time 1.67 seconds
Started Sep 18 09:39:49 AM UTC 24
Finished Sep 18 09:39:51 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997654196 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.2997654196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_err.1750037227
Short name T54
Test name
Test status
Simulation time 20742527 ps
CPU time 1.83 seconds
Started Sep 18 09:39:49 AM UTC 24
Finished Sep 18 09:39:51 AM UTC 24
Peak memory 247148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750037227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.1750037227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_genbits.2907421918
Short name T108
Test name
Test status
Simulation time 263106806 ps
CPU time 4.94 seconds
Started Sep 18 09:39:44 AM UTC 24
Finished Sep 18 09:39:50 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907421918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2907421918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_intr.568045009
Short name T125
Test name
Test status
Simulation time 24795010 ps
CPU time 1.38 seconds
Started Sep 18 09:39:44 AM UTC 24
Finished Sep 18 09:39:47 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568045009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.568045009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_regwen.578920723
Short name T124
Test name
Test status
Simulation time 30053997 ps
CPU time 1.34 seconds
Started Sep 18 09:39:44 AM UTC 24
Finished Sep 18 09:39:47 AM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578920723 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_regwen.578920723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_smoke.531257547
Short name T341
Test name
Test status
Simulation time 39623571 ps
CPU time 1.29 seconds
Started Sep 18 09:39:44 AM UTC 24
Finished Sep 18 09:39:47 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531257547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_smoke.531257547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_stress_all.3537124450
Short name T116
Test name
Test status
Simulation time 375425542 ps
CPU time 9.35 seconds
Started Sep 18 09:39:44 AM UTC 24
Finished Sep 18 09:39:55 AM UTC 24
Peak memory 232144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537124450 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3537124450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.1766954707
Short name T234
Test name
Test status
Simulation time 2787469453 ps
CPU time 76.68 seconds
Started Sep 18 09:39:44 AM UTC 24
Finished Sep 18 09:41:03 AM UTC 24
Peak memory 230288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1766954707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_
with_rand_reset.1766954707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_alert_test.1451618937
Short name T511
Test name
Test status
Simulation time 47832667 ps
CPU time 1.37 seconds
Started Sep 18 09:43:06 AM UTC 24
Finished Sep 18 09:43:09 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451618937 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1451618937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_disable.1694228553
Short name T509
Test name
Test status
Simulation time 23892983 ps
CPU time 1.4 seconds
Started Sep 18 09:43:05 AM UTC 24
Finished Sep 18 09:43:07 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694228553 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1694228553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.2254452663
Short name T510
Test name
Test status
Simulation time 76628714 ps
CPU time 1.42 seconds
Started Sep 18 09:43:06 AM UTC 24
Finished Sep 18 09:43:08 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254452663 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.2254452663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_err.1019136911
Short name T166
Test name
Test status
Simulation time 19393575 ps
CPU time 1.71 seconds
Started Sep 18 09:43:04 AM UTC 24
Finished Sep 18 09:43:08 AM UTC 24
Peak memory 238324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019136911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.1019136911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_genbits.3245762717
Short name T505
Test name
Test status
Simulation time 27407863 ps
CPU time 1.76 seconds
Started Sep 18 09:43:01 AM UTC 24
Finished Sep 18 09:43:04 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245762717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3245762717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_intr.1815481480
Short name T506
Test name
Test status
Simulation time 28199676 ps
CPU time 1.31 seconds
Started Sep 18 09:43:02 AM UTC 24
Finished Sep 18 09:43:05 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815481480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.1815481480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_smoke.2383372572
Short name T504
Test name
Test status
Simulation time 31781462 ps
CPU time 1.3 seconds
Started Sep 18 09:43:01 AM UTC 24
Finished Sep 18 09:43:03 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383372572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.2383372572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_stress_all.50838912
Short name T508
Test name
Test status
Simulation time 118241962 ps
CPU time 3.94 seconds
Started Sep 18 09:43:02 AM UTC 24
Finished Sep 18 09:43:07 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50838912 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.50838912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.295288581
Short name T606
Test name
Test status
Simulation time 7426868193 ps
CPU time 90.29 seconds
Started Sep 18 09:43:02 AM UTC 24
Finished Sep 18 09:44:35 AM UTC 24
Peak memory 230460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=295288581 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_
with_rand_reset.295288581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_alert.2491406556
Short name T513
Test name
Test status
Simulation time 22172963 ps
CPU time 1.3 seconds
Started Sep 18 09:43:10 AM UTC 24
Finished Sep 18 09:43:12 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491406556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.2491406556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_alert_test.130404370
Short name T515
Test name
Test status
Simulation time 31654093 ps
CPU time 1.25 seconds
Started Sep 18 09:43:13 AM UTC 24
Finished Sep 18 09:43:16 AM UTC 24
Peak memory 216900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130404370 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.130404370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.3418032677
Short name T516
Test name
Test status
Simulation time 28521818 ps
CPU time 1.52 seconds
Started Sep 18 09:43:13 AM UTC 24
Finished Sep 18 09:43:16 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418032677 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.3418032677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_err.3021018208
Short name T171
Test name
Test status
Simulation time 34630041 ps
CPU time 1.42 seconds
Started Sep 18 09:43:11 AM UTC 24
Finished Sep 18 09:43:14 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021018208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.3021018208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_genbits.3678183098
Short name T339
Test name
Test status
Simulation time 57532921 ps
CPU time 2.46 seconds
Started Sep 18 09:43:08 AM UTC 24
Finished Sep 18 09:43:12 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678183098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3678183098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_intr.3056309999
Short name T514
Test name
Test status
Simulation time 21260329 ps
CPU time 1.57 seconds
Started Sep 18 09:43:10 AM UTC 24
Finished Sep 18 09:43:13 AM UTC 24
Peak memory 238348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056309999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.3056309999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_smoke.515124626
Short name T512
Test name
Test status
Simulation time 40441378 ps
CPU time 1.36 seconds
Started Sep 18 09:43:07 AM UTC 24
Finished Sep 18 09:43:10 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515124626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.edn_smoke.515124626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_stress_all.4266492903
Short name T518
Test name
Test status
Simulation time 819284727 ps
CPU time 6.58 seconds
Started Sep 18 09:43:09 AM UTC 24
Finished Sep 18 09:43:17 AM UTC 24
Peak memory 232132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266492903 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4266492903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.3908430080
Short name T602
Test name
Test status
Simulation time 28047544678 ps
CPU time 81.8 seconds
Started Sep 18 09:43:09 AM UTC 24
Finished Sep 18 09:44:33 AM UTC 24
Peak memory 230264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3908430080 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all
_with_rand_reset.3908430080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_alert.3679912190
Short name T520
Test name
Test status
Simulation time 108411742 ps
CPU time 1.64 seconds
Started Sep 18 09:43:18 AM UTC 24
Finished Sep 18 09:43:20 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679912190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_alert.3679912190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_alert_test.467481650
Short name T522
Test name
Test status
Simulation time 17252406 ps
CPU time 1.42 seconds
Started Sep 18 09:43:21 AM UTC 24
Finished Sep 18 09:43:24 AM UTC 24
Peak memory 227348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467481650 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.467481650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_disable.3512324752
Short name T521
Test name
Test status
Simulation time 48891346 ps
CPU time 1.33 seconds
Started Sep 18 09:43:20 AM UTC 24
Finished Sep 18 09:43:22 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512324752 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3512324752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.780769971
Short name T523
Test name
Test status
Simulation time 72158415 ps
CPU time 1.44 seconds
Started Sep 18 09:43:21 AM UTC 24
Finished Sep 18 09:43:24 AM UTC 24
Peak memory 226908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780769971 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.780769971
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_err.3915023231
Short name T214
Test name
Test status
Simulation time 19403323 ps
CPU time 1.66 seconds
Started Sep 18 09:43:19 AM UTC 24
Finished Sep 18 09:43:22 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915023231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.3915023231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_genbits.23090583
Short name T325
Test name
Test status
Simulation time 55087522 ps
CPU time 2.04 seconds
Started Sep 18 09:43:16 AM UTC 24
Finished Sep 18 09:43:20 AM UTC 24
Peak memory 230228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23090583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.edn_genbits.23090583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_intr.417313180
Short name T519
Test name
Test status
Simulation time 26460585 ps
CPU time 1.53 seconds
Started Sep 18 09:43:18 AM UTC 24
Finished Sep 18 09:43:20 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417313180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.417313180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_smoke.1219730531
Short name T517
Test name
Test status
Simulation time 48554454 ps
CPU time 1.4 seconds
Started Sep 18 09:43:14 AM UTC 24
Finished Sep 18 09:43:17 AM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219730531 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_smoke.1219730531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_stress_all.4260614730
Short name T329
Test name
Test status
Simulation time 154406618 ps
CPU time 2.19 seconds
Started Sep 18 09:43:17 AM UTC 24
Finished Sep 18 09:43:20 AM UTC 24
Peak memory 228052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260614730 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4260614730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.158729662
Short name T248
Test name
Test status
Simulation time 8518125374 ps
CPU time 48.57 seconds
Started Sep 18 09:43:17 AM UTC 24
Finished Sep 18 09:44:07 AM UTC 24
Peak memory 230288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=158729662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_
with_rand_reset.158729662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_alert.390643454
Short name T301
Test name
Test status
Simulation time 67086378 ps
CPU time 1.76 seconds
Started Sep 18 09:43:24 AM UTC 24
Finished Sep 18 09:43:28 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390643454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.edn_alert.390643454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_alert_test.4023266177
Short name T529
Test name
Test status
Simulation time 30428244 ps
CPU time 1.25 seconds
Started Sep 18 09:43:29 AM UTC 24
Finished Sep 18 09:43:31 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023266177 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4023266177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.3222761601
Short name T528
Test name
Test status
Simulation time 33476929 ps
CPU time 1.61 seconds
Started Sep 18 09:43:28 AM UTC 24
Finished Sep 18 09:43:30 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222761601 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.3222761601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_err.1525501658
Short name T140
Test name
Test status
Simulation time 49156347 ps
CPU time 1.47 seconds
Started Sep 18 09:43:26 AM UTC 24
Finished Sep 18 09:43:29 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525501658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.1525501658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_genbits.274693129
Short name T525
Test name
Test status
Simulation time 68680810 ps
CPU time 1.9 seconds
Started Sep 18 09:43:22 AM UTC 24
Finished Sep 18 09:43:25 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274693129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_genbits.274693129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_intr.4099406820
Short name T527
Test name
Test status
Simulation time 72446455 ps
CPU time 1.12 seconds
Started Sep 18 09:43:24 AM UTC 24
Finished Sep 18 09:43:27 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099406820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.4099406820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_smoke.1430490557
Short name T524
Test name
Test status
Simulation time 18699498 ps
CPU time 1.45 seconds
Started Sep 18 09:43:21 AM UTC 24
Finished Sep 18 09:43:24 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430490557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.1430490557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_stress_all.821920457
Short name T526
Test name
Test status
Simulation time 109541305 ps
CPU time 1.97 seconds
Started Sep 18 09:43:23 AM UTC 24
Finished Sep 18 09:43:26 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821920457 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.821920457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.224314647
Short name T562
Test name
Test status
Simulation time 4880758473 ps
CPU time 34.5 seconds
Started Sep 18 09:43:24 AM UTC 24
Finished Sep 18 09:44:01 AM UTC 24
Peak memory 230348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=224314647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_
with_rand_reset.224314647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_alert.1027661656
Short name T534
Test name
Test status
Simulation time 27084227 ps
CPU time 1.71 seconds
Started Sep 18 09:43:34 AM UTC 24
Finished Sep 18 09:43:37 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027661656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.1027661656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_alert_test.3969421180
Short name T536
Test name
Test status
Simulation time 13792801 ps
CPU time 1.37 seconds
Started Sep 18 09:43:36 AM UTC 24
Finished Sep 18 09:43:39 AM UTC 24
Peak memory 217332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969421180 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3969421180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_disable.1597032905
Short name T535
Test name
Test status
Simulation time 19677481 ps
CPU time 1.34 seconds
Started Sep 18 09:43:35 AM UTC 24
Finished Sep 18 09:43:37 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597032905 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1597032905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.3900321313
Short name T225
Test name
Test status
Simulation time 35231470 ps
CPU time 1.74 seconds
Started Sep 18 09:43:35 AM UTC 24
Finished Sep 18 09:43:38 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900321313 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.3900321313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_err.888586598
Short name T196
Test name
Test status
Simulation time 19965617 ps
CPU time 1.59 seconds
Started Sep 18 09:43:35 AM UTC 24
Finished Sep 18 09:43:38 AM UTC 24
Peak memory 238220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888586598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.edn_err.888586598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_genbits.3933611248
Short name T317
Test name
Test status
Simulation time 49366576 ps
CPU time 3.01 seconds
Started Sep 18 09:43:31 AM UTC 24
Finished Sep 18 09:43:35 AM UTC 24
Peak memory 232148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933611248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3933611248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_intr.1086711593
Short name T533
Test name
Test status
Simulation time 19601753 ps
CPU time 1.52 seconds
Started Sep 18 09:43:33 AM UTC 24
Finished Sep 18 09:43:35 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086711593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.1086711593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_smoke.720126034
Short name T530
Test name
Test status
Simulation time 42458619 ps
CPU time 1.23 seconds
Started Sep 18 09:43:30 AM UTC 24
Finished Sep 18 09:43:32 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720126034 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.edn_smoke.720126034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_stress_all.2730783643
Short name T532
Test name
Test status
Simulation time 245318084 ps
CPU time 2.35 seconds
Started Sep 18 09:43:31 AM UTC 24
Finished Sep 18 09:43:34 AM UTC 24
Peak memory 217216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730783643 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2730783643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.1830078093
Short name T981
Test name
Test status
Simulation time 65223682534 ps
CPU time 195.01 seconds
Started Sep 18 09:43:32 AM UTC 24
Finished Sep 18 09:46:50 AM UTC 24
Peak memory 232388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1830078093 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all
_with_rand_reset.1830078093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_alert.3339067454
Short name T203
Test name
Test status
Simulation time 66538659 ps
CPU time 1.75 seconds
Started Sep 18 09:43:41 AM UTC 24
Finished Sep 18 09:43:43 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339067454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.3339067454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_alert_test.4019631785
Short name T544
Test name
Test status
Simulation time 17230527 ps
CPU time 1.35 seconds
Started Sep 18 09:43:44 AM UTC 24
Finished Sep 18 09:43:46 AM UTC 24
Peak memory 227612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019631785 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.4019631785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_disable.1253033881
Short name T542
Test name
Test status
Simulation time 22402469 ps
CPU time 1.31 seconds
Started Sep 18 09:43:42 AM UTC 24
Finished Sep 18 09:43:44 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253033881 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1253033881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.4128415955
Short name T543
Test name
Test status
Simulation time 121163864 ps
CPU time 1.72 seconds
Started Sep 18 09:43:43 AM UTC 24
Finished Sep 18 09:43:46 AM UTC 24
Peak memory 231000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128415955 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.4128415955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_err.1587187169
Short name T224
Test name
Test status
Simulation time 25299265 ps
CPU time 1.7 seconds
Started Sep 18 09:43:41 AM UTC 24
Finished Sep 18 09:43:43 AM UTC 24
Peak memory 246616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587187169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.1587187169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_genbits.265360045
Short name T539
Test name
Test status
Simulation time 86498599 ps
CPU time 1.67 seconds
Started Sep 18 09:43:38 AM UTC 24
Finished Sep 18 09:43:41 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265360045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_genbits.265360045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_intr.2552718713
Short name T540
Test name
Test status
Simulation time 42456669 ps
CPU time 1.26 seconds
Started Sep 18 09:43:40 AM UTC 24
Finished Sep 18 09:43:42 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552718713 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.2552718713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_smoke.2917443105
Short name T537
Test name
Test status
Simulation time 43608587 ps
CPU time 1.38 seconds
Started Sep 18 09:43:37 AM UTC 24
Finished Sep 18 09:43:40 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917443105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.2917443105
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/45.edn_stress_all.3699476911
Short name T541
Test name
Test status
Simulation time 859297414 ps
CPU time 3.6 seconds
Started Sep 18 09:43:39 AM UTC 24
Finished Sep 18 09:43:43 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699476911 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3699476911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_alert.1953581631
Short name T550
Test name
Test status
Simulation time 49653054 ps
CPU time 1.74 seconds
Started Sep 18 09:43:47 AM UTC 24
Finished Sep 18 09:43:50 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953581631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.1953581631
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_alert_test.3946442082
Short name T552
Test name
Test status
Simulation time 29996154 ps
CPU time 1.09 seconds
Started Sep 18 09:43:51 AM UTC 24
Finished Sep 18 09:43:53 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946442082 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3946442082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_disable.3736217624
Short name T548
Test name
Test status
Simulation time 32942364 ps
CPU time 1.11 seconds
Started Sep 18 09:43:47 AM UTC 24
Finished Sep 18 09:43:50 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736217624 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3736217624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.273084240
Short name T551
Test name
Test status
Simulation time 56654703 ps
CPU time 1.55 seconds
Started Sep 18 09:43:50 AM UTC 24
Finished Sep 18 09:43:52 AM UTC 24
Peak memory 226908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273084240 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.273084240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_err.3242413910
Short name T549
Test name
Test status
Simulation time 61516740 ps
CPU time 1.2 seconds
Started Sep 18 09:43:47 AM UTC 24
Finished Sep 18 09:43:50 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242413910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.3242413910
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_genbits.721356320
Short name T546
Test name
Test status
Simulation time 34939375 ps
CPU time 1.43 seconds
Started Sep 18 09:43:44 AM UTC 24
Finished Sep 18 09:43:46 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721356320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_genbits.721356320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_intr.2220463833
Short name T547
Test name
Test status
Simulation time 28998395 ps
CPU time 1.25 seconds
Started Sep 18 09:43:46 AM UTC 24
Finished Sep 18 09:43:48 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220463833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.2220463833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_smoke.3343618280
Short name T545
Test name
Test status
Simulation time 17368052 ps
CPU time 1.44 seconds
Started Sep 18 09:43:44 AM UTC 24
Finished Sep 18 09:43:46 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343618280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.3343618280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_stress_all.1195426245
Short name T554
Test name
Test status
Simulation time 1022565798 ps
CPU time 7.48 seconds
Started Sep 18 09:43:45 AM UTC 24
Finished Sep 18 09:43:54 AM UTC 24
Peak memory 230096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195426245 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1195426245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.3486417317
Short name T629
Test name
Test status
Simulation time 4288344484 ps
CPU time 57.75 seconds
Started Sep 18 09:43:46 AM UTC 24
Finished Sep 18 09:44:46 AM UTC 24
Peak memory 228380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3486417317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all
_with_rand_reset.3486417317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_alert.2296524533
Short name T302
Test name
Test status
Simulation time 30848638 ps
CPU time 1.77 seconds
Started Sep 18 09:43:54 AM UTC 24
Finished Sep 18 09:43:57 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296524533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.2296524533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_alert_test.3224214124
Short name T559
Test name
Test status
Simulation time 100045171 ps
CPU time 1.15 seconds
Started Sep 18 09:43:57 AM UTC 24
Finished Sep 18 09:43:59 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224214124 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3224214124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_disable.1881494470
Short name T558
Test name
Test status
Simulation time 12774926 ps
CPU time 1.4 seconds
Started Sep 18 09:43:56 AM UTC 24
Finished Sep 18 09:43:58 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881494470 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1881494470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.1859838877
Short name T560
Test name
Test status
Simulation time 114662230 ps
CPU time 1.63 seconds
Started Sep 18 09:43:57 AM UTC 24
Finished Sep 18 09:44:00 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859838877 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.1859838877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_err.1833520050
Short name T557
Test name
Test status
Simulation time 26574659 ps
CPU time 1.52 seconds
Started Sep 18 09:43:55 AM UTC 24
Finished Sep 18 09:43:58 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833520050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.1833520050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_genbits.1503842682
Short name T311
Test name
Test status
Simulation time 32158553 ps
CPU time 1.68 seconds
Started Sep 18 09:43:51 AM UTC 24
Finished Sep 18 09:43:54 AM UTC 24
Peak memory 231252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503842682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1503842682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_intr.1281992984
Short name T556
Test name
Test status
Simulation time 22205905 ps
CPU time 1.64 seconds
Started Sep 18 09:43:54 AM UTC 24
Finished Sep 18 09:43:56 AM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281992984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.1281992984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_smoke.4079781511
Short name T553
Test name
Test status
Simulation time 19770453 ps
CPU time 1.53 seconds
Started Sep 18 09:43:51 AM UTC 24
Finished Sep 18 09:43:53 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079781511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.4079781511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/47.edn_stress_all.673341964
Short name T555
Test name
Test status
Simulation time 40420030 ps
CPU time 1.55 seconds
Started Sep 18 09:43:53 AM UTC 24
Finished Sep 18 09:43:55 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673341964 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.673341964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_alert.219116837
Short name T566
Test name
Test status
Simulation time 22379403 ps
CPU time 1.41 seconds
Started Sep 18 09:44:02 AM UTC 24
Finished Sep 18 09:44:04 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219116837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.edn_alert.219116837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_alert_test.2794245883
Short name T568
Test name
Test status
Simulation time 55660692 ps
CPU time 1.5 seconds
Started Sep 18 09:44:04 AM UTC 24
Finished Sep 18 09:44:06 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794245883 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2794245883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_disable.4161068241
Short name T192
Test name
Test status
Simulation time 21616490 ps
CPU time 1.28 seconds
Started Sep 18 09:44:03 AM UTC 24
Finished Sep 18 09:44:05 AM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161068241 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4161068241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.4045952544
Short name T226
Test name
Test status
Simulation time 18738106 ps
CPU time 1.3 seconds
Started Sep 18 09:44:04 AM UTC 24
Finished Sep 18 09:44:06 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045952544 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.4045952544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_err.754096087
Short name T567
Test name
Test status
Simulation time 23453347 ps
CPU time 1.73 seconds
Started Sep 18 09:44:02 AM UTC 24
Finished Sep 18 09:44:04 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754096087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.edn_err.754096087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_genbits.2936736958
Short name T563
Test name
Test status
Simulation time 61839634 ps
CPU time 1.7 seconds
Started Sep 18 09:43:59 AM UTC 24
Finished Sep 18 09:44:02 AM UTC 24
Peak memory 229204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936736958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2936736958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_intr.2649284904
Short name T564
Test name
Test status
Simulation time 54798088 ps
CPU time 1.53 seconds
Started Sep 18 09:44:01 AM UTC 24
Finished Sep 18 09:44:03 AM UTC 24
Peak memory 237172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649284904 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.2649284904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_smoke.712498253
Short name T561
Test name
Test status
Simulation time 18434788 ps
CPU time 1.26 seconds
Started Sep 18 09:43:58 AM UTC 24
Finished Sep 18 09:44:01 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712498253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.edn_smoke.712498253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_stress_all.2950162511
Short name T565
Test name
Test status
Simulation time 231144356 ps
CPU time 2.06 seconds
Started Sep 18 09:44:00 AM UTC 24
Finished Sep 18 09:44:04 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950162511 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2950162511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.2636208542
Short name T646
Test name
Test status
Simulation time 5881460387 ps
CPU time 50.14 seconds
Started Sep 18 09:44:01 AM UTC 24
Finished Sep 18 09:44:52 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2636208542 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all
_with_rand_reset.2636208542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_alert.2270653572
Short name T147
Test name
Test status
Simulation time 54256190 ps
CPU time 1.59 seconds
Started Sep 18 09:44:07 AM UTC 24
Finished Sep 18 09:44:10 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270653572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.2270653572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_alert_test.114277572
Short name T574
Test name
Test status
Simulation time 52820967 ps
CPU time 1.25 seconds
Started Sep 18 09:44:11 AM UTC 24
Finished Sep 18 09:44:13 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114277572 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.114277572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_disable.4011230759
Short name T573
Test name
Test status
Simulation time 39508327 ps
CPU time 1.28 seconds
Started Sep 18 09:44:09 AM UTC 24
Finished Sep 18 09:44:12 AM UTC 24
Peak memory 216960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011230759 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4011230759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.3946390013
Short name T576
Test name
Test status
Simulation time 27693470 ps
CPU time 1.74 seconds
Started Sep 18 09:44:10 AM UTC 24
Finished Sep 18 09:44:13 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946390013 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.3946390013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_err.1589179362
Short name T197
Test name
Test status
Simulation time 19608554 ps
CPU time 1.63 seconds
Started Sep 18 09:44:08 AM UTC 24
Finished Sep 18 09:44:11 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589179362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.1589179362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_genbits.1383146190
Short name T571
Test name
Test status
Simulation time 109461164 ps
CPU time 3.37 seconds
Started Sep 18 09:44:05 AM UTC 24
Finished Sep 18 09:44:09 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383146190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1383146190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_intr.2836078775
Short name T572
Test name
Test status
Simulation time 22401429 ps
CPU time 1.46 seconds
Started Sep 18 09:44:07 AM UTC 24
Finished Sep 18 09:44:10 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836078775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.2836078775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_smoke.1540154579
Short name T569
Test name
Test status
Simulation time 29109462 ps
CPU time 1.38 seconds
Started Sep 18 09:44:05 AM UTC 24
Finished Sep 18 09:44:07 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540154579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.1540154579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_stress_all.2354200875
Short name T575
Test name
Test status
Simulation time 208272117 ps
CPU time 5.77 seconds
Started Sep 18 09:44:06 AM UTC 24
Finished Sep 18 09:44:13 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354200875 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2354200875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.329377757
Short name T781
Test name
Test status
Simulation time 3756879161 ps
CPU time 88.4 seconds
Started Sep 18 09:44:07 AM UTC 24
Finished Sep 18 09:45:38 AM UTC 24
Peak memory 232316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=329377757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_
with_rand_reset.329377757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_alert_test.767150254
Short name T345
Test name
Test status
Simulation time 49796013 ps
CPU time 1.34 seconds
Started Sep 18 09:40:00 AM UTC 24
Finished Sep 18 09:40:02 AM UTC 24
Peak memory 227556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767150254 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.767150254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_disable.1612843616
Short name T97
Test name
Test status
Simulation time 34346851 ps
CPU time 1.26 seconds
Started Sep 18 09:39:57 AM UTC 24
Finished Sep 18 09:40:00 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612843616 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1612843616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.2044671658
Short name T85
Test name
Test status
Simulation time 40541616 ps
CPU time 1.51 seconds
Started Sep 18 09:39:58 AM UTC 24
Finished Sep 18 09:40:00 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044671658 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.2044671658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_err.461812357
Short name T56
Test name
Test status
Simulation time 19869116 ps
CPU time 1.69 seconds
Started Sep 18 09:39:57 AM UTC 24
Finished Sep 18 09:40:00 AM UTC 24
Peak memory 238228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461812357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 5.edn_err.461812357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_genbits.3125063493
Short name T48
Test name
Test status
Simulation time 55736542 ps
CPU time 2.2 seconds
Started Sep 18 09:39:53 AM UTC 24
Finished Sep 18 09:39:56 AM UTC 24
Peak memory 230232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125063493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3125063493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_intr.2033410402
Short name T110
Test name
Test status
Simulation time 21086117 ps
CPU time 1.63 seconds
Started Sep 18 09:39:55 AM UTC 24
Finished Sep 18 09:39:58 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033410402 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.2033410402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_regwen.2787082250
Short name T326
Test name
Test status
Simulation time 75262208 ps
CPU time 1.36 seconds
Started Sep 18 09:39:53 AM UTC 24
Finished Sep 18 09:39:55 AM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787082250 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2787082250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_smoke.3843141963
Short name T343
Test name
Test status
Simulation time 43091300 ps
CPU time 1.42 seconds
Started Sep 18 09:39:51 AM UTC 24
Finished Sep 18 09:39:54 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843141963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.3843141963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/5.edn_stress_all.3071910107
Short name T119
Test name
Test status
Simulation time 165201140 ps
CPU time 1.97 seconds
Started Sep 18 09:39:53 AM UTC 24
Finished Sep 18 09:39:56 AM UTC 24
Peak memory 228956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071910107 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3071910107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/50.edn_alert.679856047
Short name T189
Test name
Test status
Simulation time 44873301 ps
CPU time 1.53 seconds
Started Sep 18 09:44:12 AM UTC 24
Finished Sep 18 09:44:14 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679856047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 50.edn_alert.679856047
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/50.edn_err.1881241331
Short name T141
Test name
Test status
Simulation time 30938944 ps
CPU time 1.42 seconds
Started Sep 18 09:44:13 AM UTC 24
Finished Sep 18 09:44:15 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881241331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.1881241331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/50.edn_genbits.858719640
Short name T577
Test name
Test status
Simulation time 45432309 ps
CPU time 1.98 seconds
Started Sep 18 09:44:11 AM UTC 24
Finished Sep 18 09:44:14 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858719640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 50.edn_genbits.858719640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/51.edn_alert.518488552
Short name T579
Test name
Test status
Simulation time 48253653 ps
CPU time 1.7 seconds
Started Sep 18 09:44:14 AM UTC 24
Finished Sep 18 09:44:17 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518488552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 51.edn_alert.518488552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/51.edn_err.2425420680
Short name T134
Test name
Test status
Simulation time 27568249 ps
CPU time 1.8 seconds
Started Sep 18 09:44:14 AM UTC 24
Finished Sep 18 09:44:17 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425420680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.2425420680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/51.edn_genbits.1245916380
Short name T578
Test name
Test status
Simulation time 134086853 ps
CPU time 1.54 seconds
Started Sep 18 09:44:14 AM UTC 24
Finished Sep 18 09:44:16 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245916380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1245916380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/52.edn_alert.1777730840
Short name T581
Test name
Test status
Simulation time 27606293 ps
CPU time 1.79 seconds
Started Sep 18 09:44:15 AM UTC 24
Finished Sep 18 09:44:18 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777730840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 52.edn_alert.1777730840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/52.edn_err.3928299959
Short name T582
Test name
Test status
Simulation time 18416995 ps
CPU time 1.49 seconds
Started Sep 18 09:44:16 AM UTC 24
Finished Sep 18 09:44:19 AM UTC 24
Peak memory 238324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928299959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.3928299959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/52.edn_genbits.1405694428
Short name T580
Test name
Test status
Simulation time 42717418 ps
CPU time 1.57 seconds
Started Sep 18 09:44:15 AM UTC 24
Finished Sep 18 09:44:18 AM UTC 24
Peak memory 229200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405694428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1405694428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/53.edn_alert.2017530780
Short name T583
Test name
Test status
Simulation time 29443684 ps
CPU time 1.66 seconds
Started Sep 18 09:44:17 AM UTC 24
Finished Sep 18 09:44:20 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017530780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.2017530780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/53.edn_err.4073800499
Short name T221
Test name
Test status
Simulation time 46743513 ps
CPU time 1.76 seconds
Started Sep 18 09:44:17 AM UTC 24
Finished Sep 18 09:44:20 AM UTC 24
Peak memory 242892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073800499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.4073800499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/53.edn_genbits.79428234
Short name T309
Test name
Test status
Simulation time 35635914 ps
CPU time 1.79 seconds
Started Sep 18 09:44:17 AM UTC 24
Finished Sep 18 09:44:20 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79428234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 53.edn_genbits.79428234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/54.edn_alert.3622424388
Short name T284
Test name
Test status
Simulation time 130513088 ps
CPU time 1.74 seconds
Started Sep 18 09:44:18 AM UTC 24
Finished Sep 18 09:44:21 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622424388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 54.edn_alert.3622424388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/54.edn_err.332381085
Short name T585
Test name
Test status
Simulation time 85180542 ps
CPU time 1.37 seconds
Started Sep 18 09:44:20 AM UTC 24
Finished Sep 18 09:44:22 AM UTC 24
Peak memory 237344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332381085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 54.edn_err.332381085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/54.edn_genbits.355758570
Short name T584
Test name
Test status
Simulation time 62070921 ps
CPU time 1.5 seconds
Started Sep 18 09:44:18 AM UTC 24
Finished Sep 18 09:44:21 AM UTC 24
Peak memory 226968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355758570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.edn_genbits.355758570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/55.edn_alert.96967319
Short name T303
Test name
Test status
Simulation time 54973042 ps
CPU time 1.77 seconds
Started Sep 18 09:44:21 AM UTC 24
Finished Sep 18 09:44:23 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96967319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 55.edn_alert.96967319
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/55.edn_err.3066482507
Short name T215
Test name
Test status
Simulation time 35646340 ps
CPU time 1.5 seconds
Started Sep 18 09:44:21 AM UTC 24
Finished Sep 18 09:44:23 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066482507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.3066482507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/55.edn_genbits.3186461131
Short name T587
Test name
Test status
Simulation time 90182438 ps
CPU time 1.42 seconds
Started Sep 18 09:44:21 AM UTC 24
Finished Sep 18 09:44:23 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186461131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3186461131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/56.edn_alert.4157181619
Short name T588
Test name
Test status
Simulation time 40116643 ps
CPU time 1.73 seconds
Started Sep 18 09:44:22 AM UTC 24
Finished Sep 18 09:44:25 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157181619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.4157181619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/56.edn_err.2290398390
Short name T209
Test name
Test status
Simulation time 28802242 ps
CPU time 1.53 seconds
Started Sep 18 09:44:23 AM UTC 24
Finished Sep 18 09:44:25 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290398390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.2290398390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/56.edn_genbits.2104629932
Short name T589
Test name
Test status
Simulation time 113143391 ps
CPU time 1.93 seconds
Started Sep 18 09:44:22 AM UTC 24
Finished Sep 18 09:44:25 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104629932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2104629932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/57.edn_alert.3509048350
Short name T590
Test name
Test status
Simulation time 48216611 ps
CPU time 1.49 seconds
Started Sep 18 09:44:24 AM UTC 24
Finished Sep 18 09:44:27 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509048350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.3509048350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/57.edn_err.3521019362
Short name T135
Test name
Test status
Simulation time 66828700 ps
CPU time 1.46 seconds
Started Sep 18 09:44:24 AM UTC 24
Finished Sep 18 09:44:27 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521019362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.3521019362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/57.edn_genbits.3765175834
Short name T13
Test name
Test status
Simulation time 40345822 ps
CPU time 2.26 seconds
Started Sep 18 09:44:23 AM UTC 24
Finished Sep 18 09:44:26 AM UTC 24
Peak memory 232136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765175834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3765175834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/58.edn_alert.3298340028
Short name T593
Test name
Test status
Simulation time 53801848 ps
CPU time 1.61 seconds
Started Sep 18 09:44:25 AM UTC 24
Finished Sep 18 09:44:28 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298340028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.3298340028
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/58.edn_err.753091129
Short name T592
Test name
Test status
Simulation time 21476809 ps
CPU time 1.42 seconds
Started Sep 18 09:44:25 AM UTC 24
Finished Sep 18 09:44:28 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753091129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 58.edn_err.753091129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/58.edn_genbits.2391386880
Short name T591
Test name
Test status
Simulation time 104072361 ps
CPU time 1.77 seconds
Started Sep 18 09:44:24 AM UTC 24
Finished Sep 18 09:44:27 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391386880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2391386880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/59.edn_alert.163872195
Short name T597
Test name
Test status
Simulation time 29139203 ps
CPU time 1.9 seconds
Started Sep 18 09:44:27 AM UTC 24
Finished Sep 18 09:44:30 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163872195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 59.edn_alert.163872195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/59.edn_err.703585692
Short name T595
Test name
Test status
Simulation time 39015186 ps
CPU time 1.67 seconds
Started Sep 18 09:44:27 AM UTC 24
Finished Sep 18 09:44:30 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703585692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 59.edn_err.703585692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/59.edn_genbits.4122629176
Short name T594
Test name
Test status
Simulation time 268043546 ps
CPU time 1.21 seconds
Started Sep 18 09:44:26 AM UTC 24
Finished Sep 18 09:44:29 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122629176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4122629176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_alert.2907504002
Short name T139
Test name
Test status
Simulation time 23603243 ps
CPU time 1.59 seconds
Started Sep 18 09:40:04 AM UTC 24
Finished Sep 18 09:40:07 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907504002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.2907504002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_alert_test.752544228
Short name T346
Test name
Test status
Simulation time 36372402 ps
CPU time 1.27 seconds
Started Sep 18 09:40:04 AM UTC 24
Finished Sep 18 09:40:07 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752544228 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.752544228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_disable.1783934313
Short name T86
Test name
Test status
Simulation time 26448884 ps
CPU time 1.12 seconds
Started Sep 18 09:40:04 AM UTC 24
Finished Sep 18 09:40:06 AM UTC 24
Peak memory 216784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783934313 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1783934313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2138846815
Short name T94
Test name
Test status
Simulation time 77984450 ps
CPU time 1.85 seconds
Started Sep 18 09:40:04 AM UTC 24
Finished Sep 18 09:40:07 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138846815 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2138846815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_err.1661648050
Short name T114
Test name
Test status
Simulation time 36313027 ps
CPU time 1.44 seconds
Started Sep 18 09:40:04 AM UTC 24
Finished Sep 18 09:40:07 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661648050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.1661648050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_genbits.3177404728
Short name T293
Test name
Test status
Simulation time 150655395 ps
CPU time 2.08 seconds
Started Sep 18 09:40:02 AM UTC 24
Finished Sep 18 09:40:05 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177404728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3177404728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_intr.2263554743
Short name T30
Test name
Test status
Simulation time 26160275 ps
CPU time 1.42 seconds
Started Sep 18 09:40:04 AM UTC 24
Finished Sep 18 09:40:07 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263554743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.2263554743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_regwen.3891532677
Short name T331
Test name
Test status
Simulation time 58513854 ps
CPU time 1.21 seconds
Started Sep 18 09:40:00 AM UTC 24
Finished Sep 18 09:40:02 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891532677 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.3891532677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_smoke.1056404528
Short name T344
Test name
Test status
Simulation time 132065365 ps
CPU time 1.2 seconds
Started Sep 18 09:40:00 AM UTC 24
Finished Sep 18 09:40:02 AM UTC 24
Peak memory 226592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056404528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.1056404528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.3922698453
Short name T243
Test name
Test status
Simulation time 3474738135 ps
CPU time 83.86 seconds
Started Sep 18 09:40:02 AM UTC 24
Finished Sep 18 09:41:28 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3922698453 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_
with_rand_reset.3922698453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/60.edn_alert.4219057006
Short name T598
Test name
Test status
Simulation time 253365078 ps
CPU time 1.97 seconds
Started Sep 18 09:44:28 AM UTC 24
Finished Sep 18 09:44:31 AM UTC 24
Peak memory 231012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219057006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.4219057006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/60.edn_err.1024686119
Short name T599
Test name
Test status
Simulation time 25739631 ps
CPU time 1.39 seconds
Started Sep 18 09:44:29 AM UTC 24
Finished Sep 18 09:44:31 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024686119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.1024686119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/60.edn_genbits.913827621
Short name T603
Test name
Test status
Simulation time 327688794 ps
CPU time 4.58 seconds
Started Sep 18 09:44:28 AM UTC 24
Finished Sep 18 09:44:33 AM UTC 24
Peak memory 230064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913827621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.edn_genbits.913827621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/61.edn_err.4111576288
Short name T604
Test name
Test status
Simulation time 19212042 ps
CPU time 1.37 seconds
Started Sep 18 09:44:31 AM UTC 24
Finished Sep 18 09:44:33 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111576288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.4111576288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/61.edn_genbits.3037280760
Short name T600
Test name
Test status
Simulation time 63972355 ps
CPU time 1.56 seconds
Started Sep 18 09:44:29 AM UTC 24
Finished Sep 18 09:44:31 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037280760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3037280760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/62.edn_alert.441201237
Short name T605
Test name
Test status
Simulation time 62306716 ps
CPU time 1.5 seconds
Started Sep 18 09:44:32 AM UTC 24
Finished Sep 18 09:44:34 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441201237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 62.edn_alert.441201237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/62.edn_err.123225754
Short name T188
Test name
Test status
Simulation time 27374890 ps
CPU time 1.15 seconds
Started Sep 18 09:44:32 AM UTC 24
Finished Sep 18 09:44:34 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123225754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 62.edn_err.123225754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/62.edn_genbits.4200019056
Short name T601
Test name
Test status
Simulation time 78562277 ps
CPU time 1.25 seconds
Started Sep 18 09:44:31 AM UTC 24
Finished Sep 18 09:44:33 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200019056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4200019056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/63.edn_alert.701460151
Short name T608
Test name
Test status
Simulation time 48255280 ps
CPU time 1.78 seconds
Started Sep 18 09:44:33 AM UTC 24
Finished Sep 18 09:44:36 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701460151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 63.edn_alert.701460151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/63.edn_err.1873870938
Short name T609
Test name
Test status
Simulation time 33970035 ps
CPU time 1.13 seconds
Started Sep 18 09:44:34 AM UTC 24
Finished Sep 18 09:44:36 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873870938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.1873870938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/63.edn_genbits.2562730079
Short name T607
Test name
Test status
Simulation time 32087888 ps
CPU time 2.03 seconds
Started Sep 18 09:44:32 AM UTC 24
Finished Sep 18 09:44:35 AM UTC 24
Peak memory 230280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562730079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2562730079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/64.edn_alert.2034342122
Short name T173
Test name
Test status
Simulation time 36189392 ps
CPU time 1.6 seconds
Started Sep 18 09:44:34 AM UTC 24
Finished Sep 18 09:44:37 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034342122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.2034342122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/64.edn_err.68209545
Short name T150
Test name
Test status
Simulation time 40360809 ps
CPU time 1.53 seconds
Started Sep 18 09:44:34 AM UTC 24
Finished Sep 18 09:44:37 AM UTC 24
Peak memory 226948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68209545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 64.edn_err.68209545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/64.edn_genbits.3117999581
Short name T610
Test name
Test status
Simulation time 86023480 ps
CPU time 1.99 seconds
Started Sep 18 09:44:34 AM UTC 24
Finished Sep 18 09:44:37 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117999581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3117999581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/65.edn_alert.371692087
Short name T611
Test name
Test status
Simulation time 158400782 ps
CPU time 1.79 seconds
Started Sep 18 09:44:35 AM UTC 24
Finished Sep 18 09:44:38 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371692087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 65.edn_alert.371692087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/65.edn_err.1983346388
Short name T227
Test name
Test status
Simulation time 36808362 ps
CPU time 1.29 seconds
Started Sep 18 09:44:36 AM UTC 24
Finished Sep 18 09:44:38 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983346388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.1983346388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/65.edn_genbits.2366221659
Short name T337
Test name
Test status
Simulation time 63846336 ps
CPU time 2.88 seconds
Started Sep 18 09:44:35 AM UTC 24
Finished Sep 18 09:44:39 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366221659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2366221659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/66.edn_alert.3754955434
Short name T190
Test name
Test status
Simulation time 49433007 ps
CPU time 1.56 seconds
Started Sep 18 09:44:37 AM UTC 24
Finished Sep 18 09:44:39 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754955434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.3754955434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/66.edn_err.2807191220
Short name T613
Test name
Test status
Simulation time 73443116 ps
CPU time 1.52 seconds
Started Sep 18 09:44:37 AM UTC 24
Finished Sep 18 09:44:39 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807191220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.2807191220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/66.edn_genbits.1471022790
Short name T612
Test name
Test status
Simulation time 41952593 ps
CPU time 1.93 seconds
Started Sep 18 09:44:36 AM UTC 24
Finished Sep 18 09:44:38 AM UTC 24
Peak memory 229204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471022790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1471022790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/67.edn_alert.2905856551
Short name T616
Test name
Test status
Simulation time 80735972 ps
CPU time 1.73 seconds
Started Sep 18 09:44:38 AM UTC 24
Finished Sep 18 09:44:41 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905856551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.2905856551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/67.edn_err.2802108121
Short name T614
Test name
Test status
Simulation time 29743679 ps
CPU time 1.46 seconds
Started Sep 18 09:44:38 AM UTC 24
Finished Sep 18 09:44:40 AM UTC 24
Peak memory 246616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802108121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.2802108121
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/67.edn_genbits.2157885770
Short name T615
Test name
Test status
Simulation time 27913645 ps
CPU time 1.71 seconds
Started Sep 18 09:44:38 AM UTC 24
Finished Sep 18 09:44:40 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157885770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2157885770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/68.edn_alert.652888581
Short name T204
Test name
Test status
Simulation time 292581894 ps
CPU time 2.08 seconds
Started Sep 18 09:44:39 AM UTC 24
Finished Sep 18 09:44:42 AM UTC 24
Peak memory 232632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652888581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 68.edn_alert.652888581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/68.edn_err.111679398
Short name T222
Test name
Test status
Simulation time 65231199 ps
CPU time 1.51 seconds
Started Sep 18 09:44:39 AM UTC 24
Finished Sep 18 09:44:41 AM UTC 24
Peak memory 238148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111679398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 68.edn_err.111679398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/68.edn_genbits.2910608332
Short name T617
Test name
Test status
Simulation time 53908786 ps
CPU time 1.59 seconds
Started Sep 18 09:44:39 AM UTC 24
Finished Sep 18 09:44:42 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910608332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2910608332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/69.edn_alert.2054079687
Short name T621
Test name
Test status
Simulation time 29649025 ps
CPU time 1.82 seconds
Started Sep 18 09:44:40 AM UTC 24
Finished Sep 18 09:44:43 AM UTC 24
Peak memory 226856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054079687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.2054079687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/69.edn_err.4182730716
Short name T619
Test name
Test status
Simulation time 66433803 ps
CPU time 1.14 seconds
Started Sep 18 09:44:40 AM UTC 24
Finished Sep 18 09:44:42 AM UTC 24
Peak memory 228860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182730716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.4182730716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/69.edn_genbits.1038585089
Short name T618
Test name
Test status
Simulation time 48069297 ps
CPU time 1.62 seconds
Started Sep 18 09:44:39 AM UTC 24
Finished Sep 18 09:44:42 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038585089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1038585089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_alert.140669508
Short name T132
Test name
Test status
Simulation time 27234010 ps
CPU time 1.76 seconds
Started Sep 18 09:40:09 AM UTC 24
Finished Sep 18 09:40:12 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140669508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.edn_alert.140669508
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_alert_test.103835868
Short name T238
Test name
Test status
Simulation time 49299808 ps
CPU time 1.37 seconds
Started Sep 18 09:40:12 AM UTC 24
Finished Sep 18 09:40:15 AM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103835868 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.103835868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_disable.3637210467
Short name T65
Test name
Test status
Simulation time 19659286 ps
CPU time 1.37 seconds
Started Sep 18 09:40:10 AM UTC 24
Finished Sep 18 09:40:12 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637210467 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3637210467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.286695172
Short name T151
Test name
Test status
Simulation time 88384138 ps
CPU time 1.49 seconds
Started Sep 18 09:40:12 AM UTC 24
Finished Sep 18 09:40:15 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286695172 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.286695172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_err.3645322678
Short name T348
Test name
Test status
Simulation time 17902981 ps
CPU time 1.44 seconds
Started Sep 18 09:40:10 AM UTC 24
Finished Sep 18 09:40:12 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645322678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.3645322678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_genbits.110994727
Short name T49
Test name
Test status
Simulation time 59885956 ps
CPU time 1.78 seconds
Started Sep 18 09:40:09 AM UTC 24
Finished Sep 18 09:40:11 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110994727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_genbits.110994727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_intr.561631954
Short name T43
Test name
Test status
Simulation time 84166073 ps
CPU time 1.51 seconds
Started Sep 18 09:40:09 AM UTC 24
Finished Sep 18 09:40:11 AM UTC 24
Peak memory 237348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561631954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.561631954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_regwen.3801888326
Short name T126
Test name
Test status
Simulation time 18582964 ps
CPU time 1.45 seconds
Started Sep 18 09:40:08 AM UTC 24
Finished Sep 18 09:40:10 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801888326 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.3801888326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_smoke.3299401275
Short name T347
Test name
Test status
Simulation time 23676089 ps
CPU time 1.16 seconds
Started Sep 18 09:40:06 AM UTC 24
Finished Sep 18 09:40:09 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299401275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.3299401275
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/7.edn_stress_all.2752618384
Short name T239
Test name
Test status
Simulation time 182257880 ps
CPU time 4.79 seconds
Started Sep 18 09:40:09 AM UTC 24
Finished Sep 18 09:40:15 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752618384 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2752618384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/70.edn_alert.344419340
Short name T624
Test name
Test status
Simulation time 55485123 ps
CPU time 1.55 seconds
Started Sep 18 09:44:41 AM UTC 24
Finished Sep 18 09:44:44 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344419340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 70.edn_alert.344419340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/70.edn_err.761045630
Short name T623
Test name
Test status
Simulation time 107930113 ps
CPU time 1.26 seconds
Started Sep 18 09:44:41 AM UTC 24
Finished Sep 18 09:44:44 AM UTC 24
Peak memory 231044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761045630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 70.edn_err.761045630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/70.edn_genbits.1807613102
Short name T620
Test name
Test status
Simulation time 85860137 ps
CPU time 1.57 seconds
Started Sep 18 09:44:40 AM UTC 24
Finished Sep 18 09:44:43 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807613102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1807613102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/71.edn_alert.1495292015
Short name T626
Test name
Test status
Simulation time 28481337 ps
CPU time 1.62 seconds
Started Sep 18 09:44:43 AM UTC 24
Finished Sep 18 09:44:45 AM UTC 24
Peak memory 228988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495292015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.1495292015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/71.edn_err.2675010354
Short name T627
Test name
Test status
Simulation time 22676766 ps
CPU time 1.64 seconds
Started Sep 18 09:44:43 AM UTC 24
Finished Sep 18 09:44:45 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675010354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.2675010354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/71.edn_genbits.3328735005
Short name T625
Test name
Test status
Simulation time 121635247 ps
CPU time 1.86 seconds
Started Sep 18 09:44:41 AM UTC 24
Finished Sep 18 09:44:44 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328735005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3328735005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/72.edn_alert.2539042167
Short name T628
Test name
Test status
Simulation time 26185373 ps
CPU time 1.72 seconds
Started Sep 18 09:44:43 AM UTC 24
Finished Sep 18 09:44:45 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539042167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.2539042167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/72.edn_err.4009076624
Short name T630
Test name
Test status
Simulation time 30045106 ps
CPU time 1.33 seconds
Started Sep 18 09:44:44 AM UTC 24
Finished Sep 18 09:44:46 AM UTC 24
Peak memory 238244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009076624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.4009076624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/72.edn_genbits.2456182167
Short name T633
Test name
Test status
Simulation time 66286418 ps
CPU time 3.27 seconds
Started Sep 18 09:44:43 AM UTC 24
Finished Sep 18 09:44:47 AM UTC 24
Peak memory 229976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456182167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2456182167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/73.edn_alert.2453283454
Short name T631
Test name
Test status
Simulation time 51499150 ps
CPU time 1.64 seconds
Started Sep 18 09:44:44 AM UTC 24
Finished Sep 18 09:44:46 AM UTC 24
Peak memory 226728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453283454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 73.edn_alert.2453283454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/73.edn_err.4275508422
Short name T219
Test name
Test status
Simulation time 23296442 ps
CPU time 1.32 seconds
Started Sep 18 09:44:44 AM UTC 24
Finished Sep 18 09:44:46 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275508422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.4275508422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/73.edn_genbits.1713387220
Short name T632
Test name
Test status
Simulation time 45133253 ps
CPU time 1.96 seconds
Started Sep 18 09:44:44 AM UTC 24
Finished Sep 18 09:44:47 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713387220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1713387220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/74.edn_alert.3034735356
Short name T635
Test name
Test status
Simulation time 42112977 ps
CPU time 1.62 seconds
Started Sep 18 09:44:45 AM UTC 24
Finished Sep 18 09:44:48 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034735356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.3034735356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/74.edn_err.1133032083
Short name T634
Test name
Test status
Simulation time 22992309 ps
CPU time 1.23 seconds
Started Sep 18 09:44:45 AM UTC 24
Finished Sep 18 09:44:47 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133032083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.1133032083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/74.edn_genbits.2658553936
Short name T596
Test name
Test status
Simulation time 44276169 ps
CPU time 1.88 seconds
Started Sep 18 09:44:45 AM UTC 24
Finished Sep 18 09:44:48 AM UTC 24
Peak memory 229204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658553936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2658553936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/75.edn_alert.912778164
Short name T176
Test name
Test status
Simulation time 52316916 ps
CPU time 1.64 seconds
Started Sep 18 09:44:46 AM UTC 24
Finished Sep 18 09:44:49 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912778164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 75.edn_alert.912778164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/75.edn_err.2278230468
Short name T156
Test name
Test status
Simulation time 25272370 ps
CPU time 1.95 seconds
Started Sep 18 09:44:46 AM UTC 24
Finished Sep 18 09:44:49 AM UTC 24
Peak memory 247036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278230468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.2278230468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/75.edn_genbits.858552086
Short name T636
Test name
Test status
Simulation time 61877474 ps
CPU time 1.94 seconds
Started Sep 18 09:44:46 AM UTC 24
Finished Sep 18 09:44:49 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858552086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 75.edn_genbits.858552086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/76.edn_alert.1231048824
Short name T639
Test name
Test status
Simulation time 71291317 ps
CPU time 1.48 seconds
Started Sep 18 09:44:47 AM UTC 24
Finished Sep 18 09:44:50 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231048824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.1231048824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/76.edn_err.1179908597
Short name T180
Test name
Test status
Simulation time 72855723 ps
CPU time 1.59 seconds
Started Sep 18 09:44:47 AM UTC 24
Finished Sep 18 09:44:50 AM UTC 24
Peak memory 242816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179908597 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.1179908597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/76.edn_genbits.1375960199
Short name T637
Test name
Test status
Simulation time 134003020 ps
CPU time 1.87 seconds
Started Sep 18 09:44:46 AM UTC 24
Finished Sep 18 09:44:49 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375960199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1375960199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/77.edn_alert.1404044272
Short name T640
Test name
Test status
Simulation time 66352161 ps
CPU time 1.59 seconds
Started Sep 18 09:44:48 AM UTC 24
Finished Sep 18 09:44:50 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404044272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.1404044272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/77.edn_err.2705185683
Short name T638
Test name
Test status
Simulation time 21370941 ps
CPU time 1.34 seconds
Started Sep 18 09:44:48 AM UTC 24
Finished Sep 18 09:44:50 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705185683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.2705185683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/77.edn_genbits.2487435301
Short name T641
Test name
Test status
Simulation time 86652087 ps
CPU time 1.96 seconds
Started Sep 18 09:44:47 AM UTC 24
Finished Sep 18 09:44:50 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487435301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2487435301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/78.edn_alert.3187457070
Short name T644
Test name
Test status
Simulation time 29408054 ps
CPU time 1.71 seconds
Started Sep 18 09:44:49 AM UTC 24
Finished Sep 18 09:44:51 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187457070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 78.edn_alert.3187457070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/78.edn_err.1740039571
Short name T642
Test name
Test status
Simulation time 27466481 ps
CPU time 1.39 seconds
Started Sep 18 09:44:49 AM UTC 24
Finished Sep 18 09:44:51 AM UTC 24
Peak memory 237168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740039571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.1740039571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/78.edn_genbits.927129460
Short name T643
Test name
Test status
Simulation time 34622679 ps
CPU time 1.68 seconds
Started Sep 18 09:44:49 AM UTC 24
Finished Sep 18 09:44:51 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927129460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 78.edn_genbits.927129460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/79.edn_alert.3371133073
Short name T648
Test name
Test status
Simulation time 29450189 ps
CPU time 1.82 seconds
Started Sep 18 09:44:50 AM UTC 24
Finished Sep 18 09:44:53 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371133073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.3371133073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/79.edn_err.1890788215
Short name T645
Test name
Test status
Simulation time 40054704 ps
CPU time 1.16 seconds
Started Sep 18 09:44:50 AM UTC 24
Finished Sep 18 09:44:52 AM UTC 24
Peak memory 238092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890788215 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.1890788215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/79.edn_genbits.3662723691
Short name T647
Test name
Test status
Simulation time 44683285 ps
CPU time 1.79 seconds
Started Sep 18 09:44:50 AM UTC 24
Finished Sep 18 09:44:53 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662723691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3662723691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_alert_test.1887263787
Short name T349
Test name
Test status
Simulation time 65020719 ps
CPU time 1.32 seconds
Started Sep 18 09:40:16 AM UTC 24
Finished Sep 18 09:40:18 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887263787 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1887263787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_disable.604658746
Short name T66
Test name
Test status
Simulation time 12417437 ps
CPU time 1.4 seconds
Started Sep 18 09:40:16 AM UTC 24
Finished Sep 18 09:40:18 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604658746 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.604658746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.2317751106
Short name T79
Test name
Test status
Simulation time 53576423 ps
CPU time 1.89 seconds
Started Sep 18 09:40:16 AM UTC 24
Finished Sep 18 09:40:19 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317751106 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.2317751106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_err.577061631
Short name T185
Test name
Test status
Simulation time 26019303 ps
CPU time 1.19 seconds
Started Sep 18 09:40:16 AM UTC 24
Finished Sep 18 09:40:18 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577061631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.edn_err.577061631
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_genbits.2166350822
Short name T242
Test name
Test status
Simulation time 99209064 ps
CPU time 1.65 seconds
Started Sep 18 09:40:14 AM UTC 24
Finished Sep 18 09:40:17 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166350822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2166350822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_regwen.1939749980
Short name T241
Test name
Test status
Simulation time 47083998 ps
CPU time 1.36 seconds
Started Sep 18 09:40:12 AM UTC 24
Finished Sep 18 09:40:15 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939749980 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.1939749980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_smoke.2295867341
Short name T240
Test name
Test status
Simulation time 19373763 ps
CPU time 1.37 seconds
Started Sep 18 09:40:12 AM UTC 24
Finished Sep 18 09:40:15 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295867341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.2295867341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_stress_all.947548839
Short name T115
Test name
Test status
Simulation time 221176341 ps
CPU time 3.61 seconds
Started Sep 18 09:40:15 AM UTC 24
Finished Sep 18 09:40:19 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947548839 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.947548839
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.4046949969
Short name T236
Test name
Test status
Simulation time 2079946119 ps
CPU time 61.62 seconds
Started Sep 18 09:40:15 AM UTC 24
Finished Sep 18 09:41:18 AM UTC 24
Peak memory 232320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4046949969 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_
with_rand_reset.4046949969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/80.edn_alert.3803147911
Short name T651
Test name
Test status
Simulation time 41504792 ps
CPU time 1.71 seconds
Started Sep 18 09:44:51 AM UTC 24
Finished Sep 18 09:44:54 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803147911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.3803147911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/80.edn_err.2237525673
Short name T143
Test name
Test status
Simulation time 24950579 ps
CPU time 1.34 seconds
Started Sep 18 09:44:51 AM UTC 24
Finished Sep 18 09:44:54 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237525673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.2237525673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/80.edn_genbits.3827654812
Short name T649
Test name
Test status
Simulation time 38526126 ps
CPU time 2 seconds
Started Sep 18 09:44:50 AM UTC 24
Finished Sep 18 09:44:53 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827654812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3827654812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/81.edn_alert.259942975
Short name T652
Test name
Test status
Simulation time 30418688 ps
CPU time 1.87 seconds
Started Sep 18 09:44:51 AM UTC 24
Finished Sep 18 09:44:54 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259942975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 81.edn_alert.259942975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/81.edn_err.1566232031
Short name T650
Test name
Test status
Simulation time 40535294 ps
CPU time 1.26 seconds
Started Sep 18 09:44:51 AM UTC 24
Finished Sep 18 09:44:54 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566232031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.1566232031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/81.edn_genbits.1018461525
Short name T323
Test name
Test status
Simulation time 111957432 ps
CPU time 4.15 seconds
Started Sep 18 09:44:51 AM UTC 24
Finished Sep 18 09:44:56 AM UTC 24
Peak memory 232284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018461525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1018461525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/82.edn_alert.1946668935
Short name T138
Test name
Test status
Simulation time 184264138 ps
CPU time 1.89 seconds
Started Sep 18 09:44:52 AM UTC 24
Finished Sep 18 09:44:55 AM UTC 24
Peak memory 228880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946668935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.1946668935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/82.edn_err.3460579541
Short name T653
Test name
Test status
Simulation time 34697263 ps
CPU time 1.65 seconds
Started Sep 18 09:44:52 AM UTC 24
Finished Sep 18 09:44:55 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460579541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.3460579541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/82.edn_genbits.262174707
Short name T324
Test name
Test status
Simulation time 100070328 ps
CPU time 3.51 seconds
Started Sep 18 09:44:52 AM UTC 24
Finished Sep 18 09:44:57 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262174707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 82.edn_genbits.262174707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/83.edn_alert.611780689
Short name T656
Test name
Test status
Simulation time 50295036 ps
CPU time 1.31 seconds
Started Sep 18 09:44:54 AM UTC 24
Finished Sep 18 09:44:56 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611780689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 83.edn_alert.611780689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/83.edn_err.3651035285
Short name T657
Test name
Test status
Simulation time 29049608 ps
CPU time 1.43 seconds
Started Sep 18 09:44:54 AM UTC 24
Finished Sep 18 09:44:56 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651035285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.3651035285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/83.edn_genbits.4074773442
Short name T654
Test name
Test status
Simulation time 189429162 ps
CPU time 1.65 seconds
Started Sep 18 09:44:53 AM UTC 24
Finished Sep 18 09:44:55 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074773442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4074773442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/84.edn_alert.2579288944
Short name T658
Test name
Test status
Simulation time 73979790 ps
CPU time 1.64 seconds
Started Sep 18 09:44:54 AM UTC 24
Finished Sep 18 09:44:56 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579288944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.2579288944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/84.edn_err.1618387418
Short name T661
Test name
Test status
Simulation time 19109319 ps
CPU time 1.49 seconds
Started Sep 18 09:44:55 AM UTC 24
Finished Sep 18 09:44:57 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618387418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.1618387418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/84.edn_genbits.1680105943
Short name T667
Test name
Test status
Simulation time 281663057 ps
CPU time 4.57 seconds
Started Sep 18 09:44:54 AM UTC 24
Finished Sep 18 09:44:59 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680105943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1680105943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/85.edn_alert.219295416
Short name T662
Test name
Test status
Simulation time 24183135 ps
CPU time 1.58 seconds
Started Sep 18 09:44:55 AM UTC 24
Finished Sep 18 09:44:57 AM UTC 24
Peak memory 228916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219295416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 85.edn_alert.219295416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/85.edn_err.1073052294
Short name T660
Test name
Test status
Simulation time 24514783 ps
CPU time 1.35 seconds
Started Sep 18 09:44:55 AM UTC 24
Finished Sep 18 09:44:57 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073052294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.1073052294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/85.edn_genbits.2410962486
Short name T664
Test name
Test status
Simulation time 55437550 ps
CPU time 2.82 seconds
Started Sep 18 09:44:55 AM UTC 24
Finished Sep 18 09:44:59 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410962486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2410962486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/86.edn_alert.2327622963
Short name T174
Test name
Test status
Simulation time 23060256 ps
CPU time 1.73 seconds
Started Sep 18 09:44:56 AM UTC 24
Finished Sep 18 09:44:59 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327622963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.2327622963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/86.edn_err.1266655600
Short name T663
Test name
Test status
Simulation time 26183504 ps
CPU time 1.49 seconds
Started Sep 18 09:44:56 AM UTC 24
Finished Sep 18 09:44:59 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266655600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.1266655600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/86.edn_genbits.4200172363
Short name T665
Test name
Test status
Simulation time 75848556 ps
CPU time 1.98 seconds
Started Sep 18 09:44:56 AM UTC 24
Finished Sep 18 09:44:59 AM UTC 24
Peak memory 231252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200172363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4200172363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/87.edn_alert.1673155370
Short name T154
Test name
Test status
Simulation time 64594971 ps
CPU time 1.75 seconds
Started Sep 18 09:44:57 AM UTC 24
Finished Sep 18 09:45:00 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673155370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.1673155370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/87.edn_err.169880232
Short name T666
Test name
Test status
Simulation time 28727507 ps
CPU time 0.91 seconds
Started Sep 18 09:44:57 AM UTC 24
Finished Sep 18 09:44:59 AM UTC 24
Peak memory 228948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169880232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 87.edn_err.169880232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/87.edn_genbits.3835671865
Short name T670
Test name
Test status
Simulation time 25421118 ps
CPU time 1.73 seconds
Started Sep 18 09:44:57 AM UTC 24
Finished Sep 18 09:45:00 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835671865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3835671865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/88.edn_alert.3033061673
Short name T669
Test name
Test status
Simulation time 27701989 ps
CPU time 1.43 seconds
Started Sep 18 09:44:57 AM UTC 24
Finished Sep 18 09:45:00 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033061673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.3033061673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/88.edn_err.3202663876
Short name T671
Test name
Test status
Simulation time 70570600 ps
CPU time 1.54 seconds
Started Sep 18 09:44:58 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 243252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202663876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.3202663876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/88.edn_genbits.1528121541
Short name T668
Test name
Test status
Simulation time 89957655 ps
CPU time 1.36 seconds
Started Sep 18 09:44:57 AM UTC 24
Finished Sep 18 09:45:00 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528121541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1528121541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/89.edn_alert.3485721096
Short name T672
Test name
Test status
Simulation time 29220959 ps
CPU time 1.73 seconds
Started Sep 18 09:44:59 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485721096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.3485721096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/89.edn_err.848619412
Short name T160
Test name
Test status
Simulation time 22713185 ps
CPU time 1.61 seconds
Started Sep 18 09:45:00 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 244712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848619412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 89.edn_err.848619412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/89.edn_genbits.1421396252
Short name T676
Test name
Test status
Simulation time 49728628 ps
CPU time 2.3 seconds
Started Sep 18 09:44:58 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421396252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1421396252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_alert.1183029598
Short name T87
Test name
Test status
Simulation time 25302342 ps
CPU time 1.52 seconds
Started Sep 18 09:40:19 AM UTC 24
Finished Sep 18 09:40:22 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183029598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.1183029598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_alert_test.739478328
Short name T351
Test name
Test status
Simulation time 25879022 ps
CPU time 1.25 seconds
Started Sep 18 09:40:22 AM UTC 24
Finished Sep 18 09:40:24 AM UTC 24
Peak memory 216892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739478328 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.739478328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_disable.555133530
Short name T50
Test name
Test status
Simulation time 16932048 ps
CPU time 1.26 seconds
Started Sep 18 09:40:19 AM UTC 24
Finished Sep 18 09:40:22 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555133530 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.555133530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.767755001
Short name T73
Test name
Test status
Simulation time 47922542 ps
CPU time 1.88 seconds
Started Sep 18 09:40:21 AM UTC 24
Finished Sep 18 09:40:23 AM UTC 24
Peak memory 226900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767755001 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.767755001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_err.1335740082
Short name T58
Test name
Test status
Simulation time 19522419 ps
CPU time 1.54 seconds
Started Sep 18 09:40:19 AM UTC 24
Finished Sep 18 09:40:22 AM UTC 24
Peak memory 238404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335740082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.1335740082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_genbits.3312548238
Short name T41
Test name
Test status
Simulation time 108814401 ps
CPU time 1.71 seconds
Started Sep 18 09:40:18 AM UTC 24
Finished Sep 18 09:40:21 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312548238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3312548238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_intr.859622883
Short name T57
Test name
Test status
Simulation time 34716020 ps
CPU time 1.36 seconds
Started Sep 18 09:40:19 AM UTC 24
Finished Sep 18 09:40:22 AM UTC 24
Peak memory 238344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859622883 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.859622883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_regwen.1167686197
Short name T249
Test name
Test status
Simulation time 54760782 ps
CPU time 1.42 seconds
Started Sep 18 09:40:18 AM UTC 24
Finished Sep 18 09:40:20 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167686197 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.1167686197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_smoke.1314475538
Short name T350
Test name
Test status
Simulation time 21116673 ps
CPU time 1.36 seconds
Started Sep 18 09:40:16 AM UTC 24
Finished Sep 18 09:40:18 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314475538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.1314475538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_stress_all.962708828
Short name T117
Test name
Test status
Simulation time 481465608 ps
CPU time 3.35 seconds
Started Sep 18 09:40:19 AM UTC 24
Finished Sep 18 09:40:24 AM UTC 24
Peak memory 228168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962708828 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.962708828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.75740753
Short name T403
Test name
Test status
Simulation time 8127433720 ps
CPU time 62.71 seconds
Started Sep 18 09:40:19 AM UTC 24
Finished Sep 18 09:41:24 AM UTC 24
Peak memory 230344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=75740753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_wi
th_rand_reset.75740753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/90.edn_alert.1902378362
Short name T675
Test name
Test status
Simulation time 73267239 ps
CPU time 1.62 seconds
Started Sep 18 09:45:00 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902378362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.1902378362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/90.edn_err.712952768
Short name T673
Test name
Test status
Simulation time 19500997 ps
CPU time 1.45 seconds
Started Sep 18 09:45:00 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 228992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712952768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 90.edn_err.712952768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/90.edn_genbits.2897952340
Short name T677
Test name
Test status
Simulation time 33486119 ps
CPU time 1.75 seconds
Started Sep 18 09:45:00 AM UTC 24
Finished Sep 18 09:45:03 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897952340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2897952340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/91.edn_alert.1006635143
Short name T678
Test name
Test status
Simulation time 165324551 ps
CPU time 1.81 seconds
Started Sep 18 09:45:00 AM UTC 24
Finished Sep 18 09:45:03 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006635143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.1006635143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/91.edn_err.1574558964
Short name T682
Test name
Test status
Simulation time 33027765 ps
CPU time 1.86 seconds
Started Sep 18 09:45:01 AM UTC 24
Finished Sep 18 09:45:04 AM UTC 24
Peak memory 242892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574558964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 91.edn_err.1574558964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/91.edn_genbits.1322456927
Short name T674
Test name
Test status
Simulation time 57089206 ps
CPU time 1.46 seconds
Started Sep 18 09:45:00 AM UTC 24
Finished Sep 18 09:45:02 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322456927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1322456927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/92.edn_alert.886639316
Short name T680
Test name
Test status
Simulation time 23158659 ps
CPU time 1.68 seconds
Started Sep 18 09:45:01 AM UTC 24
Finished Sep 18 09:45:04 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886639316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 92.edn_alert.886639316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/92.edn_err.2349728901
Short name T679
Test name
Test status
Simulation time 59619632 ps
CPU time 1.39 seconds
Started Sep 18 09:45:01 AM UTC 24
Finished Sep 18 09:45:04 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349728901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.2349728901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/92.edn_genbits.2323592671
Short name T681
Test name
Test status
Simulation time 56286567 ps
CPU time 1.77 seconds
Started Sep 18 09:45:01 AM UTC 24
Finished Sep 18 09:45:04 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323592671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2323592671
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/93.edn_alert.1983123359
Short name T688
Test name
Test status
Simulation time 309904020 ps
CPU time 1.59 seconds
Started Sep 18 09:45:03 AM UTC 24
Finished Sep 18 09:45:06 AM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983123359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.1983123359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/93.edn_err.1710392516
Short name T684
Test name
Test status
Simulation time 23479223 ps
CPU time 1.28 seconds
Started Sep 18 09:45:03 AM UTC 24
Finished Sep 18 09:45:06 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710392516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.1710392516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/94.edn_alert.344236315
Short name T687
Test name
Test status
Simulation time 46628675 ps
CPU time 1.51 seconds
Started Sep 18 09:45:03 AM UTC 24
Finished Sep 18 09:45:06 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344236315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 94.edn_alert.344236315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/94.edn_err.1876960644
Short name T683
Test name
Test status
Simulation time 28253906 ps
CPU time 1.11 seconds
Started Sep 18 09:45:03 AM UTC 24
Finished Sep 18 09:45:06 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876960644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.1876960644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/94.edn_genbits.1734564294
Short name T685
Test name
Test status
Simulation time 248389910 ps
CPU time 1.6 seconds
Started Sep 18 09:45:03 AM UTC 24
Finished Sep 18 09:45:06 AM UTC 24
Peak memory 226880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734564294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1734564294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/95.edn_alert.600509813
Short name T686
Test name
Test status
Simulation time 84639603 ps
CPU time 1.56 seconds
Started Sep 18 09:45:04 AM UTC 24
Finished Sep 18 09:45:06 AM UTC 24
Peak memory 231024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600509813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 95.edn_alert.600509813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/95.edn_err.630561075
Short name T182
Test name
Test status
Simulation time 20137221 ps
CPU time 1.46 seconds
Started Sep 18 09:45:05 AM UTC 24
Finished Sep 18 09:45:07 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630561075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 95.edn_err.630561075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/95.edn_genbits.2916716982
Short name T693
Test name
Test status
Simulation time 577219737 ps
CPU time 4.66 seconds
Started Sep 18 09:45:03 AM UTC 24
Finished Sep 18 09:45:09 AM UTC 24
Peak memory 231952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916716982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2916716982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/96.edn_alert.2998176260
Short name T194
Test name
Test status
Simulation time 68383732 ps
CPU time 1.54 seconds
Started Sep 18 09:45:05 AM UTC 24
Finished Sep 18 09:45:07 AM UTC 24
Peak memory 230604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998176260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.2998176260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/96.edn_err.3893765996
Short name T689
Test name
Test status
Simulation time 18475402 ps
CPU time 1.19 seconds
Started Sep 18 09:45:05 AM UTC 24
Finished Sep 18 09:45:07 AM UTC 24
Peak memory 228900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893765996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 96.edn_err.3893765996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/96.edn_genbits.2407101131
Short name T691
Test name
Test status
Simulation time 125691651 ps
CPU time 3.24 seconds
Started Sep 18 09:45:05 AM UTC 24
Finished Sep 18 09:45:09 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407101131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2407101131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/97.edn_alert.1330998496
Short name T695
Test name
Test status
Simulation time 86542734 ps
CPU time 1.69 seconds
Started Sep 18 09:45:07 AM UTC 24
Finished Sep 18 09:45:10 AM UTC 24
Peak memory 228920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330998496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.1330998496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/97.edn_err.674451461
Short name T692
Test name
Test status
Simulation time 76518795 ps
CPU time 1.35 seconds
Started Sep 18 09:45:07 AM UTC 24
Finished Sep 18 09:45:09 AM UTC 24
Peak memory 228944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674451461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 97.edn_err.674451461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/97.edn_genbits.2927659649
Short name T690
Test name
Test status
Simulation time 114862047 ps
CPU time 1.45 seconds
Started Sep 18 09:45:05 AM UTC 24
Finished Sep 18 09:45:07 AM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927659649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2927659649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/98.edn_alert.4290231668
Short name T696
Test name
Test status
Simulation time 26776143 ps
CPU time 1.65 seconds
Started Sep 18 09:45:07 AM UTC 24
Finished Sep 18 09:45:10 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290231668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.4290231668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/98.edn_err.499000052
Short name T694
Test name
Test status
Simulation time 32259411 ps
CPU time 1.46 seconds
Started Sep 18 09:45:07 AM UTC 24
Finished Sep 18 09:45:10 AM UTC 24
Peak memory 237164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499000052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 98.edn_err.499000052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/98.edn_genbits.3279165315
Short name T314
Test name
Test status
Simulation time 145621906 ps
CPU time 3.53 seconds
Started Sep 18 09:45:07 AM UTC 24
Finished Sep 18 09:45:12 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279165315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3279165315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/99.edn_alert.912714734
Short name T698
Test name
Test status
Simulation time 48719512 ps
CPU time 1.4 seconds
Started Sep 18 09:45:08 AM UTC 24
Finished Sep 18 09:45:11 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912714734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 99.edn_alert.912714734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/99.edn_err.3279016542
Short name T699
Test name
Test status
Simulation time 25924501 ps
CPU time 1.42 seconds
Started Sep 18 09:45:08 AM UTC 24
Finished Sep 18 09:45:11 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279016542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.3279016542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/default/99.edn_genbits.1840280638
Short name T697
Test name
Test status
Simulation time 51041089 ps
CPU time 1.86 seconds
Started Sep 18 09:45:07 AM UTC 24
Finished Sep 18 09:45:10 AM UTC 24
Peak memory 229012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840280638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1840280638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/99.edn_genbits/latest
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