| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.95 | 98.23 | 93.91 | 97.02 | 93.60 | 96.33 | 99.77 | 92.80 |
| T1004 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1981746555 | Sep 24 08:52:40 AM UTC 24 | Sep 24 08:52:56 AM UTC 24 | 37012553 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1189361190 | Sep 24 08:52:40 AM UTC 24 | Sep 24 08:52:56 AM UTC 24 | 19409048 ps | ||
| T1005 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.4245016843 | Sep 24 08:52:40 AM UTC 24 | Sep 24 08:52:56 AM UTC 24 | 28651450 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.3371724996 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:56 AM UTC 24 | 124583673 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1264218570 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 93701200 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2752455681 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 19461450 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.2219732151 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 27798108 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3434424811 | Sep 24 08:52:55 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 19024858 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.2728614812 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 42288515 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4238328480 | Sep 24 08:52:40 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 91075341 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.54186414 | Sep 24 08:52:53 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 47336278 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.522427628 | Sep 24 08:52:40 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 55370296 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.393508978 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 63363679 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1367057847 | Sep 24 08:52:55 AM UTC 24 | Sep 24 08:52:57 AM UTC 24 | 27953887 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2902096206 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:58 AM UTC 24 | 82593862 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.779052404 | Sep 24 08:52:54 AM UTC 24 | Sep 24 08:52:58 AM UTC 24 | 153666374 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.424268708 | Sep 24 08:52:59 AM UTC 24 | Sep 24 08:53:01 AM UTC 24 | 14277269 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.3414182651 | Sep 24 08:52:52 AM UTC 24 | Sep 24 08:53:01 AM UTC 24 | 15063310 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2932300839 | Sep 24 08:52:52 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 94252581 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.279022470 | Sep 24 08:52:59 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 109043725 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.4114669483 | Sep 24 08:52:57 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 29577295 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3919225252 | Sep 24 08:52:57 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 19838532 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1899506139 | Sep 24 08:52:52 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 106831997 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1548904852 | Sep 24 08:52:50 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 22680821 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3956034322 | Sep 24 08:52:50 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 16064539 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.912487510 | Sep 24 08:52:59 AM UTC 24 | Sep 24 08:53:02 AM UTC 24 | 50610761 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.1553989283 | Sep 24 08:52:57 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 90343938 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2331528161 | Sep 24 08:52:40 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 44487536 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.2790159666 | Sep 24 08:52:50 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 239483712 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.252238326 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 16734113 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1200402570 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 12750427 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.4233523971 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 28544367 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.1338869172 | Sep 24 08:52:57 AM UTC 24 | Sep 24 08:53:03 AM UTC 24 | 203053302 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3108518374 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 24778069 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2160859546 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 61578782 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1892356450 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 84126182 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3866369741 | Sep 24 08:52:48 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 76009389 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3965465837 | Sep 24 08:52:51 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 63837335 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2307643052 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 107652701 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3127881416 | Sep 24 08:52:52 AM UTC 24 | Sep 24 08:53:04 AM UTC 24 | 118602142 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1298032614 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:05 AM UTC 24 | 117045284 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4112628679 | Sep 24 08:52:48 AM UTC 24 | Sep 24 08:53:05 AM UTC 24 | 35848206 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3250051498 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:05 AM UTC 24 | 118244430 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2392293576 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:05 AM UTC 24 | 32931660 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2657405923 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:05 AM UTC 24 | 21961778 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.904738205 | Sep 24 08:52:48 AM UTC 24 | Sep 24 08:53:05 AM UTC 24 | 675499617 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.3614496731 | Sep 24 08:52:58 AM UTC 24 | Sep 24 08:53:06 AM UTC 24 | 89771765 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.553006039 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:06 AM UTC 24 | 17338620 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.2237503790 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 11028025 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3287904379 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 14239229 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2493193117 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 14778240 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.2407413191 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 41311690 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3108176294 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 24637696 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.500422050 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 14643980 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.415371577 | Sep 24 08:53:05 AM UTC 24 | Sep 24 08:53:07 AM UTC 24 | 52658186 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2807653177 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 27607222 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2187813635 | Sep 24 08:52:52 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 12760989 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1735181124 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 14419918 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3101460605 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 22613016 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.1925681989 | Sep 24 08:53:04 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 25304819 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.4102536230 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 35491841 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.3727320168 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 15956927 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1888342706 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 49467568 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3957964549 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 21227834 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.1953568162 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 12816155 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.4266038743 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 30689599 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.394683467 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 14028206 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.1658735643 | Sep 24 08:53:06 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 36818426 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1873430340 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 100841224 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2352435659 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 33351816 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1629693399 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:08 AM UTC 24 | 57464863 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1477183738 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:09 AM UTC 24 | 60404995 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2897352962 | Sep 24 08:53:07 AM UTC 24 | Sep 24 08:53:09 AM UTC 24 | 41543961 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.435656849 | Sep 24 08:53:07 AM UTC 24 | Sep 24 08:53:09 AM UTC 24 | 15656482 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.739670275 | Sep 24 08:53:07 AM UTC 24 | Sep 24 08:53:09 AM UTC 24 | 15855837 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.2450053343 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:09 AM UTC 24 | 54995583 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.952284539 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 171049955 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3581133535 | Sep 24 08:53:03 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 72563185 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3308898323 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 19678726 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.2524971365 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 11793603 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2945645803 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 12275642 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.1674989182 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 18368727 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2774732251 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 36818794 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.4205385262 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 46621366 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2994126462 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 12546608 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.743608318 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 56313247 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1939699905 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 13133473 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.4168891611 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 40966848 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.3679087537 | Sep 24 08:53:08 AM UTC 24 | Sep 24 08:53:10 AM UTC 24 | 24445608 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.578505284 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 115867190 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:09 AM UTC 24 |
| Peak memory | 226728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578505284 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.578505284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_genbits.3483975203 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 33963227 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:10 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483975203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3483975203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_sec_cm.3406057086 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1789961058 ps |
| CPU time | 7.2 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:15 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406057086 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3406057086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_alert.2975710483 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 51157644 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975710483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_alert.2975710483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_stress_all.4062587858 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 498384378 ps |
| CPU time | 4.91 seconds |
| Started | Sep 24 08:48:06 AM UTC 24 |
| Finished | Sep 24 08:48:12 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062587858 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4062587858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.1793729712 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3908779141 ps |
| CPU time | 65.56 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:49:24 AM UTC 24 |
| Peak memory | 230312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793729712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_ with_rand_reset.1793729712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.391208236 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 55302967 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391208236 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.391208236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_alert.1991584375 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 58005302 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:48:20 AM UTC 24 |
| Finished | Sep 24 08:48:23 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991584375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_alert.1991584375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_alert.3426322330 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 93813582 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426322330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_alert.3426322330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_intr.4227089521 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20220888 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:48:28 AM UTC 24 |
| Finished | Sep 24 08:48:33 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227089521 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4227089521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_genbits.2305809534 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 70709125 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:48:11 AM UTC 24 |
| Finished | Sep 24 08:48:16 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305809534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2305809534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_alert.1026317116 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 39877914 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:48:36 AM UTC 24 |
| Finished | Sep 24 08:49:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026317116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.edn_alert.1026317116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_alert.4289442766 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 32721386 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:33 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289442766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_alert.4289442766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_disable.532152496 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 17460521 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:09 AM UTC 24 |
| Peak memory | 226644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532152496 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.532152496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_stress_all.2173597194 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 308048597 ps |
| CPU time | 4.39 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173597194 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2173597194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_regwen.2445823751 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 16547074 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:48:37 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445823751 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 9.edn_regwen.2445823751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_alert.2409370394 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 102470829 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409370394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_alert.2409370394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.1548715010 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 426736636 ps |
| CPU time | 6.87 seconds |
| Started | Sep 24 08:52:23 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548715010 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1548715010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_disable.222610221 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 21942031 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:49:47 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222610221 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.222610221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_disable.665145808 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 22829110 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:48:32 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 227020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665145808 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.665145808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_disable.2160559056 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 13916671 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160559056 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2160559056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.3631523946 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 92494843 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:48 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631523946 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.3631523946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.351432792 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 35023788 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:52:27 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351432792 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.351432792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.4281266106 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 104713495 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281266106 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.4281266106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_alert.529364708 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 49713094 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:49:10 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529364708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.edn_alert.529364708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.3941470834 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1545916841 ps |
| CPU time | 29.2 seconds |
| Started | Sep 24 08:48:41 AM UTC 24 |
| Finished | Sep 24 08:49:21 AM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941470834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all _with_rand_reset.3941470834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_alert.563182750 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 89712449 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563182750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 25.edn_alert.563182750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_intr.1918906340 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 24005950 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:49:32 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918906340 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1918906340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_alert.2789669452 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 24634740 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:50:25 AM UTC 24 |
| Finished | Sep 24 08:50:27 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789669452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_alert.2789669452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_alert.3429867885 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 60881699 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 230940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429867885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.edn_alert.3429867885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_alert.896594971 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 84692086 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:48:06 AM UTC 24 |
| Finished | Sep 24 08:48:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896594971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.edn_alert.896594971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_alert.1339994306 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 92943668 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339994306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_alert.1339994306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_alert_test.2926901850 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 23149152 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:09 AM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926901850 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2926901850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_genbits.930116098 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 157998325 ps |
| CPU time | 3.62 seconds |
| Started | Sep 24 08:50:05 AM UTC 24 |
| Finished | Sep 24 08:50:10 AM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930116098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.edn_genbits.930116098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/59.edn_genbits.756573374 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 233534129 ps |
| CPU time | 2.66 seconds |
| Started | Sep 24 08:50:44 AM UTC 24 |
| Finished | Sep 24 08:50:48 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756573374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 59.edn_genbits.756573374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/59.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_disable.3288118327 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 23599657 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:48:52 AM UTC 24 |
| Finished | Sep 24 08:48:54 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288118327 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3288118327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.2590092596 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 28050081 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:48:48 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590092596 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.2590092596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/102.edn_alert.1168538298 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 21980683 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168538298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 102.edn_alert.1168538298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/102.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/123.edn_alert.1498700284 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 32004847 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 08:51:35 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498700284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 123.edn_alert.1498700284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/123.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/134.edn_alert.3389124323 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 165813479 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389124323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 134.edn_alert.3389124323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/134.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/148.edn_alert.3929368202 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 72196995 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929368202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 148.edn_alert.3929368202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/148.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_err.571208786 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 28768524 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 246736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571208786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 20.edn_err.571208786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_disable.3662771787 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 16603928 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:49:33 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 226724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662771787 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3662771787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_err.3946671977 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 96226960 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946671977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 23.edn_err.3946671977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_disable.2771645281 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 24573327 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771645281 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2771645281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.1733777986 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 89834810 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733777986 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.1733777986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_disable.785438986 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 14538318 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785438986 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.785438986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_disable.1853681165 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 35918646 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:50:09 AM UTC 24 |
| Finished | Sep 24 08:50:12 AM UTC 24 |
| Peak memory | 226940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853681165 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1853681165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_err.2491417843 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 47963684 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:50:20 AM UTC 24 |
| Finished | Sep 24 08:50:22 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491417843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 44.edn_err.2491417843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_disable.2799165290 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 11130516 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:48:38 AM UTC 24 |
| Finished | Sep 24 08:48:55 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799165290 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2799165290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/113.edn_genbits.3522274517 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 69779168 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:51:29 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 231232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522274517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3522274517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/113.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_stress_all.879511603 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 714050551 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 08:48:39 AM UTC 24 |
| Finished | Sep 24 08:48:55 AM UTC 24 |
| Peak memory | 228076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879511603 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.879511603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/103.edn_genbits.2611485708 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 67196141 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611485708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2611485708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/103.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_intr.1091923911 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 24966532 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:50:01 AM UTC 24 |
| Finished | Sep 24 08:50:04 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091923911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1091923911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_genbits.3552562809 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 289605827 ps |
| CPU time | 2.83 seconds |
| Started | Sep 24 08:49:58 AM UTC 24 |
| Finished | Sep 24 08:50:01 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552562809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3552562809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.1422555085 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 256523881 ps |
| CPU time | 3.34 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:29 AM UTC 24 |
| Peak memory | 216992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422555085 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1422555085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.4071591564 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 15084620 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071591564 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.4071591564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.1626684015 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 103528396 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:39 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626684015 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1626684015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/104.edn_genbits.4224182708 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 54997081 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:33 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224182708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4224182708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/104.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/112.edn_genbits.1166554640 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 172699571 ps |
| CPU time | 2.64 seconds |
| Started | Sep 24 08:51:18 AM UTC 24 |
| Finished | Sep 24 08:51:33 AM UTC 24 |
| Peak memory | 232096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166554640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1166554640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/112.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/115.edn_genbits.2564232063 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 50988997 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:51:33 AM UTC 24 |
| Finished | Sep 24 08:51:39 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564232063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2564232063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/115.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.2519745769 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 14959476928 ps |
| CPU time | 114.08 seconds |
| Started | Sep 24 08:48:56 AM UTC 24 |
| Finished | Sep 24 08:51:03 AM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519745769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all _with_rand_reset.2519745769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/151.edn_genbits.3060163389 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 97146262 ps |
| CPU time | 1.97 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060163389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3060163389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/151.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/157.edn_genbits.719222962 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 37598163 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719222962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 157.edn_genbits.719222962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/157.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/185.edn_genbits.1825722258 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 114574886 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825722258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1825722258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/185.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/217.edn_genbits.3599833715 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 540537670 ps |
| CPU time | 5.67 seconds |
| Started | Sep 24 08:52:01 AM UTC 24 |
| Finished | Sep 24 08:52:15 AM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599833715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3599833715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/217.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/289.edn_genbits.2363996728 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 74289371 ps |
| CPU time | 2.62 seconds |
| Started | Sep 24 08:52:18 AM UTC 24 |
| Finished | Sep 24 08:52:39 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363996728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2363996728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/289.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_intr.3605853746 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 22155647 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605853746 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3605853746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/113.edn_alert.1480116007 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 30698299 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:33 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480116007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 113.edn_alert.1480116007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/113.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_alert.2870055864 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 137143862 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:49:32 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870055864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.edn_alert.2870055864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_err.1942085190 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 327655189 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:48:06 AM UTC 24 |
| Finished | Sep 24 08:48:09 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942085190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.edn_err.1942085190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/107.edn_genbits.7063970 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 62666080 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7063970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_ genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 107.edn_genbits.7063970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/107.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.731177314 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 43240064 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731177314 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.731177314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.2577781361 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 18826038 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:27 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577781361 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2577781361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2913921527 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 31188800 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2913921527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2913921527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.3706218902 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 22747468 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706218902 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3706218902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.2831557782 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 46865110 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:27 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831557782 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2831557782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.3182203703 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 224112119 ps |
| CPU time | 2.5 seconds |
| Started | Sep 24 08:52:23 AM UTC 24 |
| Finished | Sep 24 08:52:28 AM UTC 24 |
| Peak memory | 227140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182203703 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3182203703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.97596424 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 196059211 ps |
| CPU time | 4.59 seconds |
| Started | Sep 24 08:52:27 AM UTC 24 |
| Finished | Sep 24 08:52:36 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97596424 -assert nopostproc +UVM_TESTNAME=edn_ base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.97596424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.92407250 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 22232151 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92407250 -assert nopostproc +UVM_TESTNAME=edn_ base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.92407250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2457854318 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 38184744 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:52:29 AM UTC 24 |
| Finished | Sep 24 08:52:32 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2457854318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2457854318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.718365995 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 14731840 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:52:26 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718365995 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.718365995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1249388165 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 13630683 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249388165 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1249388165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.2828572113 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 36604959 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:52:27 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828572113 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.2828572113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.907188232 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 158576453 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:39 AM UTC 24 |
| Peak memory | 231240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907188232 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.907188232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.2130619498 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 188857567 ps |
| CPU time | 2.78 seconds |
| Started | Sep 24 08:52:25 AM UTC 24 |
| Finished | Sep 24 08:52:39 AM UTC 24 |
| Peak memory | 217108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130619498 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2130619498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1487673737 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 35897734 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:52:49 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1487673737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1487673737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.3487536031 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 36029729 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:52:49 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487536031 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3487536031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.1136464868 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 31538601 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 08:52:49 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136464868 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1136464868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1323788837 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 34038915 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:52:49 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323788837 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.1323788837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4112628679 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 35848206 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 08:52:48 AM UTC 24 |
| Finished | Sep 24 08:53:05 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112628679 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4112628679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.904738205 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 675499617 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 08:52:48 AM UTC 24 |
| Finished | Sep 24 08:53:05 AM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904738205 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.904738205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3956034322 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 16064539 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:52:50 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3956034322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3956034322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1858054209 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 57486899 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:52:50 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858054209 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1858054209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.4169358057 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 14654625 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:52:50 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169358057 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4169358057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1548904852 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 22680821 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:52:50 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548904852 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.1548904852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2472048818 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 250899986 ps |
| CPU time | 2.39 seconds |
| Started | Sep 24 08:52:49 AM UTC 24 |
| Finished | Sep 24 08:52:53 AM UTC 24 |
| Peak memory | 227156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472048818 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2472048818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3853614720 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 142314410 ps |
| CPU time | 3.11 seconds |
| Started | Sep 24 08:52:50 AM UTC 24 |
| Finished | Sep 24 08:52:54 AM UTC 24 |
| Peak memory | 216908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853614720 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3853614720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2932300839 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 94252581 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:52:52 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2932300839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2932300839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3127881416 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 118602142 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:52:52 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127881416 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3127881416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2187813635 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 12760989 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:52:52 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187813635 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2187813635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.3414182651 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 15063310 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:52:52 AM UTC 24 |
| Finished | Sep 24 08:53:01 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414182651 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.3414182651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.2790159666 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 239483712 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 08:52:50 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790159666 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2790159666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3965465837 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 63837335 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 08:52:51 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965465837 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3965465837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.393508978 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 63363679 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =393508978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.393508978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.2728614812 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 42288515 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728614812 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2728614812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.3371724996 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 124583673 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:56 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371724996 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3371724996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1264218570 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 93701200 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264218570 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.1264218570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1899506139 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 106831997 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 08:52:52 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899506139 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1899506139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.54186414 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 47336278 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:52:53 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54186414 -assert nopostproc +UVM_TESTNAME=e dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.54186414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1367057847 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 27953887 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:52:55 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1367057847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1367057847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.2219732151 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 27798108 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219732151 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2219732151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2752455681 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 19461450 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752455681 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2752455681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3434424811 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 19024858 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:52:55 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434424811 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.3434424811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.779052404 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 153666374 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:58 AM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779052404 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.779052404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2902096206 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 82593862 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:52:54 AM UTC 24 |
| Finished | Sep 24 08:52:58 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902096206 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2902096206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1298032614 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 117045284 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:05 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1298032614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1298032614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3919225252 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 19838532 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:52:57 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919225252 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3919225252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.4114669483 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 29577295 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 08:52:57 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114669483 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4114669483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.4233523971 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 28544367 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233523971 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.4233523971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.1338869172 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 203053302 ps |
| CPU time | 2.47 seconds |
| Started | Sep 24 08:52:57 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 227140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338869172 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1338869172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.1553989283 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 90343938 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:52:57 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 223788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553989283 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1553989283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2160859546 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 61578782 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2160859546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2160859546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1200402570 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 12750427 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200402570 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1200402570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.252238326 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 16734113 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252238326 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.252238326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3108518374 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 24778069 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108518374 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.3108518374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.3614496731 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 89771765 ps |
| CPU time | 3.43 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:06 AM UTC 24 |
| Peak memory | 227140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614496731 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3614496731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2307643052 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 107652701 ps |
| CPU time | 2.24 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 216912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307643052 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2307643052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2352435659 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 33351816 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2352435659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2352435659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.424268708 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 14277269 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:52:59 AM UTC 24 |
| Finished | Sep 24 08:53:01 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424268708 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.424268708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.912487510 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 50610761 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:52:59 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912487510 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.912487510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.279022470 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 109043725 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:52:59 AM UTC 24 |
| Finished | Sep 24 08:53:02 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279022470 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.279022470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3250051498 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 118244430 ps |
| CPU time | 2.1 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:05 AM UTC 24 |
| Peak memory | 227284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250051498 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3250051498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1892356450 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 84126182 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:52:58 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 214744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892356450 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1892356450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1873430340 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 100841224 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1873430340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1873430340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2392293576 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 32931660 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:05 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392293576 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2392293576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2657405923 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 21961778 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:05 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657405923 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2657405923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1629693399 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 57464863 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629693399 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1629693399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.2450053343 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 54995583 ps |
| CPU time | 2.32 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:09 AM UTC 24 |
| Peak memory | 227144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450053343 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2450053343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1477183738 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 60404995 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:09 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477183738 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1477183738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2807653177 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 27607222 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2807653177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2807653177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3287904379 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 14239229 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287904379 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3287904379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.2237503790 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 11028025 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237503790 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2237503790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2493193117 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 14778240 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493193117 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.2493193117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3581133535 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 72563185 ps |
| CPU time | 2.64 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 227220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581133535 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3581133535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.952284539 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 171049955 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 08:53:03 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 217032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952284539 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.952284539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.2307853892 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 63019410 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307853892 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2307853892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.2579008189 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 36321561 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 08:52:32 AM UTC 24 |
| Finished | Sep 24 08:52:39 AM UTC 24 |
| Peak memory | 217028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579008189 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2579008189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2904854653 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 40291019 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:52:32 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904854653 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2904854653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.463818367 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 44108926 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =463818367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.463818367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.1155338043 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 14284950 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:52:32 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155338043 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1155338043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.1910058468 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 23603135 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:52:32 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 214668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910058468 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1910058468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.1512944782 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 17912847 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512944782 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.1512944782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.4198486396 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 25754888 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:52:30 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198486396 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4198486396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.2436266601 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 159827815 ps |
| CPU time | 3.28 seconds |
| Started | Sep 24 08:52:30 AM UTC 24 |
| Finished | Sep 24 08:52:34 AM UTC 24 |
| Peak memory | 216856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436266601 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2436266601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3108176294 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 24637696 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108176294 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3108176294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.2407413191 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 41311690 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407413191 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2407413191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.500422050 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 14643980 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500422050 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.500422050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.553006039 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 17338620 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:06 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553006039 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.553006039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.1925681989 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 25304819 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:53:04 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925681989 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1925681989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.415371577 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 52658186 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:53:05 AM UTC 24 |
| Finished | Sep 24 08:53:07 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415371577 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.415371577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.4102536230 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 35491841 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102536230 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4102536230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1735181124 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 14419918 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735181124 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1735181124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.4266038743 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 30689599 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266038743 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4266038743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3101460605 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 22613016 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101460605 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3101460605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.3143164763 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 69445181 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143164763 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3143164763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.3201689842 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 408040361 ps |
| CPU time | 4.79 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:41 AM UTC 24 |
| Peak memory | 216860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201689842 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3201689842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.1810048530 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 42277190 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810048530 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1810048530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2261340233 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 36866381 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:52:37 AM UTC 24 |
| Finished | Sep 24 08:52:39 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2261340233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2261340233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.3732564488 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 19413512 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732564488 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3732564488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.1286351879 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 12837781 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:37 AM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286351879 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1286351879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.736139209 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 94587314 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:52:35 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736139209 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.736139209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.3073441003 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 26015704 ps |
| CPU time | 1.93 seconds |
| Started | Sep 24 08:52:34 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 224916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073441003 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3073441003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.3727320168 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15956927 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727320168 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3727320168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.394683467 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 14028206 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394683467 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.394683467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.1953568162 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 12816155 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953568162 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1953568162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3957964549 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 21227834 ps |
| CPU time | 0.81 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957964549 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3957964549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1888342706 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 49467568 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888342706 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1888342706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.1658735643 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 36818426 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:53:06 AM UTC 24 |
| Finished | Sep 24 08:53:08 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658735643 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1658735643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.435656849 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 15656482 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:53:07 AM UTC 24 |
| Finished | Sep 24 08:53:09 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435656849 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.435656849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.739670275 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 15855837 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:53:07 AM UTC 24 |
| Finished | Sep 24 08:53:09 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739670275 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.739670275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2897352962 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 41543961 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:53:07 AM UTC 24 |
| Finished | Sep 24 08:53:09 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897352962 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2897352962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.2524971365 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 11793603 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524971365 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2524971365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.2396226277 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 60066460 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:42 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396226277 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2396226277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.2422154884 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 259816321 ps |
| CPU time | 6.07 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:46 AM UTC 24 |
| Peak memory | 216788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422154884 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2422154884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.523945581 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 17586746 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:41 AM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523945581 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.523945581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2294612648 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 106518527 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2294612648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2294612648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2875554022 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 20115606 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:41 AM UTC 24 |
| Peak memory | 214712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875554022 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2875554022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.3602397156 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 60177523 ps |
| CPU time | 0.88 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:41 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602397156 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3602397156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3758863977 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 56707054 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:42 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758863977 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3758863977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.3402238665 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 2705763245 ps |
| CPU time | 4.33 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:45 AM UTC 24 |
| Peak memory | 231380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402238665 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3402238665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.3260521250 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 73731417 ps |
| CPU time | 2.28 seconds |
| Started | Sep 24 08:52:38 AM UTC 24 |
| Finished | Sep 24 08:52:42 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260521250 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3260521250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1939699905 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 13133473 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939699905 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1939699905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3308898323 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 19678726 ps |
| CPU time | 0.86 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308898323 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3308898323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2994126462 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 12546608 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994126462 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2994126462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2945645803 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 12275642 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945645803 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2945645803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2774732251 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 36818794 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774732251 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2774732251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.1674989182 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 18368727 ps |
| CPU time | 0.83 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674989182 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1674989182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.743608318 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 56313247 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743608318 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.743608318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.4205385262 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 46621366 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205385262 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4205385262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.4168891611 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 40966848 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168891611 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4168891611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.3679087537 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 24445608 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:53:08 AM UTC 24 |
| Finished | Sep 24 08:53:10 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679087537 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3679087537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.578905887 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 23239448 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =578905887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.578905887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.3729392116 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 76897315 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729392116 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3729392116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3582422072 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 25480696 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582422072 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3582422072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.2871065271 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 34059400 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871065271 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.2871065271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1620109110 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 31689674 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:50 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620109110 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1620109110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.2990214094 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 81517658 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990214094 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2990214094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3776428052 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 90388380 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3776428052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3776428052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.1924420523 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 17247910 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924420523 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1924420523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.133733970 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 34819686 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133733970 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.133733970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.2941369103 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 52584475 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:52 AM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941369103 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.2941369103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.1764826608 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 136974966 ps |
| CPU time | 3.09 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:51 AM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764826608 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1764826608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.3750661409 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 69632167 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 08:52:39 AM UTC 24 |
| Finished | Sep 24 08:52:53 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750661409 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3750661409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4238328480 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 91075341 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4238328480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.4238328480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1189361190 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 19409048 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:56 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189361190 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1189361190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1981746555 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 37012553 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:56 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981746555 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1981746555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.4245016843 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 28651450 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:56 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245016843 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.4245016843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.522427628 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 55370296 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:57 AM UTC 24 |
| Peak memory | 227152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522427628 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.522427628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3613538980 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 108272008 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:53 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613538980 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3613538980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1904050487 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 108802516 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 08:52:42 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1904050487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1904050487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.521509881 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 50604553 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 08:52:42 AM UTC 24 |
| Finished | Sep 24 08:52:47 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521509881 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.521509881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1199998331 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 44333994 ps |
| CPU time | 0.79 seconds |
| Started | Sep 24 08:52:42 AM UTC 24 |
| Finished | Sep 24 08:52:47 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199998331 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1199998331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2426279022 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 66250704 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:52:42 AM UTC 24 |
| Finished | Sep 24 08:52:48 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426279022 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.2426279022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2331528161 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 44487536 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:53:03 AM UTC 24 |
| Peak memory | 224836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331528161 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2331528161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2088798883 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 94970865 ps |
| CPU time | 2.59 seconds |
| Started | Sep 24 08:52:40 AM UTC 24 |
| Finished | Sep 24 08:52:58 AM UTC 24 |
| Peak memory | 227344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088798883 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2088798883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3866369741 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 76009389 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:52:48 AM UTC 24 |
| Finished | Sep 24 08:53:04 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3866369741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3866369741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1760080549 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 81390226 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:52:46 AM UTC 24 |
| Finished | Sep 24 08:52:48 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760080549 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1760080549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.2703282237 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 20472873 ps |
| CPU time | 0.76 seconds |
| Started | Sep 24 08:52:44 AM UTC 24 |
| Finished | Sep 24 08:52:46 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703282237 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2703282237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.2442962774 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 17889010 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:52:47 AM UTC 24 |
| Finished | Sep 24 08:52:49 AM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442962774 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.2442962774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.2315620588 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 51296796 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:52:42 AM UTC 24 |
| Finished | Sep 24 08:52:48 AM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315620588 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2315620588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3073326995 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 295126670 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:52:43 AM UTC 24 |
| Finished | Sep 24 08:52:48 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073326995 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3073326995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_genbits.2527526378 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 55903770 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:48:06 AM UTC 24 |
| Finished | Sep 24 08:48:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527526378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2527526378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_intr.3129945589 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30559612 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:48:06 AM UTC 24 |
| Finished | Sep 24 08:48:08 AM UTC 24 |
| Peak memory | 237172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129945589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3129945589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_regwen.3918134419 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 37678162 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:48:05 AM UTC 24 |
| Finished | Sep 24 08:48:07 AM UTC 24 |
| Peak memory | 217240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918134419 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.edn_regwen.3918134419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/0.edn_smoke.1501530606 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 18654223 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:48:05 AM UTC 24 |
| Finished | Sep 24 08:48:07 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501530606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_smoke.1501530606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_alert_test.1588875931 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 18806920 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588875931 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1588875931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_disable.1226444720 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 18129376 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226444720 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1226444720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.2262962049 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 60748068 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262962049 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.2262962049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_err.4752181 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 160170670 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 243192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4752181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.edn_err.4752181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_intr.1290420251 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 21573475 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 226892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290420251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1290420251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_regwen.2863978235 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15713902 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:09 AM UTC 24 |
| Peak memory | 216580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863978235 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.edn_regwen.2863978235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_sec_cm.3039813089 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 938681404 ps |
| CPU time | 4.37 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:21 AM UTC 24 |
| Peak memory | 258672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039813089 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3039813089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_smoke.2933781622 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 17698106 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:09 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933781622 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_smoke.2933781622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/1.edn_stress_all.3803360588 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 389279474 ps |
| CPU time | 2.21 seconds |
| Started | Sep 24 08:48:07 AM UTC 24 |
| Finished | Sep 24 08:48:11 AM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803360588 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3803360588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_alert.1579025769 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 39931069 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:48:44 AM UTC 24 |
| Finished | Sep 24 08:48:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579025769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_alert.1579025769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_alert_test.3341780702 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 68136458 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:48:48 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341780702 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3341780702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_disable.2403812918 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 33957095 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:48:47 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403812918 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2403812918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_err.1912840846 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 29622040 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:48:47 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912840846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 10.edn_err.1912840846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/10.edn_intr.742681600 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 64363502 ps |
| CPU time | 0.79 seconds |
| Started | Sep 24 08:48:44 AM UTC 24 |
| Finished | Sep 24 08:48:46 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742681600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.742681600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/102.edn_genbits.2792381572 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 927780309 ps |
| CPU time | 7.19 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:28 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792381572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2792381572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/102.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/103.edn_alert.3502216289 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 32228780 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502216289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 103.edn_alert.3502216289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/103.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/104.edn_alert.1533820904 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 26319352 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533820904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 104.edn_alert.1533820904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/104.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/105.edn_alert.2484597491 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 127755752 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484597491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 105.edn_alert.2484597491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/105.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/105.edn_genbits.2925053984 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 56339821 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:33 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925053984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2925053984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/105.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/106.edn_alert.1066412266 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 375238542 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:16 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066412266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 106.edn_alert.1066412266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/106.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/106.edn_genbits.4114596008 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 195010272 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:51:13 AM UTC 24 |
| Finished | Sep 24 08:51:33 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114596008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4114596008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/106.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/107.edn_alert.1576203924 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 23010716 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576203924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 107.edn_alert.1576203924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/107.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/108.edn_alert.1654636546 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 24819513 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654636546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 108.edn_alert.1654636546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/108.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/108.edn_genbits.1582412028 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 63826597 ps |
| CPU time | 2.57 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:35 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582412028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1582412028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/108.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/109.edn_alert.2844511017 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 64693906 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844511017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 109.edn_alert.2844511017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/109.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/109.edn_genbits.4159064931 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 96899672 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159064931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4159064931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/109.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_alert.1132691839 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 150437322 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:48:51 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132691839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_alert.1132691839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_alert_test.768281030 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 18590564 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:48:52 AM UTC 24 |
| Finished | Sep 24 08:48:54 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768281030 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.768281030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3649592270 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 21876131 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:48:52 AM UTC 24 |
| Finished | Sep 24 08:48:54 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649592270 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3649592270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_err.731083304 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 28540464 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:48:52 AM UTC 24 |
| Finished | Sep 24 08:48:54 AM UTC 24 |
| Peak memory | 238212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731083304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 11.edn_err.731083304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_genbits.1083571460 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 40154390 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:48:48 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083571460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1083571460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_intr.4214949064 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 23542186 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:48:51 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214949064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4214949064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_smoke.4004244609 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 38237560 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:48:48 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004244609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_smoke.4004244609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_stress_all.2080720231 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 205666184 ps |
| CPU time | 3.58 seconds |
| Started | Sep 24 08:48:48 AM UTC 24 |
| Finished | Sep 24 08:48:56 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080720231 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2080720231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.3679153258 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 10673167555 ps |
| CPU time | 116.39 seconds |
| Started | Sep 24 08:48:49 AM UTC 24 |
| Finished | Sep 24 08:50:49 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679153258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all _with_rand_reset.3679153258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/110.edn_alert.2395612160 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 66374261 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:33 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395612160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 110.edn_alert.2395612160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/110.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/110.edn_genbits.2793335475 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 56623716 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:14 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793335475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2793335475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/110.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/111.edn_alert.249194641 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 55252031 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:51:17 AM UTC 24 |
| Finished | Sep 24 08:51:34 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249194641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 111.edn_alert.249194641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/111.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/111.edn_genbits.1246401876 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 24248609 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:51:15 AM UTC 24 |
| Finished | Sep 24 08:51:18 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246401876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1246401876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/111.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/112.edn_alert.1399541601 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 71798055 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:51:20 AM UTC 24 |
| Finished | Sep 24 08:51:32 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399541601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 112.edn_alert.1399541601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/112.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/114.edn_alert.3504506228 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 28426992 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:51:33 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504506228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 114.edn_alert.3504506228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/114.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/114.edn_genbits.3122482150 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 69107576 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:51:33 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122482150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3122482150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/114.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/115.edn_alert.2159417893 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 156469086 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:33 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159417893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 115.edn_alert.2159417893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/115.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/116.edn_alert.1268533530 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 119995495 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:37 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268533530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 116.edn_alert.1268533530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/116.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/116.edn_genbits.4280659098 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 49240832 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280659098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4280659098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/116.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/117.edn_alert.1092963165 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 32279934 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092963165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 117.edn_alert.1092963165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/117.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/117.edn_genbits.3365167188 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 66420211 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:37 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365167188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3365167188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/117.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/118.edn_alert.678529642 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 64226189 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678529642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 118.edn_alert.678529642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/118.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/118.edn_genbits.1039892273 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 37516626 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039892273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1039892273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/118.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/119.edn_alert.2397007243 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 44516754 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 228912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397007243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 119.edn_alert.2397007243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/119.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/119.edn_genbits.1251939818 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 90459957 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251939818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1251939818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/119.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_alert.3535270136 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 67616089 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:48:54 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535270136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_alert.3535270136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_alert_test.1817040783 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 41494775 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:48:54 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 226596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817040783 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1817040783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_disable.1756677129 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 39118703 ps |
| CPU time | 0.78 seconds |
| Started | Sep 24 08:48:54 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756677129 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1756677129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.695114457 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 51550850 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:48:54 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695114457 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.695114457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_err.724830972 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 27805332 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:48:54 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 238276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724830972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 12.edn_err.724830972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_genbits.4253760825 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 137571534 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:48:53 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253760825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4253760825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_smoke.1554740448 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 40975791 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:48:53 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554740448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_smoke.1554740448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_stress_all.2589470402 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 219869398 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:48:53 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 226940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589470402 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2589470402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.1638290378 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3452389182 ps |
| CPU time | 19.04 seconds |
| Started | Sep 24 08:48:53 AM UTC 24 |
| Finished | Sep 24 08:49:25 AM UTC 24 |
| Peak memory | 230368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638290378 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all _with_rand_reset.1638290378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/120.edn_alert.2610921603 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 90265751 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610921603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 120.edn_alert.2610921603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/120.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/120.edn_genbits.2032533545 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 37191891 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032533545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2032533545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/120.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/121.edn_alert.76448348 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 27726145 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76448348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.76448348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/121.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/121.edn_genbits.3655407575 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 70996672 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 230232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655407575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3655407575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/121.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/122.edn_alert.1570317709 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 25712940 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 230872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570317709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 122.edn_alert.1570317709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/122.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/122.edn_genbits.3815098704 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 144187242 ps |
| CPU time | 3.24 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:40 AM UTC 24 |
| Peak memory | 231916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815098704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3815098704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/122.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/123.edn_genbits.4124653196 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 46553226 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:51:34 AM UTC 24 |
| Finished | Sep 24 08:51:37 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124653196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.4124653196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/123.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/124.edn_alert.626106975 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 24721437 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:36 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 228912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626106975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 124.edn_alert.626106975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/124.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/124.edn_genbits.1641699354 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 108696342 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:51:35 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 228928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641699354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1641699354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/124.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/125.edn_alert.2509519345 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 161889099 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:51:36 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509519345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 125.edn_alert.2509519345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/125.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/125.edn_genbits.2200032014 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 385697166 ps |
| CPU time | 4.27 seconds |
| Started | Sep 24 08:51:36 AM UTC 24 |
| Finished | Sep 24 08:51:41 AM UTC 24 |
| Peak memory | 232112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200032014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2200032014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/125.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/126.edn_alert.2228894605 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 62916017 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:51:36 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228894605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 126.edn_alert.2228894605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/126.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/126.edn_genbits.1324528414 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 30173440 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:51:36 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324528414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1324528414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/126.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/127.edn_alert.1199361868 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 248890885 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:51:38 AM UTC 24 |
| Finished | Sep 24 08:51:40 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199361868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 127.edn_alert.1199361868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/127.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/127.edn_genbits.3118377781 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 82318241 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:51:38 AM UTC 24 |
| Finished | Sep 24 08:51:40 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118377781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3118377781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/127.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/128.edn_alert.2450269862 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 95910003 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450269862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 128.edn_alert.2450269862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/128.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/128.edn_genbits.405848322 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 55297377 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:51:38 AM UTC 24 |
| Finished | Sep 24 08:51:41 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405848322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 128.edn_genbits.405848322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/128.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/129.edn_alert.1830734430 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 142499812 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830734430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 129.edn_alert.1830734430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/129.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/129.edn_genbits.228832650 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 26399776 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:41 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228832650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 129.edn_genbits.228832650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/129.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_alert_test.3445264395 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 137784574 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:48:56 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445264395 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3445264395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_disable.758409941 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 118466663 ps |
| CPU time | 0.81 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758409941 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.758409941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.4232290095 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 23188926 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232290095 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.4232290095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_err.1251975887 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 32443887 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 237172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251975887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 13.edn_err.1251975887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_genbits.1270169077 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 45955891 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270169077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1270169077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_intr.1020538978 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 22655778 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020538978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1020538978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_smoke.3294004733 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 32463311 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294004733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_smoke.3294004733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_stress_all.1475494297 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 50907975 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475494297 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1475494297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.953668550 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5275572462 ps |
| CPU time | 60.8 seconds |
| Started | Sep 24 08:48:55 AM UTC 24 |
| Finished | Sep 24 08:50:08 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953668550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_ with_rand_reset.953668550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/130.edn_alert.3952614527 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 85191775 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952614527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 130.edn_alert.3952614527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/130.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/130.edn_genbits.2115732315 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 42002417 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115732315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2115732315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/130.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/131.edn_alert.2272478092 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 37052504 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272478092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 131.edn_alert.2272478092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/131.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/131.edn_genbits.2157164891 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 53978730 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:41 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157164891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2157164891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/131.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/132.edn_alert.510319313 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 25803959 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510319313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 132.edn_alert.510319313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/132.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/132.edn_genbits.2962053234 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 62767058 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962053234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2962053234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/132.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/133.edn_alert.3725890814 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 68688444 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 226948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725890814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 133.edn_alert.3725890814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/133.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/133.edn_genbits.1701419218 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 42008430 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701419218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1701419218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/133.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/134.edn_genbits.624914812 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 42627286 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624914812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 134.edn_genbits.624914812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/134.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/135.edn_alert.3102492280 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 41910695 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102492280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 135.edn_alert.3102492280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/135.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/135.edn_genbits.248073197 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 65097586 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:51:39 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 228944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248073197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 135.edn_genbits.248073197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/135.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/136.edn_alert.3638849062 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 27601295 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638849062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 136.edn_alert.3638849062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/136.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/136.edn_genbits.3075215339 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 80570217 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075215339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3075215339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/136.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/137.edn_alert.1363715703 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 35087199 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363715703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 137.edn_alert.1363715703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/137.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/137.edn_genbits.3131288567 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 48692758 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:43 AM UTC 24 |
| Peak memory | 229256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131288567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3131288567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/137.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/138.edn_alert.202658638 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 27324345 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 231040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202658638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 138.edn_alert.202658638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/138.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/138.edn_genbits.1937571001 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 34055941 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937571001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1937571001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/138.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/139.edn_alert.2483336753 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 227082017 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483336753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 139.edn_alert.2483336753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/139.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/139.edn_genbits.4270780491 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 80276556 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:40 AM UTC 24 |
| Finished | Sep 24 08:51:42 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270780491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4270780491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/139.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_alert.2213003716 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 70502811 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:48:58 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213003716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_alert.2213003716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_alert_test.3670414036 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 65720456 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670414036 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3670414036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_disable.2479479457 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 28067690 ps |
| CPU time | 0.81 seconds |
| Started | Sep 24 08:49:00 AM UTC 24 |
| Finished | Sep 24 08:49:10 AM UTC 24 |
| Peak memory | 226852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479479457 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2479479457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.3350643327 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 27960508 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:49:03 AM UTC 24 |
| Finished | Sep 24 08:49:07 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350643327 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.3350643327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_err.3008875152 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 32014322 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:48:59 AM UTC 24 |
| Finished | Sep 24 08:49:10 AM UTC 24 |
| Peak memory | 238124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008875152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 14.edn_err.3008875152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_genbits.1855584491 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 40708235 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:48:56 AM UTC 24 |
| Finished | Sep 24 08:49:09 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855584491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1855584491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_intr.2599022190 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 21614719 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:48:57 AM UTC 24 |
| Finished | Sep 24 08:49:10 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599022190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2599022190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_smoke.3894954880 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 56441559 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:48:56 AM UTC 24 |
| Finished | Sep 24 08:49:08 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894954880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_smoke.3894954880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/14.edn_stress_all.2933407012 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 735049346 ps |
| CPU time | 3.24 seconds |
| Started | Sep 24 08:48:56 AM UTC 24 |
| Finished | Sep 24 08:49:11 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933407012 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2933407012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/14.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/140.edn_alert.1012264218 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 67177196 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:51:41 AM UTC 24 |
| Finished | Sep 24 08:51:43 AM UTC 24 |
| Peak memory | 231036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012264218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 140.edn_alert.1012264218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/140.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/140.edn_genbits.1242027095 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 34898507 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:41 AM UTC 24 |
| Finished | Sep 24 08:51:43 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242027095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1242027095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/140.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/141.edn_alert.3868162254 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 82125634 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:44 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868162254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 141.edn_alert.3868162254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/141.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/141.edn_genbits.3078890505 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 48768324 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:41 AM UTC 24 |
| Finished | Sep 24 08:51:43 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078890505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3078890505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/141.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/142.edn_alert.278827525 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 30726192 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:45 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278827525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 142.edn_alert.278827525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/142.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/142.edn_genbits.3243535184 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 48059546 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:45 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243535184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3243535184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/142.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/143.edn_alert.2631827238 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 44338238 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:45 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631827238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 143.edn_alert.2631827238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/143.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/143.edn_genbits.3650184536 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 153870024 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:45 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650184536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3650184536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/143.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/144.edn_alert.3738546711 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 137004237 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738546711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 144.edn_alert.3738546711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/144.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/144.edn_genbits.992991438 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 63817847 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:45 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992991438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 144.edn_genbits.992991438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/144.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/145.edn_alert.1619787802 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 93494533 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619787802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 145.edn_alert.1619787802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/145.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/145.edn_genbits.4073215938 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 40228134 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:45 AM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073215938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4073215938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/145.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/146.edn_alert.4178450247 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 35090654 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:47 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178450247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 146.edn_alert.4178450247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/146.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/146.edn_genbits.2887487415 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 166749719 ps |
| CPU time | 2.27 seconds |
| Started | Sep 24 08:51:42 AM UTC 24 |
| Finished | Sep 24 08:51:49 AM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887487415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2887487415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/146.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/147.edn_alert.2601486079 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 29844761 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:47 AM UTC 24 |
| Peak memory | 228996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601486079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 147.edn_alert.2601486079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/147.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/147.edn_genbits.2315854932 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 45596371 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315854932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2315854932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/147.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/148.edn_genbits.1181199489 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 32722915 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:47 AM UTC 24 |
| Peak memory | 228984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181199489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1181199489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/148.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/149.edn_alert.2537937253 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 88615655 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537937253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 149.edn_alert.2537937253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/149.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/149.edn_genbits.1513907605 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 34076152 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:47 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513907605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1513907605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/149.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_alert.4139641083 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 29138571 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 231040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139641083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.edn_alert.4139641083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_alert_test.507775218 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 16625494 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507775218 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.507775218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_disable.1098167740 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 68659033 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 226996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098167740 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1098167740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2008848843 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 72155633 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008848843 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2008848843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_err.790889334 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 28828817 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790889334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 15.edn_err.790889334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_genbits.2921408142 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 95330356 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921408142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2921408142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_intr.2538809480 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 34581251 ps |
| CPU time | 0.91 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538809480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2538809480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_smoke.943479240 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 25717416 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:10 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943479240 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.edn_smoke.943479240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/15.edn_stress_all.1283169736 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 557468091 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:14 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283169736 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1283169736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/15.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/150.edn_alert.1175748045 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 56263922 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175748045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 150.edn_alert.1175748045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/150.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/150.edn_genbits.4201195542 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 87394678 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201195542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4201195542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/150.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/151.edn_alert.167450825 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 129835293 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167450825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 151.edn_alert.167450825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/151.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/152.edn_alert.1839841802 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 31576480 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839841802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 152.edn_alert.1839841802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/152.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/152.edn_genbits.4125528294 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 47853725 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125528294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4125528294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/152.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/153.edn_alert.2235106822 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 327673631 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235106822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 153.edn_alert.2235106822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/153.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/153.edn_genbits.2417268867 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 71316664 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417268867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2417268867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/153.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/154.edn_alert.4159283155 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 57548260 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:46 AM UTC 24 |
| Peak memory | 231072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159283155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 154.edn_alert.4159283155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/154.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/154.edn_genbits.3543925556 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 55910292 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:51:44 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543925556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3543925556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/154.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/155.edn_alert.404191736 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 55221489 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404191736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 155.edn_alert.404191736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/155.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/155.edn_genbits.2797046057 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 48630275 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797046057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2797046057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/155.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/156.edn_alert.21601258 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 26874524 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21601258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.21601258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/156.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/156.edn_genbits.3661547211 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 36910777 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661547211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3661547211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/156.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/157.edn_alert.3840737011 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 25991733 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840737011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 157.edn_alert.3840737011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/157.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/158.edn_alert.905886283 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 114876836 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:46 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905886283 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 158.edn_alert.905886283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/158.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/158.edn_genbits.2054921852 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 46190127 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:51:45 AM UTC 24 |
| Finished | Sep 24 08:51:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054921852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2054921852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/158.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/159.edn_alert.1048447306 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 46997853 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:51:48 AM UTC 24 |
| Finished | Sep 24 08:51:50 AM UTC 24 |
| Peak memory | 231012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048447306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 159.edn_alert.1048447306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/159.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/159.edn_genbits.117717521 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 103888089 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:51:48 AM UTC 24 |
| Finished | Sep 24 08:51:50 AM UTC 24 |
| Peak memory | 231176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117717521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 159.edn_genbits.117717521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/159.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_alert.1786985830 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 22381542 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786985830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_alert.1786985830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_alert_test.2844697013 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 13615225 ps |
| CPU time | 0.97 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844697013 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2844697013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.3325533029 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 37215429 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325533029 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.3325533029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_err.1227360973 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 37277942 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 246860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227360973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 16.edn_err.1227360973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_genbits.2798009070 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 20828653 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798009070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2798009070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_intr.3098959243 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 22544935 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098959243 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3098959243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_smoke.4163498090 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 32189038 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:49:08 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163498090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_smoke.4163498090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/16.edn_stress_all.2704605669 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 122646932 ps |
| CPU time | 2.66 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704605669 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2704605669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/16.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/160.edn_alert.2224536447 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 70029731 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:51:48 AM UTC 24 |
| Finished | Sep 24 08:51:50 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224536447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 160.edn_alert.2224536447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/160.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/160.edn_genbits.2386690499 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 35038490 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:51:48 AM UTC 24 |
| Finished | Sep 24 08:51:50 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386690499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2386690499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/160.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/161.edn_alert.1023024625 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 36329955 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:51:48 AM UTC 24 |
| Finished | Sep 24 08:51:50 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023024625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 161.edn_alert.1023024625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/161.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/161.edn_genbits.1628243310 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 37418169 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:48 AM UTC 24 |
| Finished | Sep 24 08:51:50 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628243310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1628243310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/161.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/162.edn_alert.3385774606 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 22541836 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:51 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385774606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 162.edn_alert.3385774606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/162.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/162.edn_genbits.3833242547 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 285906976 ps |
| CPU time | 3.25 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:54 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833242547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3833242547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/162.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/163.edn_alert.1875728995 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 81761217 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:51 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875728995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 163.edn_alert.1875728995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/163.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/163.edn_genbits.4092688821 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 127436434 ps |
| CPU time | 3.14 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092688821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.4092688821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/163.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/164.edn_alert.710597417 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 80006040 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710597417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 164.edn_alert.710597417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/164.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/164.edn_genbits.3032146321 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 227709154 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:51 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032146321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3032146321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/164.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/165.edn_alert.1196878465 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 35406264 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196878465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 165.edn_alert.1196878465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/165.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/165.edn_genbits.3112589613 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 36078085 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112589613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3112589613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/165.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/166.edn_alert.2474103169 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 36816974 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474103169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 166.edn_alert.2474103169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/166.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/166.edn_genbits.100534500 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 25394961 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100534500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 166.edn_genbits.100534500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/166.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/167.edn_alert.2226314230 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 121043307 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226314230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 167.edn_alert.2226314230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/167.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/167.edn_genbits.1460797635 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 30273654 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460797635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1460797635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/167.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/168.edn_alert.184437865 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 37341413 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184437865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 168.edn_alert.184437865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/168.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/168.edn_genbits.2772183880 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 51031590 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772183880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2772183880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/168.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/169.edn_alert.934957734 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 47201812 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934957734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 169.edn_alert.934957734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/169.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/169.edn_genbits.2936805126 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 69515961 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:51:49 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936805126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2936805126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/169.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_alert_test.1991686653 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 39811688 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:49:11 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991686653 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1991686653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_disable.2750395377 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 33138971 ps |
| CPU time | 0.82 seconds |
| Started | Sep 24 08:49:11 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750395377 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2750395377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.777931043 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 23625968 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:49:11 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 226792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777931043 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.777931043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_err.1445986776 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 34854199 ps |
| CPU time | 1.02 seconds |
| Started | Sep 24 08:49:11 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 246656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445986776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 17.edn_err.1445986776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_genbits.1139608166 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 64955585 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139608166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1139608166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_intr.1935167717 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 30444057 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 237176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935167717 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1935167717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_smoke.146283281 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 37198144 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:29 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146283281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.edn_smoke.146283281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/17.edn_stress_all.1376434896 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 914586768 ps |
| CPU time | 4.46 seconds |
| Started | Sep 24 08:49:09 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376434896 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1376434896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/17.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/170.edn_alert.280596660 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 29534776 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:51:50 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280596660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 170.edn_alert.280596660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/170.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/170.edn_genbits.3045743794 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 59156862 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 08:51:50 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045743794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3045743794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/170.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/171.edn_alert.433639687 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 73834455 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 08:51:50 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433639687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 171.edn_alert.433639687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/171.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/171.edn_genbits.2897546058 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 268222123 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:51:50 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897546058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2897546058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/171.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/172.edn_alert.2502557731 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 60049341 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502557731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 172.edn_alert.2502557731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/172.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/172.edn_genbits.1071130719 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 37632372 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:51:50 AM UTC 24 |
| Finished | Sep 24 08:51:52 AM UTC 24 |
| Peak memory | 229256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071130719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1071130719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/172.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/173.edn_alert.3712121213 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 129467479 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712121213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 173.edn_alert.3712121213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/173.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/173.edn_genbits.1477282082 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 53586128 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:54 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477282082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1477282082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/173.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/174.edn_alert.3271947729 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 26627780 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271947729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 174.edn_alert.3271947729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/174.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/174.edn_genbits.3948284066 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 55766781 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:54 AM UTC 24 |
| Peak memory | 229500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948284066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3948284066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/174.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/175.edn_alert.2250808699 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 28930617 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250808699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 175.edn_alert.2250808699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/175.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/175.edn_genbits.2041327187 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 79721583 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:51:51 AM UTC 24 |
| Finished | Sep 24 08:51:53 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041327187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2041327187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/175.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/176.edn_alert.3464252776 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 64928045 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:54 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464252776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 176.edn_alert.3464252776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/176.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/176.edn_genbits.2972372686 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 46751416 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:55 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972372686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2972372686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/176.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/177.edn_alert.2274392471 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 50055829 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:55 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274392471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 177.edn_alert.2274392471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/177.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/177.edn_genbits.644090565 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 251248270 ps |
| CPU time | 3.6 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644090565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 177.edn_genbits.644090565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/177.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/178.edn_alert.1068409149 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 29267736 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:55 AM UTC 24 |
| Peak memory | 226864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068409149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 178.edn_alert.1068409149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/178.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/178.edn_genbits.2975011025 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 49358909 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:55 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975011025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2975011025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/178.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/179.edn_alert.1432732021 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 51406335 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:55 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432732021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 179.edn_alert.1432732021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/179.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/179.edn_genbits.3515741884 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 129290546 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:55 AM UTC 24 |
| Peak memory | 226748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515741884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3515741884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/179.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_alert.3779481226 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 38902012 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:49:25 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779481226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_alert.3779481226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_alert_test.140176699 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 14175863 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:31 AM UTC 24 |
| Peak memory | 227268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140176699 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.140176699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_disable.1046231538 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 48891071 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:31 AM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046231538 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1046231538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_err.1252096598 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 20938906 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 08:49:26 AM UTC 24 |
| Finished | Sep 24 08:49:28 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252096598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 18.edn_err.1252096598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_genbits.4035701764 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 40106728 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:11 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035701764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4035701764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_intr.39743536 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 24805510 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:49:22 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39743536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 18.edn_intr.39743536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_smoke.1003800752 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 26031344 ps |
| CPU time | 0.96 seconds |
| Started | Sep 24 08:49:11 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003800752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_smoke.1003800752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_stress_all.1134566972 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 119195184 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:49:12 AM UTC 24 |
| Finished | Sep 24 08:49:27 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134566972 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1134566972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.3629780320 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 33893349224 ps |
| CPU time | 156.12 seconds |
| Started | Sep 24 08:49:15 AM UTC 24 |
| Finished | Sep 24 08:52:04 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629780320 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all _with_rand_reset.3629780320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/180.edn_alert.2843509144 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 88143147 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:51:53 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843509144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 180.edn_alert.2843509144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/180.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/180.edn_genbits.2083490874 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 213615899 ps |
| CPU time | 2.91 seconds |
| Started | Sep 24 08:51:52 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083490874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2083490874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/180.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/181.edn_alert.2693635777 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 48970570 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693635777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 181.edn_alert.2693635777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/181.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/181.edn_genbits.2502604981 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 77683599 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502604981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2502604981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/181.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/182.edn_alert.4035130374 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 96016278 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035130374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 182.edn_alert.4035130374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/182.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/182.edn_genbits.3950378897 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 83433593 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950378897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3950378897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/182.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/183.edn_alert.1999205241 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 28507939 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999205241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 183.edn_alert.1999205241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/183.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/183.edn_genbits.1647769754 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 65725771 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647769754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1647769754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/183.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/184.edn_alert.577340159 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 27160375 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577340159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 184.edn_alert.577340159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/184.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/184.edn_genbits.3347316577 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 101613523 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347316577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3347316577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/184.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/185.edn_alert.2781899139 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 96076719 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781899139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 185.edn_alert.2781899139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/185.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/186.edn_alert.608458228 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 32764612 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608458228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 186.edn_alert.608458228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/186.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/186.edn_genbits.211827916 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 222065026 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211827916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 186.edn_genbits.211827916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/186.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/187.edn_alert.3193829502 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 57561002 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193829502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 187.edn_alert.3193829502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/187.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/187.edn_genbits.971282796 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 149136526 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:51:54 AM UTC 24 |
| Finished | Sep 24 08:51:56 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971282796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 187.edn_genbits.971282796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/187.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/188.edn_alert.2773640029 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 269914828 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:57 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773640029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 188.edn_alert.2773640029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/188.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/188.edn_genbits.2014904583 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 47049909 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014904583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2014904583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/188.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/189.edn_alert.805449188 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 89056541 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805449188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 189.edn_alert.805449188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/189.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/189.edn_genbits.1859474544 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 68374540 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859474544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1859474544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/189.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_alert.3114512511 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 29945902 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114512511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_alert.3114512511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_alert_test.1740126471 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 34101836 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 216612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740126471 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1740126471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_disable.3464804788 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 20096478 ps |
| CPU time | 0.87 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464804788 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3464804788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.3939356511 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 38119645 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939356511 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.3939356511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_err.2530793383 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 26508297 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:37 AM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530793383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 19.edn_err.2530793383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_genbits.93213567 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 45283761 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93213567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 19.edn_genbits.93213567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_intr.3535488943 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 24390081 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535488943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3535488943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_smoke.4276633406 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 31756445 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:31 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276633406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_smoke.4276633406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_stress_all.4176916841 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 91958200 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:49:32 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176916841 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4176916841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.370304708 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 7491507630 ps |
| CPU time | 54.23 seconds |
| Started | Sep 24 08:49:28 AM UTC 24 |
| Finished | Sep 24 08:50:25 AM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370304708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_ with_rand_reset.370304708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/190.edn_alert.3532750758 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 74490262 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532750758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 190.edn_alert.3532750758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/190.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/190.edn_genbits.3345263473 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 53347711 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345263473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3345263473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/190.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/191.edn_alert.2447763406 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 98108074 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447763406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 191.edn_alert.2447763406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/191.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/191.edn_genbits.2150587807 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 60255443 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150587807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2150587807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/191.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/192.edn_alert.2409053453 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 35855368 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:51:57 AM UTC 24 |
| Finished | Sep 24 08:51:59 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409053453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 192.edn_alert.2409053453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/192.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/192.edn_genbits.1973770730 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 40836544 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:55 AM UTC 24 |
| Finished | Sep 24 08:51:58 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973770730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1973770730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/192.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/193.edn_alert.2150039870 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 48369935 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:57 AM UTC 24 |
| Finished | Sep 24 08:52:00 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150039870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 193.edn_alert.2150039870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/193.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/193.edn_genbits.4049546095 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 88105483 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 08:51:57 AM UTC 24 |
| Finished | Sep 24 08:52:00 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049546095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.4049546095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/193.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/194.edn_alert.662429346 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 23551884 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:57 AM UTC 24 |
| Finished | Sep 24 08:51:59 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662429346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 194.edn_alert.662429346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/194.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/194.edn_genbits.1052621234 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 55204330 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:51:57 AM UTC 24 |
| Finished | Sep 24 08:51:59 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052621234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1052621234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/194.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/195.edn_alert.782825772 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 94715166 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:06 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782825772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 195.edn_alert.782825772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/195.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/195.edn_genbits.3844649426 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 28675834 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:51:57 AM UTC 24 |
| Finished | Sep 24 08:51:59 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844649426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3844649426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/195.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/196.edn_alert.3630296522 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 44102719 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:06 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630296522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 196.edn_alert.3630296522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/196.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/196.edn_genbits.3342494525 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 56709303 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:07 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342494525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3342494525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/196.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/197.edn_alert.2954426587 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 43749810 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:07 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954426587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 197.edn_alert.2954426587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/197.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/197.edn_genbits.1714527244 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 130169057 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:07 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714527244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1714527244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/197.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/198.edn_alert.538005071 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 39615378 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 228976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538005071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 198.edn_alert.538005071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/198.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/198.edn_genbits.2676286456 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 51762587 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676286456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2676286456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/198.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/199.edn_alert.3671058175 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 36925717 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:01 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671058175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 199.edn_alert.3671058175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/199.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/199.edn_genbits.2061257991 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 60255896 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:07 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061257991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2061257991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/199.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_alert.1629330445 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 46415685 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:20 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629330445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_alert.1629330445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_alert_test.1743309260 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27079341 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:48:11 AM UTC 24 |
| Finished | Sep 24 08:48:21 AM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743309260 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1743309260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_disable.2928146871 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11267506 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:19 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928146871 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2928146871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.4901974 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 89025623 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:20 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4901974 -assert nopostproc +UVM_TESTNAME=edn_disabl e_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.4901974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_err.4247308136 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 60070748 ps |
| CPU time | 0.84 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:19 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247308136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.edn_err.4247308136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_genbits.2911225047 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 81261949 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:19 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911225047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2911225047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_intr.3955771709 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 23973153 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:20 AM UTC 24 |
| Peak memory | 238328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955771709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3955771709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_regwen.2675144460 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 43713296 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675144460 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.edn_regwen.2675144460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_sec_cm.54237679 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2022866091 ps |
| CPU time | 8.41 seconds |
| Started | Sep 24 08:48:10 AM UTC 24 |
| Finished | Sep 24 08:48:27 AM UTC 24 |
| Peak memory | 260928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54237679 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.54237679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/2.edn_smoke.3175204424 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 49912964 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:48:09 AM UTC 24 |
| Finished | Sep 24 08:48:18 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175204424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_smoke.3175204424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/2.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_alert.3174308922 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 45351066 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174308922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_alert.3174308922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_alert_test.593267520 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 94454962 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:40 AM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593267520 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.593267520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_disable.1751197811 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 26997628 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751197811 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1751197811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_genbits.1035746449 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 57799264 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 228796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035746449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1035746449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_intr.2459853429 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 28752127 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 237180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459853429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2459853429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_smoke.2352402197 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 38454823 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352402197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_smoke.2352402197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_stress_all.2147965630 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 248761842 ps |
| CPU time | 4.94 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147965630 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2147965630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.4189875379 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 44460684527 ps |
| CPU time | 96.06 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:51:15 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189875379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all _with_rand_reset.4189875379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/200.edn_genbits.2691614300 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 23858115 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:01 AM UTC 24 |
| Peak memory | 228736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691614300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2691614300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/200.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/201.edn_genbits.3583675424 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 73289027 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583675424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3583675424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/201.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/202.edn_genbits.1342464497 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 94298025 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342464497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1342464497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/202.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/203.edn_genbits.2398072146 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 240302134 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 08:51:58 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398072146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2398072146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/203.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/204.edn_genbits.612824101 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 113465403 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:59 AM UTC 24 |
| Finished | Sep 24 08:52:03 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612824101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 204.edn_genbits.612824101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/204.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/205.edn_genbits.3041279326 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 75491713 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:51:59 AM UTC 24 |
| Finished | Sep 24 08:52:03 AM UTC 24 |
| Peak memory | 229000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041279326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3041279326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/205.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/206.edn_genbits.4113413073 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 74731088 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:51:59 AM UTC 24 |
| Finished | Sep 24 08:52:03 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113413073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4113413073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/206.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/207.edn_genbits.1129563887 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 85959222 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:51:59 AM UTC 24 |
| Finished | Sep 24 08:52:03 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129563887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1129563887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/207.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/208.edn_genbits.3913593784 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 79508925 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:51:59 AM UTC 24 |
| Finished | Sep 24 08:52:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913593784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3913593784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/208.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/209.edn_genbits.3999908697 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 74757676 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:51:59 AM UTC 24 |
| Finished | Sep 24 08:52:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999908697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3999908697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/209.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_alert_test.167386784 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 23732250 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:40 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167386784 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.167386784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_disable.4004153478 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 14707682 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:40 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004153478 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4004153478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.2248071450 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 108816808 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:40 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248071450 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.2248071450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_err.3552963941 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 41249889 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 226916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552963941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 21.edn_err.3552963941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_genbits.1012702977 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 33498112 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012702977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1012702977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_intr.931659494 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 24973723 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:40 AM UTC 24 |
| Peak memory | 237892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931659494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.931659494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_smoke.1349739169 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 42549242 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:49:30 AM UTC 24 |
| Finished | Sep 24 08:49:39 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349739169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.edn_smoke.1349739169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_stress_all.692876167 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 256327803 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692876167 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.692876167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3162127589 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 7652257220 ps |
| CPU time | 54.53 seconds |
| Started | Sep 24 08:49:31 AM UTC 24 |
| Finished | Sep 24 08:50:34 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162127589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all _with_rand_reset.3162127589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/210.edn_genbits.287942609 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 68421048 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:52:00 AM UTC 24 |
| Finished | Sep 24 08:52:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287942609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.287942609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/210.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/211.edn_genbits.1346432714 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 61507658 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:52:00 AM UTC 24 |
| Finished | Sep 24 08:52:02 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346432714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1346432714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/211.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/212.edn_genbits.144411420 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 52510467 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:52:00 AM UTC 24 |
| Finished | Sep 24 08:52:02 AM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144411420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 212.edn_genbits.144411420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/212.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/213.edn_genbits.3400711073 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 87687260 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:52:00 AM UTC 24 |
| Finished | Sep 24 08:52:02 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400711073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3400711073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/213.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/214.edn_genbits.3986394388 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 102482923 ps |
| CPU time | 2.24 seconds |
| Started | Sep 24 08:52:00 AM UTC 24 |
| Finished | Sep 24 08:52:03 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986394388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3986394388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/214.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/215.edn_genbits.3394260376 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 92710895 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:52:01 AM UTC 24 |
| Finished | Sep 24 08:52:10 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394260376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3394260376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/215.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/216.edn_genbits.2584913262 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 121371368 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:52:01 AM UTC 24 |
| Finished | Sep 24 08:52:10 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584913262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2584913262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/216.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/218.edn_genbits.3139610369 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 62090644 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:52:01 AM UTC 24 |
| Finished | Sep 24 08:52:06 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139610369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3139610369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/218.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/219.edn_genbits.494526234 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 155989907 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 08:52:02 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494526234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 219.edn_genbits.494526234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/219.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_alert_test.1151257311 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 60920516 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:49:33 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151257311 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1151257311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.581459850 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 54248322 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:49:33 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581459850 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.581459850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_err.4003871167 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 20170315 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:49:32 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 238348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003871167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 22.edn_err.4003871167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_genbits.1641044363 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 65942366 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:49:32 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641044363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1641044363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_smoke.738587048 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 23806731 ps |
| CPU time | 0.85 seconds |
| Started | Sep 24 08:49:32 AM UTC 24 |
| Finished | Sep 24 08:49:38 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738587048 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 22.edn_smoke.738587048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/22.edn_stress_all.181063433 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 363718421 ps |
| CPU time | 6.59 seconds |
| Started | Sep 24 08:49:32 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181063433 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.181063433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/22.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/220.edn_genbits.2011478414 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 79571720 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:52:02 AM UTC 24 |
| Finished | Sep 24 08:52:07 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011478414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2011478414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/220.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/221.edn_genbits.1300207526 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 64589042 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300207526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1300207526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/221.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/222.edn_genbits.2145528909 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 38732420 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145528909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2145528909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/222.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/223.edn_genbits.1158779045 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 28475560 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158779045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1158779045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/223.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/224.edn_genbits.1225001606 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 111979465 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225001606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1225001606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/224.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/225.edn_genbits.1061114915 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 375388784 ps |
| CPU time | 4.28 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061114915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1061114915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/225.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/226.edn_genbits.3402887730 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 57024085 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402887730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3402887730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/226.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/227.edn_genbits.833214210 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 59864916 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833214210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 227.edn_genbits.833214210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/227.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/228.edn_genbits.430301278 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 35547401 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:52:03 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430301278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 228.edn_genbits.430301278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/228.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/229.edn_genbits.722205690 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 51109395 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:52:04 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722205690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 229.edn_genbits.722205690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/229.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_alert.815971491 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 33150321 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815971491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 23.edn_alert.815971491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_alert_test.4024514342 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 37643584 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 216940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024514342 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4024514342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_disable.3822120268 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 15571332 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822120268 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3822120268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.742446477 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 42251747 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742446477 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.742446477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_genbits.2744396738 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 105525193 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:49:34 AM UTC 24 |
| Finished | Sep 24 08:49:37 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744396738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2744396738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_intr.2293410305 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 20932415 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293410305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2293410305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_smoke.4264949559 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 178493173 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:49:34 AM UTC 24 |
| Finished | Sep 24 08:49:37 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264949559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.edn_smoke.4264949559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/23.edn_stress_all.2502292786 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 297301095 ps |
| CPU time | 5 seconds |
| Started | Sep 24 08:49:38 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502292786 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2502292786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/23.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/230.edn_genbits.4212769412 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 98355387 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:52:04 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212769412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4212769412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/230.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/231.edn_genbits.906942867 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 137263440 ps |
| CPU time | 3.22 seconds |
| Started | Sep 24 08:52:04 AM UTC 24 |
| Finished | Sep 24 08:52:10 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906942867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 231.edn_genbits.906942867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/231.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/232.edn_genbits.920805212 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 93176718 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:52:04 AM UTC 24 |
| Finished | Sep 24 08:52:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920805212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 232.edn_genbits.920805212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/232.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/233.edn_genbits.68747738 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 88626983 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:52:06 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68747738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 233.edn_genbits.68747738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/233.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/234.edn_genbits.3368833142 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 133641548 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:52:07 AM UTC 24 |
| Finished | Sep 24 08:52:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368833142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3368833142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/234.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/235.edn_genbits.2030485040 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 89349609 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 08:52:08 AM UTC 24 |
| Finished | Sep 24 08:52:10 AM UTC 24 |
| Peak memory | 229000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030485040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2030485040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/235.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/236.edn_genbits.2843235446 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 51196679 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:52:08 AM UTC 24 |
| Finished | Sep 24 08:52:11 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843235446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2843235446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/236.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/237.edn_genbits.2859226823 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 43374421 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:52:08 AM UTC 24 |
| Finished | Sep 24 08:52:10 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859226823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2859226823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/237.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/238.edn_genbits.1065484824 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 76841933 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065484824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1065484824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/238.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/239.edn_genbits.2737046184 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 103431017 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737046184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2737046184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/239.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_alert.704024376 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 89977064 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704024376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 24.edn_alert.704024376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_alert_test.88840751 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 51430930 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88840751 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.88840751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.3448197366 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 209926605 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448197366 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3448197366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_err.217136393 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 440203775 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 243256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217136393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 24.edn_err.217136393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_genbits.2396613895 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 49584605 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396613895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2396613895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_smoke.2817298860 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 45184239 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817298860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.edn_smoke.2817298860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_stress_all.2452673580 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 35902444 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:49:39 AM UTC 24 |
| Finished | Sep 24 08:49:41 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452673580 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2452673580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.1211298214 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3239705241 ps |
| CPU time | 23.81 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:50:05 AM UTC 24 |
| Peak memory | 232412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211298214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all _with_rand_reset.1211298214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/240.edn_genbits.2653602739 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 73365962 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653602739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2653602739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/240.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/241.edn_genbits.3480290496 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 72741085 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480290496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3480290496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/241.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/242.edn_genbits.4049242597 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 73083207 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 227304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049242597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4049242597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/242.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/243.edn_genbits.3521419537 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 88017455 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 225408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521419537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3521419537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/243.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/244.edn_genbits.3498896800 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 81845521 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498896800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3498896800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/244.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/245.edn_genbits.2715903088 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 200213493 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715903088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2715903088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/245.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/246.edn_genbits.3246684781 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 31118442 ps |
| CPU time | 1.01 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246684781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3246684781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/246.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/247.edn_genbits.4239297419 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 97447256 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239297419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4239297419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/247.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/248.edn_genbits.510093655 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 56243995 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:12 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510093655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 248.edn_genbits.510093655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/248.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/249.edn_genbits.3118456642 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 170005787 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:52:09 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118456642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3118456642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/249.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_alert_test.2946897726 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 59957445 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946897726 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2946897726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_disable.3264902851 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 10955142 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264902851 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3264902851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_err.1369700019 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 32118711 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369700019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 25.edn_err.1369700019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_genbits.4111852080 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 52956885 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:45 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111852080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.4111852080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_intr.2984079613 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 25641187 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984079613 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2984079613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_smoke.3794452992 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 36220591 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:49:40 AM UTC 24 |
| Finished | Sep 24 08:49:43 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794452992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.edn_smoke.3794452992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_stress_all.2837855745 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 171486771 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837855745 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2837855745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.583471404 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 9380209769 ps |
| CPU time | 114.14 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:51:38 AM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583471404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_ with_rand_reset.583471404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/250.edn_genbits.3740165077 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 147334514 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:52:10 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740165077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3740165077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/250.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/251.edn_genbits.1382743911 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 39136630 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 08:52:10 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382743911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1382743911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/251.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/252.edn_genbits.16327738 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 28517207 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:52:10 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16327738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 252.edn_genbits.16327738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/252.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/253.edn_genbits.3170595303 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 45908874 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:52:10 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 227060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170595303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3170595303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/253.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/259.edn_genbits.3400133863 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 35772678 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:52:11 AM UTC 24 |
| Finished | Sep 24 08:52:13 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400133863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3400133863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/259.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_alert.624905851 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 97284737 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624905851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 26.edn_alert.624905851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_alert_test.967827491 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 26207220 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:49:43 AM UTC 24 |
| Finished | Sep 24 08:49:46 AM UTC 24 |
| Peak memory | 227348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967827491 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.967827491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_disable.1398653133 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 11342932 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398653133 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1398653133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.2034404962 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 32324898 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:49:43 AM UTC 24 |
| Finished | Sep 24 08:49:46 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034404962 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.2034404962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_err.1573793567 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 37660444 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 237232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573793567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 26.edn_err.1573793567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_genbits.441335491 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 69397227 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:45 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441335491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.edn_genbits.441335491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_intr.2015196415 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 49480356 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015196415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2015196415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_smoke.4212869305 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 18481542 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:44 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212869305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.edn_smoke.4212869305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_stress_all.1695772406 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 104114093 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:49:46 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695772406 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1695772406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.3966740193 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1015105177 ps |
| CPU time | 30.37 seconds |
| Started | Sep 24 08:49:42 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966740193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all _with_rand_reset.3966740193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/260.edn_genbits.3412681479 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 27086161 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:52:12 AM UTC 24 |
| Finished | Sep 24 08:52:17 AM UTC 24 |
| Peak memory | 231300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412681479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3412681479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/260.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/261.edn_genbits.2087274653 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 116345965 ps |
| CPU time | 2.48 seconds |
| Started | Sep 24 08:52:12 AM UTC 24 |
| Finished | Sep 24 08:52:16 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087274653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2087274653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/261.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/262.edn_genbits.3412498472 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 37890063 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 08:52:12 AM UTC 24 |
| Finished | Sep 24 08:52:18 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412498472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3412498472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/262.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/263.edn_genbits.1285890671 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 123414014 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:52:12 AM UTC 24 |
| Finished | Sep 24 08:52:17 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285890671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1285890671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/263.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/264.edn_genbits.1983858760 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 223692487 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:52:12 AM UTC 24 |
| Finished | Sep 24 08:52:18 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983858760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1983858760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/264.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/265.edn_genbits.1023349400 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 134047529 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:19 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023349400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1023349400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/265.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/266.edn_genbits.3853854487 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 39024676 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:19 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853854487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3853854487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/266.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/267.edn_genbits.880031062 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 259352535 ps |
| CPU time | 3.46 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:21 AM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880031062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 267.edn_genbits.880031062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/267.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/268.edn_genbits.3976915451 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 50035636 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:22 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976915451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3976915451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/268.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/269.edn_genbits.720453671 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 35702474 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:19 AM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720453671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 269.edn_genbits.720453671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/269.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_alert.437956202 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 30317845 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:49:44 AM UTC 24 |
| Finished | Sep 24 08:49:46 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437956202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 27.edn_alert.437956202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_alert_test.544479933 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 24560857 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544479933 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.544479933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_disable.1377596695 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 29403964 ps |
| CPU time | 0.89 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377596695 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1377596695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1401976168 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 94097423 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401976168 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1401976168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_err.3493652557 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24332053 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:49:44 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493652557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 27.edn_err.3493652557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_genbits.2488931702 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 100302204 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:49:43 AM UTC 24 |
| Finished | Sep 24 08:49:46 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488931702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2488931702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_intr.205836372 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 22581936 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:44 AM UTC 24 |
| Finished | Sep 24 08:49:46 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205836372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.205836372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_smoke.722900243 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 41723411 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:49:43 AM UTC 24 |
| Finished | Sep 24 08:49:45 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722900243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 27.edn_smoke.722900243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_stress_all.4284602910 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 131046702 ps |
| CPU time | 2.12 seconds |
| Started | Sep 24 08:49:44 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284602910 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4284602910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.4211356122 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1755710821 ps |
| CPU time | 38.17 seconds |
| Started | Sep 24 08:49:44 AM UTC 24 |
| Finished | Sep 24 08:50:23 AM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211356122 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all _with_rand_reset.4211356122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/270.edn_genbits.2057289560 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 53384717 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:15 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057289560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2057289560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/270.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/271.edn_genbits.4253684970 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 28413241 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:16 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253684970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4253684970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/271.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/272.edn_genbits.2671558679 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 31862764 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:19 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671558679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2671558679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/272.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/273.edn_genbits.1690865719 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 46715564 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:22 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690865719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1690865719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/273.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/274.edn_genbits.2205530728 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 30003475 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:22 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205530728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2205530728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/274.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/275.edn_genbits.1139653748 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 184829698 ps |
| CPU time | 2.53 seconds |
| Started | Sep 24 08:52:13 AM UTC 24 |
| Finished | Sep 24 08:52:24 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139653748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1139653748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/275.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/276.edn_genbits.3161673482 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 209105413 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:52:14 AM UTC 24 |
| Finished | Sep 24 08:52:17 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161673482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3161673482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/276.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/277.edn_genbits.1753110201 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 59970968 ps |
| CPU time | 1.05 seconds |
| Started | Sep 24 08:52:14 AM UTC 24 |
| Finished | Sep 24 08:52:16 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753110201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1753110201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/277.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/278.edn_genbits.4054894408 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 32392308 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:52:15 AM UTC 24 |
| Finished | Sep 24 08:52:17 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054894408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4054894408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/278.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/279.edn_genbits.1457263377 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 82675796 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:52:15 AM UTC 24 |
| Finished | Sep 24 08:52:17 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457263377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1457263377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/279.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_alert.268224537 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 27868132 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:48 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268224537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 28.edn_alert.268224537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_alert_test.263436630 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 37101231 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263436630 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.263436630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_err.2197515041 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 35251251 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197515041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 28.edn_err.2197515041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_genbits.4144538492 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 31158284 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144538492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4144538492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_intr.1181821859 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 29050068 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181821859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1181821859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_smoke.815433905 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 17141201 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815433905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 28.edn_smoke.815433905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_stress_all.211646661 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 216931237 ps |
| CPU time | 3.68 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211646661 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.211646661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.3270685547 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 6021781941 ps |
| CPU time | 78.84 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:51:06 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270685547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all _with_rand_reset.3270685547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/280.edn_genbits.1131258465 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 66948164 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:52:16 AM UTC 24 |
| Finished | Sep 24 08:52:18 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131258465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1131258465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/280.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/281.edn_genbits.4268924400 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 68702065 ps |
| CPU time | 2.5 seconds |
| Started | Sep 24 08:52:17 AM UTC 24 |
| Finished | Sep 24 08:52:24 AM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268924400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4268924400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/281.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/282.edn_genbits.3171257132 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 45531159 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:52:17 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171257132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3171257132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/282.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/283.edn_genbits.4057067652 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 132326431 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:52:17 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 230888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057067652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4057067652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/283.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/284.edn_genbits.1018060753 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 24773732 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:52:18 AM UTC 24 |
| Finished | Sep 24 08:52:27 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018060753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1018060753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/284.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/285.edn_genbits.596017928 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 27279638 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:52:18 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596017928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 285.edn_genbits.596017928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/285.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/286.edn_genbits.1775026174 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 53046160 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:52:18 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775026174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1775026174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/286.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/287.edn_genbits.2787604618 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 34344497 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:52:18 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787604618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2787604618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/287.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/288.edn_genbits.1644298690 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 39651837 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:52:18 AM UTC 24 |
| Finished | Sep 24 08:52:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644298690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1644298690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/288.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_alert.3669823368 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 32991014 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:49:46 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669823368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.edn_alert.3669823368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_alert_test.3703118295 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 33124186 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 08:49:47 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703118295 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3703118295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.3428679585 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 69729008 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:49:47 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428679585 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.3428679585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_err.2488200986 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 24449925 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:49:47 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488200986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 29.edn_err.2488200986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_genbits.2597151350 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 43057488 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597151350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2597151350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_intr.4115412987 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 34312722 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:49:46 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115412987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4115412987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_smoke.3474419773 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 25265158 ps |
| CPU time | 0.92 seconds |
| Started | Sep 24 08:49:45 AM UTC 24 |
| Finished | Sep 24 08:49:47 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474419773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.edn_smoke.3474419773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_stress_all.265472485 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 298961235 ps |
| CPU time | 6.57 seconds |
| Started | Sep 24 08:49:46 AM UTC 24 |
| Finished | Sep 24 08:49:54 AM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265472485 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.265472485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.442702063 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2571123171 ps |
| CPU time | 70.25 seconds |
| Started | Sep 24 08:49:46 AM UTC 24 |
| Finished | Sep 24 08:50:58 AM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442702063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_ with_rand_reset.442702063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/290.edn_genbits.790174746 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 50740905 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 08:52:19 AM UTC 24 |
| Finished | Sep 24 08:52:24 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790174746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 290.edn_genbits.790174746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/290.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/291.edn_genbits.3112020272 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 39245038 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:52:19 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112020272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3112020272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/291.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/292.edn_genbits.277307266 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 26222968 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:52:19 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277307266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 292.edn_genbits.277307266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/292.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/293.edn_genbits.2230149411 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 53383579 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:52:19 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 228972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230149411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2230149411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/293.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/294.edn_genbits.2769043976 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 49708822 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:52:20 AM UTC 24 |
| Finished | Sep 24 08:52:23 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769043976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2769043976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/294.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/295.edn_genbits.172120272 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 114736057 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:52:20 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172120272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 295.edn_genbits.172120272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/295.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/296.edn_genbits.770304812 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 217023731 ps |
| CPU time | 3.63 seconds |
| Started | Sep 24 08:52:20 AM UTC 24 |
| Finished | Sep 24 08:52:25 AM UTC 24 |
| Peak memory | 232116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770304812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 296.edn_genbits.770304812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/296.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/297.edn_genbits.1621776818 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 93894625 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:52:22 AM UTC 24 |
| Finished | Sep 24 08:52:32 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621776818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1621776818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/297.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/298.edn_genbits.2941942244 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 53682066 ps |
| CPU time | 1.14 seconds |
| Started | Sep 24 08:52:23 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941942244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2941942244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/298.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/299.edn_genbits.3441720158 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 75516821 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:52:23 AM UTC 24 |
| Finished | Sep 24 08:52:33 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441720158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3441720158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/299.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_alert.1789567395 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 28749001 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789567395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_alert.1789567395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_alert_test.1593427249 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 18779270 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593427249 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1593427249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_disable.1018694396 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 15958365 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018694396 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1018694396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.1989060151 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 46440717 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989060151 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.1989060151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_err.3423308728 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 22850059 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423308728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.edn_err.3423308728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_intr.4227481800 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 27378584 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:48:18 AM UTC 24 |
| Finished | Sep 24 08:48:20 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227481800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4227481800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_regwen.4267141299 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 26395811 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:48:11 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267141299 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.edn_regwen.4267141299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_sec_cm.2115502156 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2576999712 ps |
| CPU time | 10.09 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:31 AM UTC 24 |
| Peak memory | 260920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115502156 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2115502156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_smoke.160704317 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 19901520 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:48:11 AM UTC 24 |
| Finished | Sep 24 08:48:21 AM UTC 24 |
| Peak memory | 226716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160704317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.edn_smoke.160704317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_stress_all.2408648655 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 419792567 ps |
| CPU time | 4.08 seconds |
| Started | Sep 24 08:48:12 AM UTC 24 |
| Finished | Sep 24 08:48:21 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408648655 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2408648655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.1015340632 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 6791837620 ps |
| CPU time | 71.58 seconds |
| Started | Sep 24 08:48:17 AM UTC 24 |
| Finished | Sep 24 08:49:30 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015340632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_ with_rand_reset.1015340632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_alert.3529406921 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 30709371 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529406921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.edn_alert.3529406921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_alert_test.1924493131 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 13092567 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:51 AM UTC 24 |
| Peak memory | 217332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924493131 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1924493131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_disable.4143020899 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 40388225 ps |
| CPU time | 0.93 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143020899 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4143020899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1541407713 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 56456417 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:51 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541407713 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1541407713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_err.3666036379 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 25462267 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666036379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 30.edn_err.3666036379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_genbits.2110396593 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 76822602 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110396593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2110396593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_intr.31850744 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 39288843 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31850744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 30.edn_intr.31850744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_smoke.223745407 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 47876627 ps |
| CPU time | 1.03 seconds |
| Started | Sep 24 08:49:47 AM UTC 24 |
| Finished | Sep 24 08:49:49 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223745407 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 30.edn_smoke.223745407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_stress_all.2191059009 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 465647465 ps |
| CPU time | 2.83 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191059009 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2191059009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.3866167269 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 15213166808 ps |
| CPU time | 77.28 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 230548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866167269 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all _with_rand_reset.3866167269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_alert.3667951604 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 26207223 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:49:49 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667951604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_alert.3667951604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_alert_test.586305024 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 35819369 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:49:50 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 227300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586305024 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.586305024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_disable.183767210 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 38605307 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:49 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183767210 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.183767210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.3724537370 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 110050856 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:49:50 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724537370 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.3724537370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_err.1359438924 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 56780937 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:49:49 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359438924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 31.edn_err.1359438924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_genbits.3967246624 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 77212524 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967246624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3967246624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_intr.3309075317 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 29469195 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:49:49 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309075317 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3309075317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_smoke.3183276012 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 22729618 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:49:48 AM UTC 24 |
| Finished | Sep 24 08:49:50 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183276012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_smoke.3183276012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/31.edn_stress_all.2394747775 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 187133451 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:49:49 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394747775 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2394747775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/31.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_alert.2977179971 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 366106614 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 08:49:51 AM UTC 24 |
| Finished | Sep 24 08:49:54 AM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977179971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_alert.2977179971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_alert_test.4099641588 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 48461575 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:49:52 AM UTC 24 |
| Finished | Sep 24 08:49:54 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099641588 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4099641588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_disable.610495576 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 10285037 ps |
| CPU time | 0.98 seconds |
| Started | Sep 24 08:49:51 AM UTC 24 |
| Finished | Sep 24 08:49:53 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610495576 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.610495576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.61136327 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 63105064 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:49:51 AM UTC 24 |
| Finished | Sep 24 08:49:53 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61136327 -assert nopostproc +UVM_TESTNAME=edn_disab le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.61136327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_err.2778559187 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 34677769 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:51 AM UTC 24 |
| Finished | Sep 24 08:49:53 AM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778559187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 32.edn_err.2778559187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_genbits.3663194320 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 85262999 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:49:50 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663194320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3663194320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_intr.3002467906 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 29224050 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:51 AM UTC 24 |
| Finished | Sep 24 08:49:53 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002467906 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3002467906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_smoke.3256625841 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 17709956 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:49:50 AM UTC 24 |
| Finished | Sep 24 08:49:52 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256625841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_smoke.3256625841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/32.edn_stress_all.3879566687 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 490061686 ps |
| CPU time | 6.15 seconds |
| Started | Sep 24 08:49:51 AM UTC 24 |
| Finished | Sep 24 08:49:58 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879566687 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3879566687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/32.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_alert_test.2708807769 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 10069222 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708807769 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2708807769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_disable.1053534270 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 48763032 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:55 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053534270 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1053534270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.4051008993 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 49388117 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051008993 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.4051008993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_err.3655047219 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 19192405 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655047219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 33.edn_err.3655047219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_genbits.3994752919 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 44159592 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:49:52 AM UTC 24 |
| Finished | Sep 24 08:49:54 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994752919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3994752919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_intr.1085342109 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 57941891 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085342109 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1085342109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_smoke.2547610479 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 31947510 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:49:52 AM UTC 24 |
| Finished | Sep 24 08:49:54 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547610479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_smoke.2547610479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/33.edn_stress_all.384591826 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 139419734 ps |
| CPU time | 2.28 seconds |
| Started | Sep 24 08:49:52 AM UTC 24 |
| Finished | Sep 24 08:49:55 AM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384591826 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.384591826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/33.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_alert.3553985638 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 21539642 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:49:55 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553985638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_alert.3553985638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_alert_test.2250698652 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 17903385 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:49:55 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250698652 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2250698652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_disable.613292008 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 13162760 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:49:55 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613292008 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.613292008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.2239467163 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 41793185 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:49:55 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239467163 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.2239467163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_err.2068619197 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 22616543 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:49:55 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068619197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 34.edn_err.2068619197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_genbits.2077687876 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 25941125 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:49:54 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077687876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2077687876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_intr.2534217067 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 21590293 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:49:54 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534217067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2534217067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_smoke.2833162749 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 62003636 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:49:53 AM UTC 24 |
| Finished | Sep 24 08:49:56 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833162749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_smoke.2833162749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_stress_all.3852301362 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 215418536 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:49:54 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852301362 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3852301362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.4036321673 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 13995586723 ps |
| CPU time | 32.97 seconds |
| Started | Sep 24 08:49:54 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 232348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036321673 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all _with_rand_reset.4036321673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_alert.1690119471 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 73174863 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:49:56 AM UTC 24 |
| Finished | Sep 24 08:49:59 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690119471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.edn_alert.1690119471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_alert_test.4122074291 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 18112238 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:49:57 AM UTC 24 |
| Finished | Sep 24 08:50:00 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122074291 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4122074291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_disable.1859227722 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 23364093 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:49:57 AM UTC 24 |
| Finished | Sep 24 08:50:00 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859227722 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1859227722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.3116170391 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 40071492 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 08:49:57 AM UTC 24 |
| Finished | Sep 24 08:50:00 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116170391 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.3116170391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_err.3864242264 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 18777408 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:49:57 AM UTC 24 |
| Finished | Sep 24 08:50:00 AM UTC 24 |
| Peak memory | 238224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864242264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 35.edn_err.3864242264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_genbits.1205510132 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 120918887 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:49:56 AM UTC 24 |
| Finished | Sep 24 08:49:59 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205510132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1205510132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_intr.2544357535 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 21071489 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:49:56 AM UTC 24 |
| Finished | Sep 24 08:49:58 AM UTC 24 |
| Peak memory | 237180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544357535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2544357535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_smoke.3254749377 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 22624181 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:49:55 AM UTC 24 |
| Finished | Sep 24 08:49:57 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254749377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.edn_smoke.3254749377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/35.edn_stress_all.880117477 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 517973189 ps |
| CPU time | 6.28 seconds |
| Started | Sep 24 08:49:56 AM UTC 24 |
| Finished | Sep 24 08:50:03 AM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880117477 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.880117477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/35.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_alert.2180629586 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 24954942 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:49:59 AM UTC 24 |
| Finished | Sep 24 08:50:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180629586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.edn_alert.2180629586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_alert_test.234387070 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 23320698 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:49:59 AM UTC 24 |
| Finished | Sep 24 08:50:01 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234387070 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.234387070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_disable.4011383958 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 13348612 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:49:59 AM UTC 24 |
| Finished | Sep 24 08:50:01 AM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011383958 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4011383958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_err.209481863 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 22395381 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:49:59 AM UTC 24 |
| Finished | Sep 24 08:50:01 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209481863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 36.edn_err.209481863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_intr.4287069280 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 22704335 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:49:59 AM UTC 24 |
| Finished | Sep 24 08:50:01 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287069280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4287069280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_smoke.3593336633 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 28291808 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:49:58 AM UTC 24 |
| Finished | Sep 24 08:50:00 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593336633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.edn_smoke.3593336633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/36.edn_stress_all.3644429412 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 62102771 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:49:58 AM UTC 24 |
| Finished | Sep 24 08:50:00 AM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644429412 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3644429412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_alert.2298501713 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 89097341 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:50:01 AM UTC 24 |
| Finished | Sep 24 08:50:04 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298501713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.edn_alert.2298501713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_alert_test.3727329354 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 36091511 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:50:02 AM UTC 24 |
| Finished | Sep 24 08:50:04 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727329354 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3727329354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_disable.3662009571 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 28704121 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:50:01 AM UTC 24 |
| Finished | Sep 24 08:50:04 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662009571 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3662009571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.1219503018 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 65358639 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:50:02 AM UTC 24 |
| Finished | Sep 24 08:50:04 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219503018 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.1219503018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_err.1901271087 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 25588683 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:50:01 AM UTC 24 |
| Finished | Sep 24 08:50:04 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901271087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 37.edn_err.1901271087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_genbits.3280504814 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 28348448 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:50:00 AM UTC 24 |
| Finished | Sep 24 08:50:03 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280504814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3280504814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_smoke.2521936196 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 30251997 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:49:59 AM UTC 24 |
| Finished | Sep 24 08:50:01 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521936196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.edn_smoke.2521936196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_stress_all.2353072383 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3245356011 ps |
| CPU time | 6.31 seconds |
| Started | Sep 24 08:50:00 AM UTC 24 |
| Finished | Sep 24 08:50:08 AM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353072383 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2353072383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.1513270252 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4904063533 ps |
| CPU time | 69.88 seconds |
| Started | Sep 24 08:50:00 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 230292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513270252 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all _with_rand_reset.1513270252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_alert.3558363418 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 86919116 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:50:03 AM UTC 24 |
| Finished | Sep 24 08:50:06 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558363418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_alert.3558363418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_alert_test.1862237511 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 25788232 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:50:04 AM UTC 24 |
| Finished | Sep 24 08:50:06 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862237511 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1862237511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_disable.951020094 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 11489210 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:50:04 AM UTC 24 |
| Finished | Sep 24 08:50:06 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951020094 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.951020094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.249205855 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 53061653 ps |
| CPU time | 2.02 seconds |
| Started | Sep 24 08:50:04 AM UTC 24 |
| Finished | Sep 24 08:50:07 AM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249205855 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.249205855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_err.8419808 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 38165295 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:50:03 AM UTC 24 |
| Finished | Sep 24 08:50:05 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8419808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 38.edn_err.8419808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_genbits.4144665171 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 55276528 ps |
| CPU time | 2.35 seconds |
| Started | Sep 24 08:50:03 AM UTC 24 |
| Finished | Sep 24 08:50:06 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144665171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4144665171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_intr.1000413445 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 26487193 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 08:50:03 AM UTC 24 |
| Finished | Sep 24 08:50:06 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000413445 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1000413445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_smoke.3712173799 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 22819914 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:50:03 AM UTC 24 |
| Finished | Sep 24 08:50:05 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712173799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_smoke.3712173799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/38.edn_stress_all.1379977973 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 319729850 ps |
| CPU time | 7.18 seconds |
| Started | Sep 24 08:50:03 AM UTC 24 |
| Finished | Sep 24 08:50:11 AM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379977973 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1379977973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/38.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_alert.460370229 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 24038681 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 08:50:06 AM UTC 24 |
| Finished | Sep 24 08:50:08 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460370229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 39.edn_alert.460370229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_alert_test.723121359 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 13981097 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:09 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723121359 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.723121359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_disable.1212452957 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 32134644 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:09 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212452957 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1212452957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.2658422276 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 74726980 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:09 AM UTC 24 |
| Peak memory | 229072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658422276 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.2658422276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_err.1154444605 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 25928688 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:09 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154444605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 39.edn_err.1154444605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_intr.2159765023 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 27970821 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:50:05 AM UTC 24 |
| Finished | Sep 24 08:50:08 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159765023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2159765023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_smoke.4199654183 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 16519615 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:50:04 AM UTC 24 |
| Finished | Sep 24 08:50:07 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199654183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_smoke.4199654183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_stress_all.3423089976 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 317040567 ps |
| CPU time | 3.83 seconds |
| Started | Sep 24 08:50:05 AM UTC 24 |
| Finished | Sep 24 08:50:10 AM UTC 24 |
| Peak memory | 228096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423089976 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3423089976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.2930554883 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 8621220583 ps |
| CPU time | 65.58 seconds |
| Started | Sep 24 08:50:05 AM UTC 24 |
| Finished | Sep 24 08:51:13 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930554883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all _with_rand_reset.2930554883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_alert_test.101996783 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 44673053 ps |
| CPU time | 0.94 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:32 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101996783 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.101996783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_disable.1289409042 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 13804805 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:48:21 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289409042 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1289409042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.2885297280 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 35050962 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:48:21 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885297280 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.2885297280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_err.3313912573 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 27485511 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:48:20 AM UTC 24 |
| Finished | Sep 24 08:48:23 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313912573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.edn_err.3313912573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_genbits.1537875108 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 89471019 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:48:20 AM UTC 24 |
| Finished | Sep 24 08:48:23 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537875108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1537875108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_intr.291949264 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30417099 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:48:20 AM UTC 24 |
| Finished | Sep 24 08:48:23 AM UTC 24 |
| Peak memory | 238348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291949264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.291949264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_regwen.25995976 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 18751977 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25995976 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.edn_regwen.25995976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_sec_cm.386150632 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 721060192 ps |
| CPU time | 6.04 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 258680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386150632 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.386150632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_smoke.892148599 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 19937889 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:48:19 AM UTC 24 |
| Finished | Sep 24 08:48:22 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892148599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.edn_smoke.892148599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/4.edn_stress_all.1493219541 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 132161790 ps |
| CPU time | 3.34 seconds |
| Started | Sep 24 08:48:20 AM UTC 24 |
| Finished | Sep 24 08:48:25 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493219541 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1493219541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/4.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_alert.1767990906 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 40390840 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 08:50:08 AM UTC 24 |
| Finished | Sep 24 08:50:11 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767990906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.edn_alert.1767990906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_alert_test.241535788 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 40096851 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:50:09 AM UTC 24 |
| Finished | Sep 24 08:50:12 AM UTC 24 |
| Peak memory | 227120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241535788 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.241535788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.95501310 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 27615499 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 08:50:09 AM UTC 24 |
| Finished | Sep 24 08:50:12 AM UTC 24 |
| Peak memory | 226824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95501310 -assert nopostproc +UVM_TESTNAME=edn_disab le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.95501310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_err.3269882047 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 29484756 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:50:08 AM UTC 24 |
| Finished | Sep 24 08:50:11 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269882047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 40.edn_err.3269882047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_genbits.3672185200 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 60124975 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:09 AM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672185200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3672185200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_intr.3225317551 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 24791561 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:50:08 AM UTC 24 |
| Finished | Sep 24 08:50:10 AM UTC 24 |
| Peak memory | 227036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225317551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3225317551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_smoke.1723636899 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 42956356 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:09 AM UTC 24 |
| Peak memory | 226536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723636899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.edn_smoke.1723636899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_stress_all.661311351 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 145531727 ps |
| CPU time | 3.57 seconds |
| Started | Sep 24 08:50:07 AM UTC 24 |
| Finished | Sep 24 08:50:12 AM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661311351 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.661311351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.3588954230 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5071360516 ps |
| CPU time | 62.62 seconds |
| Started | Sep 24 08:50:08 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588954230 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all _with_rand_reset.3588954230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_alert.2437875667 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 91662636 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:50:11 AM UTC 24 |
| Finished | Sep 24 08:50:13 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437875667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.edn_alert.2437875667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_alert_test.3443291221 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 24751398 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:50:12 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443291221 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3443291221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_disable.2958453838 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 14594229 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:50:12 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958453838 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2958453838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.1453492549 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 49996880 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 08:50:12 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453492549 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.1453492549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_err.3499326989 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 53133126 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 08:50:11 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499326989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 41.edn_err.3499326989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_genbits.680322804 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 118735881 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:50:11 AM UTC 24 |
| Finished | Sep 24 08:50:13 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680322804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.edn_genbits.680322804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_intr.1457078296 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 29594457 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:50:11 AM UTC 24 |
| Finished | Sep 24 08:50:13 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457078296 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1457078296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_smoke.2654093221 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 43521060 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:50:10 AM UTC 24 |
| Finished | Sep 24 08:50:13 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654093221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.edn_smoke.2654093221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/41.edn_stress_all.4214724981 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 449496469 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 08:50:11 AM UTC 24 |
| Finished | Sep 24 08:50:15 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214724981 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4214724981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/41.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_alert.2824587160 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 27190557 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:50:13 AM UTC 24 |
| Finished | Sep 24 08:50:16 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824587160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_alert.2824587160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_alert_test.2186504423 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 48687144 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:50:14 AM UTC 24 |
| Finished | Sep 24 08:50:17 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186504423 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2186504423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_disable.3668557653 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 63303730 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:50:14 AM UTC 24 |
| Finished | Sep 24 08:50:17 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668557653 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3668557653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.2364377572 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 58662850 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 08:50:14 AM UTC 24 |
| Finished | Sep 24 08:50:17 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364377572 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2364377572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_err.34465849 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 34846131 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 08:50:14 AM UTC 24 |
| Finished | Sep 24 08:50:16 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34465849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 42.edn_err.34465849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_genbits.3075803860 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 20012525 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:50:12 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075803860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3075803860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_intr.635208554 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 22070676 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:50:13 AM UTC 24 |
| Finished | Sep 24 08:50:16 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635208554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.635208554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_smoke.1481843752 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 38359300 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:50:12 AM UTC 24 |
| Finished | Sep 24 08:50:14 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481843752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_smoke.1481843752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_stress_all.2087747803 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 172466308 ps |
| CPU time | 5.17 seconds |
| Started | Sep 24 08:50:13 AM UTC 24 |
| Finished | Sep 24 08:50:19 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087747803 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2087747803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.4095812860 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2853964289 ps |
| CPU time | 36.2 seconds |
| Started | Sep 24 08:50:13 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095812860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all _with_rand_reset.4095812860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_alert.28798756 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 87876352 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:50:16 AM UTC 24 |
| Finished | Sep 24 08:50:19 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28798756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.28798756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_alert_test.2587203713 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 78402344 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 08:50:17 AM UTC 24 |
| Finished | Sep 24 08:50:20 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587203713 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2587203713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_disable.3894288427 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 13932413 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:50:16 AM UTC 24 |
| Finished | Sep 24 08:50:18 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894288427 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3894288427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.126162588 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 44548798 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:50:17 AM UTC 24 |
| Finished | Sep 24 08:50:20 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126162588 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.126162588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_err.2992947580 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 63751290 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:50:16 AM UTC 24 |
| Finished | Sep 24 08:50:19 AM UTC 24 |
| Peak memory | 242780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992947580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 43.edn_err.2992947580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_genbits.3260952177 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 31165274 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 08:50:15 AM UTC 24 |
| Finished | Sep 24 08:50:18 AM UTC 24 |
| Peak memory | 229136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260952177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3260952177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_intr.268357870 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 28390104 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:50:16 AM UTC 24 |
| Finished | Sep 24 08:50:18 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268357870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.268357870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_smoke.3480182185 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 46034172 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:50:15 AM UTC 24 |
| Finished | Sep 24 08:50:17 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480182185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.edn_smoke.3480182185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_stress_all.3729936063 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 111470216 ps |
| CPU time | 3.51 seconds |
| Started | Sep 24 08:50:15 AM UTC 24 |
| Finished | Sep 24 08:50:19 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729936063 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3729936063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.2791719035 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1140577531 ps |
| CPU time | 29.36 seconds |
| Started | Sep 24 08:50:16 AM UTC 24 |
| Finished | Sep 24 08:50:46 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791719035 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all _with_rand_reset.2791719035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_alert.515047398 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 399886132 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 08:50:18 AM UTC 24 |
| Finished | Sep 24 08:50:21 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515047398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 44.edn_alert.515047398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_alert_test.3516332792 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 30691935 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 08:50:20 AM UTC 24 |
| Finished | Sep 24 08:50:22 AM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516332792 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3516332792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_disable.2616580453 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 19607684 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:50:20 AM UTC 24 |
| Finished | Sep 24 08:50:22 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616580453 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2616580453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.1939348042 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 34183329 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:50:20 AM UTC 24 |
| Finished | Sep 24 08:50:22 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939348042 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.1939348042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_genbits.415953462 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 146755789 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:50:17 AM UTC 24 |
| Finished | Sep 24 08:50:20 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415953462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.edn_genbits.415953462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_intr.45143250 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 31773045 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:50:18 AM UTC 24 |
| Finished | Sep 24 08:50:21 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45143250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 44.edn_intr.45143250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_smoke.2363540945 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 52172848 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:50:17 AM UTC 24 |
| Finished | Sep 24 08:50:20 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363540945 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.edn_smoke.2363540945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/44.edn_stress_all.3791453087 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 623850156 ps |
| CPU time | 5.49 seconds |
| Started | Sep 24 08:50:18 AM UTC 24 |
| Finished | Sep 24 08:50:25 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791453087 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3791453087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/44.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_alert.2596875168 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 80783094 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:50:21 AM UTC 24 |
| Finished | Sep 24 08:50:24 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596875168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.edn_alert.2596875168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_alert_test.3872358319 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 62091209 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:50:23 AM UTC 24 |
| Finished | Sep 24 08:50:26 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872358319 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3872358319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_disable.3661557517 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 17697338 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:50:22 AM UTC 24 |
| Finished | Sep 24 08:50:25 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661557517 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3661557517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3936401189 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 31564633 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:50:22 AM UTC 24 |
| Finished | Sep 24 08:50:25 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936401189 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3936401189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_err.2349710694 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 71248082 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:50:22 AM UTC 24 |
| Finished | Sep 24 08:50:25 AM UTC 24 |
| Peak memory | 242840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349710694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 45.edn_err.2349710694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_genbits.1750855599 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 235832892 ps |
| CPU time | 2.73 seconds |
| Started | Sep 24 08:50:21 AM UTC 24 |
| Finished | Sep 24 08:50:25 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750855599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1750855599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_intr.3685220114 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 88573741 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:50:21 AM UTC 24 |
| Finished | Sep 24 08:50:23 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685220114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3685220114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_smoke.769357669 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 16839632 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:50:21 AM UTC 24 |
| Finished | Sep 24 08:50:23 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769357669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 45.edn_smoke.769357669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/45.edn_stress_all.4144695742 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2078938466 ps |
| CPU time | 5.79 seconds |
| Started | Sep 24 08:50:21 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144695742 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4144695742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/45.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_alert_test.2746780216 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 25179441 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:50:26 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746780216 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2746780216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_disable.2204713145 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 26697930 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:50:26 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204713145 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2204713145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.594991334 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 27355019 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 08:50:26 AM UTC 24 |
| Finished | Sep 24 08:50:29 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594991334 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.594991334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_err.1230979461 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 32228579 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:50:26 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 238348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230979461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 46.edn_err.1230979461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_genbits.3547043958 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 57325949 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:50:23 AM UTC 24 |
| Finished | Sep 24 08:50:26 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547043958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3547043958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_intr.2139816208 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 33367629 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:50:25 AM UTC 24 |
| Finished | Sep 24 08:50:27 AM UTC 24 |
| Peak memory | 237300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139816208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2139816208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_smoke.2149638579 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 39999466 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:50:23 AM UTC 24 |
| Finished | Sep 24 08:50:26 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149638579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_smoke.2149638579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/46.edn_stress_all.1107531953 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 419865655 ps |
| CPU time | 8.6 seconds |
| Started | Sep 24 08:50:25 AM UTC 24 |
| Finished | Sep 24 08:50:34 AM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107531953 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1107531953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/46.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_alert.3260839179 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 39794142 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:50:27 AM UTC 24 |
| Finished | Sep 24 08:50:30 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260839179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_alert.3260839179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_alert_test.767147796 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 16379067 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:50:29 AM UTC 24 |
| Finished | Sep 24 08:50:31 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767147796 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.767147796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_disable.2607599709 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 41377867 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:50:28 AM UTC 24 |
| Finished | Sep 24 08:50:31 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607599709 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2607599709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.536484204 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 50872936 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:50:28 AM UTC 24 |
| Finished | Sep 24 08:50:32 AM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536484204 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.536484204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_err.4174328165 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 56819925 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:50:28 AM UTC 24 |
| Finished | Sep 24 08:50:31 AM UTC 24 |
| Peak memory | 247064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174328165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 47.edn_err.4174328165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_genbits.3525444094 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 72531679 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:50:26 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525444094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3525444094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_intr.1198654203 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 21343447 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:50:27 AM UTC 24 |
| Finished | Sep 24 08:50:30 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198654203 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1198654203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_smoke.1074659214 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 14964807 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:50:26 AM UTC 24 |
| Finished | Sep 24 08:50:28 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074659214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_smoke.1074659214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/47.edn_stress_all.1099976066 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 220509173 ps |
| CPU time | 5.44 seconds |
| Started | Sep 24 08:50:27 AM UTC 24 |
| Finished | Sep 24 08:50:34 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099976066 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1099976066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/47.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_alert.73443420 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 49232741 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:50:30 AM UTC 24 |
| Finished | Sep 24 08:50:33 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73443420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.73443420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_alert_test.1651154671 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 17031386 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:50:32 AM UTC 24 |
| Finished | Sep 24 08:50:34 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651154671 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1651154671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_disable.1093707885 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 12110895 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:50:31 AM UTC 24 |
| Finished | Sep 24 08:50:33 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093707885 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1093707885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.3747954247 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 34158284 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 08:50:32 AM UTC 24 |
| Finished | Sep 24 08:50:35 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747954247 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.3747954247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_err.2265611775 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 28732692 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:50:31 AM UTC 24 |
| Finished | Sep 24 08:50:34 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265611775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 48.edn_err.2265611775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_genbits.1515193164 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 51237960 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:50:30 AM UTC 24 |
| Finished | Sep 24 08:50:32 AM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515193164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1515193164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_intr.80825865 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 24287583 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:50:30 AM UTC 24 |
| Finished | Sep 24 08:50:33 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80825865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 48.edn_intr.80825865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_smoke.1338360014 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 20448295 ps |
| CPU time | 1.36 seconds |
| Started | Sep 24 08:50:30 AM UTC 24 |
| Finished | Sep 24 08:50:32 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338360014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.edn_smoke.1338360014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_stress_all.3152901174 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 328632662 ps |
| CPU time | 6.81 seconds |
| Started | Sep 24 08:50:30 AM UTC 24 |
| Finished | Sep 24 08:50:38 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152901174 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3152901174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.516447472 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 738097187 ps |
| CPU time | 26.65 seconds |
| Started | Sep 24 08:50:30 AM UTC 24 |
| Finished | Sep 24 08:50:58 AM UTC 24 |
| Peak memory | 230252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516447472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_ with_rand_reset.516447472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_alert.4114344162 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 50417816 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:50:33 AM UTC 24 |
| Finished | Sep 24 08:50:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114344162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_alert.4114344162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_alert_test.828823605 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 32324151 ps |
| CPU time | 1.26 seconds |
| Started | Sep 24 08:50:36 AM UTC 24 |
| Finished | Sep 24 08:50:38 AM UTC 24 |
| Peak memory | 216192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828823605 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.828823605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_disable.3912344782 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 13937503 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:50:35 AM UTC 24 |
| Finished | Sep 24 08:50:37 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912344782 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3912344782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.4196874760 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 92261496 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:50:35 AM UTC 24 |
| Finished | Sep 24 08:50:37 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196874760 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.4196874760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_err.960073381 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 21895948 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:50:35 AM UTC 24 |
| Finished | Sep 24 08:50:37 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960073381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 49.edn_err.960073381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_genbits.3655489388 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 30969763 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 08:50:32 AM UTC 24 |
| Finished | Sep 24 08:50:35 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655489388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3655489388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_intr.1480578587 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 30030335 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:50:33 AM UTC 24 |
| Finished | Sep 24 08:50:36 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480578587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1480578587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_smoke.1784568416 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 39881130 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:50:32 AM UTC 24 |
| Finished | Sep 24 08:50:35 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784568416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_smoke.1784568416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_stress_all.219326152 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 893367761 ps |
| CPU time | 6.1 seconds |
| Started | Sep 24 08:50:33 AM UTC 24 |
| Finished | Sep 24 08:50:41 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219326152 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.219326152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.1306158958 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1709031734 ps |
| CPU time | 43 seconds |
| Started | Sep 24 08:50:33 AM UTC 24 |
| Finished | Sep 24 08:51:19 AM UTC 24 |
| Peak memory | 232348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306158958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all _with_rand_reset.1306158958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_alert_test.777106210 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 51179089 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 216476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777106210 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.777106210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_disable.2603069751 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11612622 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603069751 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2603069751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.792150500 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 22095190 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:33 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792150500 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.792150500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_err.3188599403 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 33297631 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:33 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188599403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 5.edn_err.3188599403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_genbits.3001446551 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 98635621 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:32 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001446551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3001446551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_intr.3721272328 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 37215743 ps |
| CPU time | 0.95 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:32 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721272328 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3721272328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_regwen.2736829300 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 74988825 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:32 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736829300 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 5.edn_regwen.2736829300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_smoke.1567235425 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 25308957 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:32 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567235425 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_smoke.1567235425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_stress_all.2981673296 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 65136472 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:48:33 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981673296 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2981673296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.1862717790 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2681847872 ps |
| CPU time | 38.08 seconds |
| Started | Sep 24 08:48:23 AM UTC 24 |
| Finished | Sep 24 08:49:10 AM UTC 24 |
| Peak memory | 230492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862717790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_ with_rand_reset.1862717790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/50.edn_alert.3839321072 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 49053872 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:50:36 AM UTC 24 |
| Finished | Sep 24 08:50:39 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839321072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 50.edn_alert.3839321072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/50.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/50.edn_err.3015795997 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 62534135 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:50:36 AM UTC 24 |
| Finished | Sep 24 08:50:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015795997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 50.edn_err.3015795997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/50.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/50.edn_genbits.2072972594 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 66185265 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:50:36 AM UTC 24 |
| Finished | Sep 24 08:50:39 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072972594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2072972594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/50.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/51.edn_alert.2463829984 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 35805334 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:50:36 AM UTC 24 |
| Finished | Sep 24 08:50:39 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463829984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 51.edn_alert.2463829984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/51.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/51.edn_err.3452489751 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 24340229 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:50:37 AM UTC 24 |
| Finished | Sep 24 08:50:40 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452489751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 51.edn_err.3452489751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/51.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/51.edn_genbits.2143177824 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 66808118 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 08:50:36 AM UTC 24 |
| Finished | Sep 24 08:50:39 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143177824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2143177824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/51.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/52.edn_alert.1145466723 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 29097328 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 08:50:38 AM UTC 24 |
| Finished | Sep 24 08:50:42 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145466723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 52.edn_alert.1145466723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/52.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/52.edn_err.2519175192 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 20156998 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:50:38 AM UTC 24 |
| Finished | Sep 24 08:50:41 AM UTC 24 |
| Peak memory | 238284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519175192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 52.edn_err.2519175192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/52.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/52.edn_genbits.689731336 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 76374648 ps |
| CPU time | 2.17 seconds |
| Started | Sep 24 08:50:37 AM UTC 24 |
| Finished | Sep 24 08:50:40 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689731336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 52.edn_genbits.689731336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/52.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/53.edn_alert.68770828 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 81394735 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:50:38 AM UTC 24 |
| Finished | Sep 24 08:50:42 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68770828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.68770828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/53.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/53.edn_err.1617134873 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 38470891 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 08:50:39 AM UTC 24 |
| Finished | Sep 24 08:50:43 AM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617134873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 53.edn_err.1617134873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/53.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/53.edn_genbits.3646362656 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 25804755 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:50:38 AM UTC 24 |
| Finished | Sep 24 08:50:42 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646362656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3646362656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/53.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/54.edn_alert.4042447371 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 97598995 ps |
| CPU time | 1.66 seconds |
| Started | Sep 24 08:50:40 AM UTC 24 |
| Finished | Sep 24 08:50:43 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042447371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 54.edn_alert.4042447371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/54.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/54.edn_err.2323341899 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 49455622 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:50:40 AM UTC 24 |
| Finished | Sep 24 08:50:43 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323341899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 54.edn_err.2323341899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/54.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/54.edn_genbits.882261775 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 42099317 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 08:50:40 AM UTC 24 |
| Finished | Sep 24 08:50:44 AM UTC 24 |
| Peak memory | 230240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882261775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 54.edn_genbits.882261775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/54.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/55.edn_alert.3058936507 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 285546077 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:50:40 AM UTC 24 |
| Finished | Sep 24 08:50:43 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058936507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 55.edn_alert.3058936507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/55.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/55.edn_err.2252203824 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 18853736 ps |
| CPU time | 1.73 seconds |
| Started | Sep 24 08:50:41 AM UTC 24 |
| Finished | Sep 24 08:50:44 AM UTC 24 |
| Peak memory | 237544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252203824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 55.edn_err.2252203824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/55.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/55.edn_genbits.230058417 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 87111600 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:50:40 AM UTC 24 |
| Finished | Sep 24 08:50:43 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230058417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 55.edn_genbits.230058417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/55.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/56.edn_alert.132477495 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 40941463 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:50:42 AM UTC 24 |
| Finished | Sep 24 08:50:45 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132477495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 56.edn_alert.132477495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/56.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/56.edn_err.2545575954 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 34482537 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:50:42 AM UTC 24 |
| Finished | Sep 24 08:50:45 AM UTC 24 |
| Peak memory | 238036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545575954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 56.edn_err.2545575954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/56.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/56.edn_genbits.2589326718 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 121057116 ps |
| CPU time | 2.15 seconds |
| Started | Sep 24 08:50:41 AM UTC 24 |
| Finished | Sep 24 08:50:45 AM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589326718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2589326718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/56.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/57.edn_alert.1129233570 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 366018021 ps |
| CPU time | 2.58 seconds |
| Started | Sep 24 08:50:43 AM UTC 24 |
| Finished | Sep 24 08:50:47 AM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129233570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 57.edn_alert.1129233570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/57.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/57.edn_err.3393033593 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 93357205 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 08:50:43 AM UTC 24 |
| Finished | Sep 24 08:50:46 AM UTC 24 |
| Peak memory | 242892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393033593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 57.edn_err.3393033593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/57.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/57.edn_genbits.414912878 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 35487583 ps |
| CPU time | 1.98 seconds |
| Started | Sep 24 08:50:42 AM UTC 24 |
| Finished | Sep 24 08:50:45 AM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414912878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 57.edn_genbits.414912878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/57.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/58.edn_alert.4239625616 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 53332668 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:50:44 AM UTC 24 |
| Finished | Sep 24 08:50:47 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239625616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 58.edn_alert.4239625616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/58.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/58.edn_err.3395412397 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 28039873 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:50:44 AM UTC 24 |
| Finished | Sep 24 08:50:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395412397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 58.edn_err.3395412397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/58.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/58.edn_genbits.3441705870 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 51665074 ps |
| CPU time | 2.29 seconds |
| Started | Sep 24 08:50:43 AM UTC 24 |
| Finished | Sep 24 08:50:47 AM UTC 24 |
| Peak memory | 230284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441705870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3441705870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/58.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/59.edn_alert.72436674 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 42204697 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:50:44 AM UTC 24 |
| Finished | Sep 24 08:50:47 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72436674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.72436674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/59.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/59.edn_err.3852250251 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 24093880 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:50:45 AM UTC 24 |
| Finished | Sep 24 08:50:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852250251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 59.edn_err.3852250251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/59.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_alert.3330684343 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 40786804 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:48:28 AM UTC 24 |
| Finished | Sep 24 08:48:33 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330684343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_alert.3330684343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_alert_test.4004381087 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 35993509 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:48:33 AM UTC 24 |
| Finished | Sep 24 08:48:36 AM UTC 24 |
| Peak memory | 217424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004381087 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4004381087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.954225053 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 244398932 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:48:33 AM UTC 24 |
| Finished | Sep 24 08:48:35 AM UTC 24 |
| Peak memory | 226728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954225053 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.954225053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_err.3438527106 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 36438247 ps |
| CPU time | 0.76 seconds |
| Started | Sep 24 08:48:29 AM UTC 24 |
| Finished | Sep 24 08:48:32 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438527106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 6.edn_err.3438527106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_genbits.2333953041 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 51809090 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 229080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333953041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2333953041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_regwen.525248804 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 30394440 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 216492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525248804 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_regwen.525248804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_smoke.3130566136 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 38003044 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:34 AM UTC 24 |
| Peak memory | 226756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130566136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_smoke.3130566136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_stress_all.2152064590 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 561127208 ps |
| CPU time | 3.95 seconds |
| Started | Sep 24 08:48:24 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152064590 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2152064590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.3944996051 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3636733411 ps |
| CPU time | 88.08 seconds |
| Started | Sep 24 08:48:25 AM UTC 24 |
| Finished | Sep 24 08:50:03 AM UTC 24 |
| Peak memory | 230240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944996051 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_ with_rand_reset.3944996051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/60.edn_alert.4129554030 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 27088420 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 08:50:46 AM UTC 24 |
| Finished | Sep 24 08:50:49 AM UTC 24 |
| Peak memory | 230924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129554030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 60.edn_alert.4129554030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/60.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/60.edn_err.1231246961 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 21179689 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 08:50:46 AM UTC 24 |
| Finished | Sep 24 08:50:48 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231246961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 60.edn_err.1231246961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/60.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/60.edn_genbits.1715706784 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 269615565 ps |
| CPU time | 4.87 seconds |
| Started | Sep 24 08:50:46 AM UTC 24 |
| Finished | Sep 24 08:50:52 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715706784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1715706784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/60.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/61.edn_alert.1411740692 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 87132226 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:50:46 AM UTC 24 |
| Finished | Sep 24 08:50:49 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411740692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 61.edn_alert.1411740692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/61.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/61.edn_err.4154935641 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 35726398 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:50:47 AM UTC 24 |
| Finished | Sep 24 08:50:49 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154935641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 61.edn_err.4154935641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/61.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/61.edn_genbits.889250059 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1280516272 ps |
| CPU time | 9.6 seconds |
| Started | Sep 24 08:50:46 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889250059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 61.edn_genbits.889250059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/61.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/62.edn_alert.4219013607 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 136538916 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 08:50:48 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219013607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 62.edn_alert.4219013607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/62.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/62.edn_err.1039061444 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 45350899 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:50:48 AM UTC 24 |
| Finished | Sep 24 08:50:50 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039061444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 62.edn_err.1039061444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/62.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/62.edn_genbits.888576902 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 197459084 ps |
| CPU time | 3.46 seconds |
| Started | Sep 24 08:50:47 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888576902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 62.edn_genbits.888576902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/62.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/63.edn_alert.2514569545 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 85552245 ps |
| CPU time | 1.55 seconds |
| Started | Sep 24 08:50:48 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514569545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 63.edn_alert.2514569545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/63.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/63.edn_err.3051380284 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 24067092 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:50:48 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051380284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 63.edn_err.3051380284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/63.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/63.edn_genbits.3536471360 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 127458440 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 08:50:48 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536471360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3536471360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/63.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/64.edn_alert.793122836 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 24369877 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:50:49 AM UTC 24 |
| Finished | Sep 24 08:50:53 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793122836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 64.edn_alert.793122836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/64.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/64.edn_err.2426039321 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 28401532 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:50:49 AM UTC 24 |
| Finished | Sep 24 08:50:52 AM UTC 24 |
| Peak memory | 231028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426039321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 64.edn_err.2426039321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/64.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/64.edn_genbits.4125606453 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 222147917 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:50:48 AM UTC 24 |
| Finished | Sep 24 08:50:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125606453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4125606453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/64.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/65.edn_alert.1923157827 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 41191463 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:50:50 AM UTC 24 |
| Finished | Sep 24 08:50:52 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923157827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 65.edn_alert.1923157827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/65.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/65.edn_err.1451701852 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 32023553 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:50:50 AM UTC 24 |
| Finished | Sep 24 08:50:52 AM UTC 24 |
| Peak memory | 246680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451701852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 65.edn_err.1451701852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/65.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/65.edn_genbits.1487238657 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 139812379 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:50:50 AM UTC 24 |
| Finished | Sep 24 08:50:52 AM UTC 24 |
| Peak memory | 229000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487238657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1487238657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/65.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/66.edn_alert.489412162 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 73968207 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:55 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489412162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 66.edn_alert.489412162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/66.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/66.edn_err.3390419381 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 28936481 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:54 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390419381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 66.edn_err.3390419381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/66.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/66.edn_genbits.631443459 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 35902620 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:50:51 AM UTC 24 |
| Finished | Sep 24 08:50:53 AM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631443459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 66.edn_genbits.631443459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/66.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/67.edn_alert.1879724142 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 41963431 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:55 AM UTC 24 |
| Peak memory | 231032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879724142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 67.edn_alert.1879724142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/67.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/67.edn_err.908622740 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 31515409 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:54 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908622740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 67.edn_err.908622740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/67.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/67.edn_genbits.2211922964 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 87233249 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211922964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2211922964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/67.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/68.edn_alert.1145290150 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 23182868 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:55 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145290150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 68.edn_alert.1145290150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/68.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/68.edn_err.1941898753 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 22030223 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:55 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941898753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 68.edn_err.1941898753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/68.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/68.edn_genbits.3414433983 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 99175980 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 08:50:52 AM UTC 24 |
| Finished | Sep 24 08:50:55 AM UTC 24 |
| Peak memory | 228968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414433983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3414433983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/68.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/69.edn_alert.4112745812 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 128445380 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:50:53 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112745812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 69.edn_alert.4112745812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/69.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/69.edn_err.2674208001 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 55566269 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:50:53 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 246920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674208001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 69.edn_err.2674208001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/69.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/69.edn_genbits.3729772053 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 147691448 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:50:53 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729772053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3729772053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/69.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_alert_test.107377991 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 45719949 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 216696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107377991 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.107377991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_disable.3352727271 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 18919033 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352727271 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3352727271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.858212724 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 87004003 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858212724 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.858212724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_err.1328114440 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 38673626 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 244752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328114440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 7.edn_err.1328114440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_genbits.2659763474 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 75588801 ps |
| CPU time | 3.35 seconds |
| Started | Sep 24 08:48:33 AM UTC 24 |
| Finished | Sep 24 08:48:38 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659763474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2659763474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_intr.1410994996 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 41724197 ps |
| CPU time | 1.68 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 229260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410994996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1410994996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_regwen.506465680 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 38244581 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:48:33 AM UTC 24 |
| Finished | Sep 24 08:48:35 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506465680 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_regwen.506465680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_smoke.1990125081 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 17243943 ps |
| CPU time | 1.2 seconds |
| Started | Sep 24 08:48:33 AM UTC 24 |
| Finished | Sep 24 08:48:35 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990125081 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_smoke.1990125081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/7.edn_stress_all.2134661097 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 282527564 ps |
| CPU time | 5.9 seconds |
| Started | Sep 24 08:48:33 AM UTC 24 |
| Finished | Sep 24 08:48:40 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134661097 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2134661097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/7.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/70.edn_alert.251962010 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 28502428 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:50:53 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251962010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 70.edn_alert.251962010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/70.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/70.edn_err.1973554608 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 32459013 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:50:53 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973554608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 70.edn_err.1973554608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/70.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/70.edn_genbits.1690794773 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 130733343 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:50:53 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690794773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1690794773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/70.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/71.edn_alert.259478683 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 43133740 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:50:55 AM UTC 24 |
| Finished | Sep 24 08:50:57 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259478683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 71.edn_alert.259478683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/71.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/71.edn_err.4190593122 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 38689016 ps |
| CPU time | 1.06 seconds |
| Started | Sep 24 08:50:55 AM UTC 24 |
| Finished | Sep 24 08:50:57 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190593122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 71.edn_err.4190593122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/71.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/71.edn_genbits.2447130305 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 59950545 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 08:50:54 AM UTC 24 |
| Finished | Sep 24 08:50:56 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447130305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2447130305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/71.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/72.edn_alert.3399454576 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 77181509 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:50:56 AM UTC 24 |
| Finished | Sep 24 08:50:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399454576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 72.edn_alert.3399454576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/72.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/72.edn_err.4237594121 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 71128644 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:50:56 AM UTC 24 |
| Finished | Sep 24 08:50:59 AM UTC 24 |
| Peak memory | 242952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237594121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 72.edn_err.4237594121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/72.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/72.edn_genbits.2953610608 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 77151677 ps |
| CPU time | 1.75 seconds |
| Started | Sep 24 08:50:56 AM UTC 24 |
| Finished | Sep 24 08:50:59 AM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953610608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2953610608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/72.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/73.edn_alert.985661795 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 80108114 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:50:56 AM UTC 24 |
| Finished | Sep 24 08:50:59 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985661795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 73.edn_alert.985661795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/73.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/73.edn_err.1546664507 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 46938406 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:50:56 AM UTC 24 |
| Finished | Sep 24 08:50:59 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546664507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 73.edn_err.1546664507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/73.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/73.edn_genbits.577157270 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 120594268 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:50:56 AM UTC 24 |
| Finished | Sep 24 08:50:59 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577157270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 73.edn_genbits.577157270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/73.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/74.edn_alert.2729381344 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 63580196 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729381344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 74.edn_alert.2729381344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/74.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/74.edn_err.4134842218 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 229641947 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 242780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134842218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 74.edn_err.4134842218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/74.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/74.edn_genbits.550490198 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 48591635 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550490198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 74.edn_genbits.550490198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/74.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/75.edn_alert.1856363664 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 38984335 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856363664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 75.edn_alert.1856363664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/75.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/75.edn_err.1781767337 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 23853900 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781767337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 75.edn_err.1781767337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/75.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/75.edn_genbits.1519636086 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 43259104 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519636086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1519636086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/75.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/76.edn_alert.1774055897 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 29010183 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774055897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 76.edn_alert.1774055897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/76.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/76.edn_err.39873525 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 55549988 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39873525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 76.edn_err.39873525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/76.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/76.edn_genbits.2254226016 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 58949750 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:50:57 AM UTC 24 |
| Finished | Sep 24 08:51:00 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254226016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2254226016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/76.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/77.edn_alert.2361345108 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 24757437 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:50:59 AM UTC 24 |
| Finished | Sep 24 08:51:01 AM UTC 24 |
| Peak memory | 229000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361345108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 77.edn_alert.2361345108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/77.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/77.edn_err.2379108007 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 28337744 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:50:59 AM UTC 24 |
| Finished | Sep 24 08:51:01 AM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379108007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 77.edn_err.2379108007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/77.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/77.edn_genbits.331198945 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 96830703 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:50:59 AM UTC 24 |
| Finished | Sep 24 08:51:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331198945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 77.edn_genbits.331198945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/77.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/78.edn_alert.3001656076 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 36588612 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001656076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 78.edn_alert.3001656076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/78.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/78.edn_err.3826650238 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 64891784 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826650238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 78.edn_err.3826650238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/78.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/78.edn_genbits.377161452 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 47926440 ps |
| CPU time | 1.72 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:03 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377161452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 78.edn_genbits.377161452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/78.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/79.edn_alert.2375809948 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 62718023 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:03 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375809948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 79.edn_alert.2375809948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/79.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/79.edn_err.3352671482 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 22224805 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:02 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352671482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 79.edn_err.3352671482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/79.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/79.edn_genbits.410021941 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 43767127 ps |
| CPU time | 1.52 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410021941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 79.edn_genbits.410021941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/79.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_alert_test.3007707512 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 17758513 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:48:37 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007707512 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3007707512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.4206888275 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 65411807 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 08:48:37 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206888275 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.4206888275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_genbits.1036933491 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 109773428 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:48:35 AM UTC 24 |
| Finished | Sep 24 08:48:47 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036933491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1036933491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_regwen.2764972424 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 74601661 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764972424 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 8.edn_regwen.2764972424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_smoke.423435688 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 72772514 ps |
| CPU time | 0.99 seconds |
| Started | Sep 24 08:48:34 AM UTC 24 |
| Finished | Sep 24 08:48:37 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423435688 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.edn_smoke.423435688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/8.edn_stress_all.3799069639 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 132065760 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 08:48:35 AM UTC 24 |
| Finished | Sep 24 08:48:38 AM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799069639 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3799069639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/80.edn_alert.3470053460 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 54223125 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470053460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 80.edn_alert.3470053460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/80.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/80.edn_err.3457340655 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 30028691 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457340655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 80.edn_err.3457340655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/80.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/80.edn_genbits.3314287458 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 66458944 ps |
| CPU time | 1.37 seconds |
| Started | Sep 24 08:51:00 AM UTC 24 |
| Finished | Sep 24 08:51:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314287458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3314287458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/80.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/81.edn_alert.3263621726 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 33544364 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:03 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263621726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 81.edn_alert.3263621726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/81.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/81.edn_err.3390563878 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 43562364 ps |
| CPU time | 1.77 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 242836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390563878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 81.edn_err.3390563878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/81.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/81.edn_genbits.2757288442 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 100406554 ps |
| CPU time | 2.98 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:05 AM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757288442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2757288442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/81.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/82.edn_alert.2459452207 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 27273186 ps |
| CPU time | 1.81 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459452207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 82.edn_alert.2459452207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/82.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/82.edn_err.2797189295 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 38590950 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797189295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 82.edn_err.2797189295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/82.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/82.edn_genbits.1442982624 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 39396775 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442982624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1442982624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/82.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/83.edn_alert.2897521106 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 103438431 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897521106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 83.edn_alert.2897521106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/83.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/83.edn_err.2028279687 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 25870518 ps |
| CPU time | 1.22 seconds |
| Started | Sep 24 08:51:03 AM UTC 24 |
| Finished | Sep 24 08:51:05 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028279687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 83.edn_err.2028279687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/83.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/83.edn_genbits.338869308 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 34055043 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:51:01 AM UTC 24 |
| Finished | Sep 24 08:51:04 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338869308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 83.edn_genbits.338869308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/83.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/84.edn_alert.1492663723 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 24626928 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 08:51:03 AM UTC 24 |
| Finished | Sep 24 08:51:05 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492663723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 84.edn_alert.1492663723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/84.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/84.edn_err.1134367913 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 24615948 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:06 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134367913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 84.edn_err.1134367913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/84.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/84.edn_genbits.1653666852 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 68518923 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:51:03 AM UTC 24 |
| Finished | Sep 24 08:51:05 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653666852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1653666852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/84.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/85.edn_alert.1337849875 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 55344742 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337849875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 85.edn_alert.1337849875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/85.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/85.edn_err.2460277166 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 56406452 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 238348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460277166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 85.edn_err.2460277166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/85.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/85.edn_genbits.62523059 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 67649885 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62523059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 85.edn_genbits.62523059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/85.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/86.edn_alert.574531319 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 41764958 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574531319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 86.edn_alert.574531319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/86.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/86.edn_err.3185896222 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 30232892 ps |
| CPU time | 1.4 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185896222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 86.edn_err.3185896222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/86.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/86.edn_genbits.648104339 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 39315679 ps |
| CPU time | 2.11 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648104339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 86.edn_genbits.648104339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/86.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/87.edn_alert.3289693189 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 26945847 ps |
| CPU time | 1.53 seconds |
| Started | Sep 24 08:51:05 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289693189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 87.edn_alert.3289693189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/87.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/87.edn_err.2639443733 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 102680221 ps |
| CPU time | 1.1 seconds |
| Started | Sep 24 08:51:05 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 238336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639443733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 87.edn_err.2639443733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/87.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/87.edn_genbits.2576661309 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 50399250 ps |
| CPU time | 1.89 seconds |
| Started | Sep 24 08:51:04 AM UTC 24 |
| Finished | Sep 24 08:51:07 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576661309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2576661309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/87.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/88.edn_alert.3726398162 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 41721162 ps |
| CPU time | 1.71 seconds |
| Started | Sep 24 08:51:05 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726398162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 88.edn_alert.3726398162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/88.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/88.edn_err.3239056910 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 34143800 ps |
| CPU time | 1.59 seconds |
| Started | Sep 24 08:51:05 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 243256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239056910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 88.edn_err.3239056910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/88.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/88.edn_genbits.1452244742 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 42046396 ps |
| CPU time | 1.9 seconds |
| Started | Sep 24 08:51:05 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452244742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1452244742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/88.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/89.edn_alert.2629702395 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 30379581 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:51:06 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629702395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 89.edn_alert.2629702395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/89.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/89.edn_err.3050364481 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 66966722 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:51:06 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050364481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 89.edn_err.3050364481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/89.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/89.edn_genbits.3385375021 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 41167819 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:51:06 AM UTC 24 |
| Finished | Sep 24 08:51:08 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385375021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3385375021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/89.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_alert.3497502764 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 51761922 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:48:38 AM UTC 24 |
| Finished | Sep 24 08:48:48 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497502764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.edn_alert.3497502764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_alert_test.918399931 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 54004819 ps |
| CPU time | 0.8 seconds |
| Started | Sep 24 08:48:38 AM UTC 24 |
| Finished | Sep 24 08:48:51 AM UTC 24 |
| Peak memory | 226592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918399931 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.918399931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.547629849 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 43180976 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:48:38 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 227096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547629849 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.547629849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_err.1082108320 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 33881659 ps |
| CPU time | 0.9 seconds |
| Started | Sep 24 08:48:38 AM UTC 24 |
| Finished | Sep 24 08:48:54 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082108320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 9.edn_err.1082108320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_genbits.428549705 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 39247339 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 08:48:37 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428549705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.edn_genbits.428549705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_intr.1759600307 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 61841290 ps |
| CPU time | 1 seconds |
| Started | Sep 24 08:48:38 AM UTC 24 |
| Finished | Sep 24 08:48:55 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759600307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1759600307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_smoke.2016884287 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 33163345 ps |
| CPU time | 1.15 seconds |
| Started | Sep 24 08:48:37 AM UTC 24 |
| Finished | Sep 24 08:48:52 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016884287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.edn_smoke.2016884287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/9.edn_stress_all.3531562874 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 222307694 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:48:37 AM UTC 24 |
| Finished | Sep 24 08:48:53 AM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531562874 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3531562874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/9.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/90.edn_alert.2431882221 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 33299912 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:51:07 AM UTC 24 |
| Finished | Sep 24 08:51:09 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431882221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 90.edn_alert.2431882221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/90.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/90.edn_err.2631737401 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 22921938 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:51:07 AM UTC 24 |
| Finished | Sep 24 08:51:09 AM UTC 24 |
| Peak memory | 244512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631737401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 90.edn_err.2631737401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/90.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/90.edn_genbits.1681771818 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 82061529 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:51:06 AM UTC 24 |
| Finished | Sep 24 08:51:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681771818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1681771818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/90.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/91.edn_alert.2552666085 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 37648541 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:51:07 AM UTC 24 |
| Finished | Sep 24 08:51:09 AM UTC 24 |
| Peak memory | 229004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552666085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 91.edn_alert.2552666085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/91.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/91.edn_err.122468209 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 53735184 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:51:07 AM UTC 24 |
| Finished | Sep 24 08:51:09 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122468209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 91.edn_err.122468209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/91.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/91.edn_genbits.3119247336 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 137107275 ps |
| CPU time | 2.19 seconds |
| Started | Sep 24 08:51:07 AM UTC 24 |
| Finished | Sep 24 08:51:10 AM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119247336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3119247336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/91.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/92.edn_alert.1604411075 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 27500444 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604411075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 92.edn_alert.1604411075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/92.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/92.edn_err.118518650 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 70326788 ps |
| CPU time | 1.58 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 238276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118518650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 92.edn_err.118518650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/92.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/92.edn_genbits.4214455329 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 25264068 ps |
| CPU time | 1.49 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214455329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.4214455329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/92.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/93.edn_alert.1917985768 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 29383683 ps |
| CPU time | 1.47 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917985768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 93.edn_alert.1917985768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/93.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/93.edn_err.4018264645 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 24564919 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 247100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018264645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 93.edn_err.4018264645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/93.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/93.edn_genbits.4093855745 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 50246632 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093855745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4093855745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/93.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/94.edn_alert.2782887749 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 34080854 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782887749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 94.edn_alert.2782887749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/94.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/94.edn_err.2274049701 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 36562447 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:10 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274049701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 94.edn_err.2274049701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/94.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/94.edn_genbits.2792751268 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 68389339 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:51:08 AM UTC 24 |
| Finished | Sep 24 08:51:11 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792751268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2792751268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/94.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/95.edn_alert.6336044 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 50823072 ps |
| CPU time | 1.65 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6336044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.6336044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/95.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/95.edn_err.2065924398 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 19008929 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065924398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 95.edn_err.2065924398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/95.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/95.edn_genbits.3678459919 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 81597790 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678459919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3678459919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/95.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/96.edn_alert.3208368235 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 46915825 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208368235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 96.edn_alert.3208368235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/96.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/96.edn_err.2789852193 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 30541054 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789852193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 96.edn_err.2789852193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/96.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/96.edn_genbits.3390837374 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 41249694 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:13 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390837374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3390837374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/96.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/97.edn_alert.3315642061 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 45534697 ps |
| CPU time | 1.24 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:12 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315642061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 97.edn_alert.3315642061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/97.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/97.edn_err.3782273944 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 36776796 ps |
| CPU time | 1.64 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:13 AM UTC 24 |
| Peak memory | 246980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782273944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 97.edn_err.3782273944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/97.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/97.edn_genbits.957132781 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 40216445 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:13 AM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957132781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 97.edn_genbits.957132781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/97.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/98.edn_alert.1427826074 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 28785128 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:13 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427826074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 98.edn_alert.1427826074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/98.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/98.edn_genbits.1595717650 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 57560089 ps |
| CPU time | 2.18 seconds |
| Started | Sep 24 08:51:10 AM UTC 24 |
| Finished | Sep 24 08:51:13 AM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595717650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1595717650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/98.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/default/99.edn_genbits.3547923009 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 46592119 ps |
| CPU time | 1.42 seconds |
| Started | Sep 24 08:51:11 AM UTC 24 |
| Finished | Sep 24 08:51:14 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547923009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3547923009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/99.edn_genbits/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |