Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	2	0	2	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr_pin

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_pins[0]

68962

1

T1

19

T2

18

T3

86

all_pins[1]

68962

1

T1

19

T2

18

T3

86

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	133499	1			T1	38		T2	36		T3	172
values[0x1]	4425	1			T4	3		T61	16		T65	31
transitions[0x0=>0x1]	4009	1			T4	3		T61	12		T65	30
transitions[0x1=>0x0]	4021	1			T4	3		T61	12		T65	30

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	65487	1			T1	19		T2	18		T3	86
all_pins[0]	values[0x1]	3475	1			T4	1		T61	10		T65	27
all_pins[0]	transitions[0x0=>0x1]	3259	1			T4	1		T61	8		T65	26
all_pins[0]	transitions[0x1=>0x0]	734	1			T4	2		T61	4		T65	3
all_pins[1]	values[0x0]	68012	1			T1	19		T2	18		T3	86
all_pins[1]	values[0x1]	950	1			T4	2		T61	6		T65	4
all_pins[1]	transitions[0x0=>0x1]	750	1			T4	2		T61	4		T65	4
all_pins[1]	transitions[0x1=>0x0]	3287	1			T4	1		T61	8		T65	27