| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.68 | 98.23 | 93.97 | 97.02 | 91.28 | 96.33 | 99.77 | 93.18 |
| T1013 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2820096243 | Oct 03 01:16:30 AM UTC 24 | Oct 03 01:16:34 AM UTC 24 | 35433769 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2015439994 | Oct 03 01:16:32 AM UTC 24 | Oct 03 01:16:35 AM UTC 24 | 112937168 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.2901373842 | Oct 03 01:16:32 AM UTC 24 | Oct 03 01:16:35 AM UTC 24 | 83037757 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1125157466 | Oct 03 01:16:31 AM UTC 24 | Oct 03 01:16:35 AM UTC 24 | 160881157 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2089902703 | Oct 03 01:16:32 AM UTC 24 | Oct 03 01:16:35 AM UTC 24 | 30499399 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2157217281 | Oct 03 01:16:34 AM UTC 24 | Oct 03 01:16:36 AM UTC 24 | 30736050 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.824284684 | Oct 03 01:16:33 AM UTC 24 | Oct 03 01:16:36 AM UTC 24 | 26193731 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2785946912 | Oct 03 01:16:34 AM UTC 24 | Oct 03 01:16:36 AM UTC 24 | 73427055 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3207213803 | Oct 03 01:16:34 AM UTC 24 | Oct 03 01:16:37 AM UTC 24 | 104466822 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.1070918409 | Oct 03 01:16:34 AM UTC 24 | Oct 03 01:16:37 AM UTC 24 | 51526546 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.1125027923 | Oct 03 01:16:34 AM UTC 24 | Oct 03 01:16:38 AM UTC 24 | 83772954 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3243128688 | Oct 03 01:16:35 AM UTC 24 | Oct 03 01:16:38 AM UTC 24 | 13244639 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3600297437 | Oct 03 01:16:36 AM UTC 24 | Oct 03 01:16:39 AM UTC 24 | 24900240 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.2956595341 | Oct 03 01:16:36 AM UTC 24 | Oct 03 01:16:39 AM UTC 24 | 36794279 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.3732625482 | Oct 03 01:16:37 AM UTC 24 | Oct 03 01:16:40 AM UTC 24 | 14337281 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1304779450 | Oct 03 01:16:35 AM UTC 24 | Oct 03 01:16:41 AM UTC 24 | 107085519 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3036899131 | Oct 03 01:16:38 AM UTC 24 | Oct 03 01:16:41 AM UTC 24 | 32335608 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.2764126620 | Oct 03 01:16:38 AM UTC 24 | Oct 03 01:16:41 AM UTC 24 | 55833617 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.1534121313 | Oct 03 01:16:35 AM UTC 24 | Oct 03 01:16:41 AM UTC 24 | 356149005 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1283993472 | Oct 03 01:16:37 AM UTC 24 | Oct 03 01:16:41 AM UTC 24 | 263395402 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1672436151 | Oct 03 01:16:40 AM UTC 24 | Oct 03 01:16:42 AM UTC 24 | 19218288 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1920091096 | Oct 03 01:16:39 AM UTC 24 | Oct 03 01:16:42 AM UTC 24 | 89330026 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.4143722234 | Oct 03 01:16:40 AM UTC 24 | Oct 03 01:16:42 AM UTC 24 | 14697560 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3261706513 | Oct 03 01:16:39 AM UTC 24 | Oct 03 01:16:43 AM UTC 24 | 69855465 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1647513852 | Oct 03 01:16:36 AM UTC 24 | Oct 03 01:16:43 AM UTC 24 | 85682776 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2813329508 | Oct 03 01:16:41 AM UTC 24 | Oct 03 01:16:44 AM UTC 24 | 26960971 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.2421189907 | Oct 03 01:16:41 AM UTC 24 | Oct 03 01:16:44 AM UTC 24 | 48921683 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.1050504357 | Oct 03 01:16:42 AM UTC 24 | Oct 03 01:16:44 AM UTC 24 | 33985288 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3170326036 | Oct 03 01:16:42 AM UTC 24 | Oct 03 01:16:44 AM UTC 24 | 16411319 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.371174735 | Oct 03 01:16:41 AM UTC 24 | Oct 03 01:16:45 AM UTC 24 | 104964966 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1529658654 | Oct 03 01:16:42 AM UTC 24 | Oct 03 01:16:45 AM UTC 24 | 70221523 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3381633005 | Oct 03 01:16:42 AM UTC 24 | Oct 03 01:16:45 AM UTC 24 | 50175414 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1773898283 | Oct 03 01:16:42 AM UTC 24 | Oct 03 01:16:45 AM UTC 24 | 190817157 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.3339857755 | Oct 03 01:16:44 AM UTC 24 | Oct 03 01:16:46 AM UTC 24 | 40355495 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2336847553 | Oct 03 01:16:44 AM UTC 24 | Oct 03 01:16:46 AM UTC 24 | 22713205 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2089363769 | Oct 03 01:16:44 AM UTC 24 | Oct 03 01:16:47 AM UTC 24 | 19974820 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.3316670569 | Oct 03 01:16:44 AM UTC 24 | Oct 03 01:16:47 AM UTC 24 | 44420156 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1957048881 | Oct 03 01:16:45 AM UTC 24 | Oct 03 01:16:48 AM UTC 24 | 18054457 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.205281119 | Oct 03 01:16:43 AM UTC 24 | Oct 03 01:16:48 AM UTC 24 | 214045774 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3818315896 | Oct 03 01:16:46 AM UTC 24 | Oct 03 01:16:48 AM UTC 24 | 28846193 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3028895474 | Oct 03 01:16:46 AM UTC 24 | Oct 03 01:16:48 AM UTC 24 | 17113505 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.63311341 | Oct 03 01:16:46 AM UTC 24 | Oct 03 01:16:49 AM UTC 24 | 53157637 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.3819798016 | Oct 03 01:16:45 AM UTC 24 | Oct 03 01:16:49 AM UTC 24 | 48104377 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1360009760 | Oct 03 01:16:46 AM UTC 24 | Oct 03 01:16:50 AM UTC 24 | 23700487 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.658079416 | Oct 03 01:16:47 AM UTC 24 | Oct 03 01:16:50 AM UTC 24 | 23407701 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.951041669 | Oct 03 01:16:48 AM UTC 24 | Oct 03 01:16:50 AM UTC 24 | 33348546 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3660390956 | Oct 03 01:16:47 AM UTC 24 | Oct 03 01:16:50 AM UTC 24 | 80753004 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3727743234 | Oct 03 01:16:45 AM UTC 24 | Oct 03 01:16:50 AM UTC 24 | 287910684 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3206499776 | Oct 03 01:16:46 AM UTC 24 | Oct 03 01:16:51 AM UTC 24 | 82981555 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1111054071 | Oct 03 01:16:49 AM UTC 24 | Oct 03 01:16:52 AM UTC 24 | 302392161 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.1455629657 | Oct 03 01:16:50 AM UTC 24 | Oct 03 01:16:52 AM UTC 24 | 17198471 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.2206870715 | Oct 03 01:16:50 AM UTC 24 | Oct 03 01:16:52 AM UTC 24 | 37749172 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.217372845 | Oct 03 01:16:47 AM UTC 24 | Oct 03 01:16:52 AM UTC 24 | 101952187 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.2756406503 | Oct 03 01:16:50 AM UTC 24 | Oct 03 01:16:52 AM UTC 24 | 58669950 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.3936262210 | Oct 03 01:16:49 AM UTC 24 | Oct 03 01:16:53 AM UTC 24 | 149317534 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1749847701 | Oct 03 01:16:50 AM UTC 24 | Oct 03 01:16:53 AM UTC 24 | 175716381 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2665352774 | Oct 03 01:16:51 AM UTC 24 | Oct 03 01:16:53 AM UTC 24 | 18680587 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1094171233 | Oct 03 01:16:51 AM UTC 24 | Oct 03 01:16:53 AM UTC 24 | 14179503 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4021558039 | Oct 03 01:16:51 AM UTC 24 | Oct 03 01:16:54 AM UTC 24 | 119280880 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1027722949 | Oct 03 01:16:51 AM UTC 24 | Oct 03 01:16:54 AM UTC 24 | 231426035 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3648207352 | Oct 03 01:16:52 AM UTC 24 | Oct 03 01:16:55 AM UTC 24 | 240040183 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.454885147 | Oct 03 01:16:52 AM UTC 24 | Oct 03 01:16:56 AM UTC 24 | 79572595 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.25974902 | Oct 03 01:16:54 AM UTC 24 | Oct 03 01:16:56 AM UTC 24 | 41281762 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3526966286 | Oct 03 01:16:54 AM UTC 24 | Oct 03 01:16:56 AM UTC 24 | 23176596 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3707542160 | Oct 03 01:16:54 AM UTC 24 | Oct 03 01:16:56 AM UTC 24 | 31210264 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3858354932 | Oct 03 01:16:51 AM UTC 24 | Oct 03 01:16:57 AM UTC 24 | 80289719 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1030930997 | Oct 03 01:16:53 AM UTC 24 | Oct 03 01:16:57 AM UTC 24 | 525773542 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.2253836490 | Oct 03 01:16:54 AM UTC 24 | Oct 03 01:16:57 AM UTC 24 | 42804248 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3535855932 | Oct 03 01:16:55 AM UTC 24 | Oct 03 01:16:57 AM UTC 24 | 10379727 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1255045809 | Oct 03 01:16:55 AM UTC 24 | Oct 03 01:16:57 AM UTC 24 | 37103927 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.1804279131 | Oct 03 01:16:56 AM UTC 24 | Oct 03 01:16:59 AM UTC 24 | 19943891 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.2881628656 | Oct 03 01:16:52 AM UTC 24 | Oct 03 01:16:59 AM UTC 24 | 112002975 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.277060168 | Oct 03 01:16:55 AM UTC 24 | Oct 03 01:16:59 AM UTC 24 | 138458555 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1321382534 | Oct 03 01:16:56 AM UTC 24 | Oct 03 01:16:59 AM UTC 24 | 55942465 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.424106122 | Oct 03 01:16:57 AM UTC 24 | Oct 03 01:17:00 AM UTC 24 | 38027616 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.2830689738 | Oct 03 01:16:58 AM UTC 24 | Oct 03 01:17:00 AM UTC 24 | 39526396 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.2239253132 | Oct 03 01:16:57 AM UTC 24 | Oct 03 01:17:00 AM UTC 24 | 15184525 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.2444845777 | Oct 03 01:16:57 AM UTC 24 | Oct 03 01:17:00 AM UTC 24 | 14648692 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3848444469 | Oct 03 01:16:58 AM UTC 24 | Oct 03 01:17:00 AM UTC 24 | 38344096 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.4157813422 | Oct 03 01:16:59 AM UTC 24 | Oct 03 01:17:01 AM UTC 24 | 26592188 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.700734180 | Oct 03 01:16:59 AM UTC 24 | Oct 03 01:17:01 AM UTC 24 | 18152044 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1933540576 | Oct 03 01:16:59 AM UTC 24 | Oct 03 01:17:01 AM UTC 24 | 15707222 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.1618482260 | Oct 03 01:16:55 AM UTC 24 | Oct 03 01:17:02 AM UTC 24 | 914167262 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1982482730 | Oct 03 01:17:00 AM UTC 24 | Oct 03 01:17:02 AM UTC 24 | 162454235 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3474894872 | Oct 03 01:17:00 AM UTC 24 | Oct 03 01:17:02 AM UTC 24 | 10381407 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1632250745 | Oct 03 01:17:00 AM UTC 24 | Oct 03 01:17:02 AM UTC 24 | 13743054 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.843550666 | Oct 03 01:17:00 AM UTC 24 | Oct 03 01:17:02 AM UTC 24 | 27464036 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.2513555903 | Oct 03 01:17:00 AM UTC 24 | Oct 03 01:17:02 AM UTC 24 | 18799767 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3157824798 | Oct 03 01:17:01 AM UTC 24 | Oct 03 01:17:03 AM UTC 24 | 42030402 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.838906967 | Oct 03 01:17:01 AM UTC 24 | Oct 03 01:17:03 AM UTC 24 | 15681538 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.390304936 | Oct 03 01:17:01 AM UTC 24 | Oct 03 01:17:03 AM UTC 24 | 22612288 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3186405449 | Oct 03 01:17:01 AM UTC 24 | Oct 03 01:17:04 AM UTC 24 | 50090354 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.2169647859 | Oct 03 01:17:02 AM UTC 24 | Oct 03 01:17:05 AM UTC 24 | 14017725 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3664530413 | Oct 03 01:17:02 AM UTC 24 | Oct 03 01:17:05 AM UTC 24 | 14592745 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3792867615 | Oct 03 01:17:03 AM UTC 24 | Oct 03 01:17:05 AM UTC 24 | 40035505 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.3425955780 | Oct 03 01:17:03 AM UTC 24 | Oct 03 01:17:05 AM UTC 24 | 22896245 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2534134513 | Oct 03 01:17:03 AM UTC 24 | Oct 03 01:17:05 AM UTC 24 | 46802576 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.984495683 | Oct 03 01:17:03 AM UTC 24 | Oct 03 01:17:05 AM UTC 24 | 74472918 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3764167290 | Oct 03 01:17:04 AM UTC 24 | Oct 03 01:17:06 AM UTC 24 | 34078422 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2334755053 | Oct 03 01:17:04 AM UTC 24 | Oct 03 01:17:06 AM UTC 24 | 43165444 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1650255535 | Oct 03 01:17:04 AM UTC 24 | Oct 03 01:17:06 AM UTC 24 | 35015300 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.611471594 | Oct 03 01:17:04 AM UTC 24 | Oct 03 01:17:06 AM UTC 24 | 122762287 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.317104147 | Oct 03 01:17:05 AM UTC 24 | Oct 03 01:17:07 AM UTC 24 | 19854468 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3537922362 | Oct 03 01:17:05 AM UTC 24 | Oct 03 01:17:07 AM UTC 24 | 10827660 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1783727611 | Oct 03 01:17:05 AM UTC 24 | Oct 03 01:17:07 AM UTC 24 | 53672675 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_alert.3309425508 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 45200085 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:36 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309425508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_alert.3309425508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_genbits.2000037972 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 94914320 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:36 AM UTC 24 |
| Peak memory | 231004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000037972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2000037972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_sec_cm.459477901 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 283260636 ps |
| CPU time | 4.81 seconds |
| Started | Oct 03 01:08:36 AM UTC 24 |
| Finished | Oct 03 01:08:42 AM UTC 24 |
| Peak memory | 260620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459477901 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.459477901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_stress_all.2828264149 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1024717277 ps |
| CPU time | 3.94 seconds |
| Started | Oct 03 01:08:34 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828264149 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2828264149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_disable.565456211 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12169011 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:45 AM UTC 24 |
| Peak memory | 227020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565456211 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.565456211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.531654498 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 16658918582 ps |
| CPU time | 45.31 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:09:20 AM UTC 24 |
| Peak memory | 230500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531654498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_w ith_rand_reset.531654498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_sec_cm.3033551794 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 325363241 ps |
| CPU time | 8.34 seconds |
| Started | Oct 03 01:08:38 AM UTC 24 |
| Finished | Oct 03 01:08:48 AM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033551794 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3033551794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_alert.74251152 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 35724039 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:08:59 AM UTC 24 |
| Finished | Oct 03 01:09:01 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74251152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.74251152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.2060692689 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 57343354 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:08:43 AM UTC 24 |
| Finished | Oct 03 01:08:46 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060692689 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.2060692689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_regwen.2637815908 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 16612086 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:08:32 AM UTC 24 |
| Finished | Oct 03 01:08:34 AM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637815908 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.edn_regwen.2637815908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_alert.2047630964 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 91484754 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:09:09 AM UTC 24 |
| Finished | Oct 03 01:09:11 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047630964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_alert.2047630964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_err.2555153385 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 18425861 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:08:52 AM UTC 24 |
| Finished | Oct 03 01:08:55 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555153385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 7.edn_err.2555153385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_alert.2562530798 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 30049703 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:10:10 AM UTC 24 |
| Finished | Oct 03 01:10:13 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562530798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.edn_alert.2562530798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.3375622785 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 13675434927 ps |
| CPU time | 58.97 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:09:38 AM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375622785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_ with_rand_reset.3375622785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1932594937 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 11614364 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:16:11 AM UTC 24 |
| Finished | Oct 03 01:16:13 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932594937 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1932594937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.784247741 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 265508049 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 01:16:27 AM UTC 24 |
| Finished | Oct 03 01:16:32 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784247741 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.784247741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_intr.2279037064 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 28394984 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:09:13 AM UTC 24 |
| Finished | Oct 03 01:09:15 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279037064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2279037064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.2503430141 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 94439460 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:08:56 AM UTC 24 |
| Finished | Oct 03 01:08:59 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503430141 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.2503430141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_disable.3681156454 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 47955982 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:09:53 AM UTC 24 |
| Finished | Oct 03 01:09:56 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681156454 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3681156454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_disable.1086878283 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 23238030 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:09:09 AM UTC 24 |
| Finished | Oct 03 01:09:11 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086878283 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1086878283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_disable.2243333655 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 31112188 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:12:09 AM UTC 24 |
| Finished | Oct 03 01:12:12 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243333655 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2243333655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_alert.2231029356 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 81068478 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 01:09:21 AM UTC 24 |
| Finished | Oct 03 01:09:24 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231029356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.edn_alert.2231029356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.3934592182 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 101404697 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:09:35 AM UTC 24 |
| Finished | Oct 03 01:09:37 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934592182 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.3934592182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_stress_all.3045666160 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 259650210 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:42 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045666160 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3045666160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_alert.520506066 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 81155596 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:12:07 AM UTC 24 |
| Finished | Oct 03 01:12:10 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520506066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 43.edn_alert.520506066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_genbits.988216466 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 108387907 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 01:12:15 AM UTC 24 |
| Finished | Oct 03 01:12:18 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988216466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.edn_genbits.988216466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_alert.795002581 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 23026328 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:44 AM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795002581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.edn_alert.795002581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_intr.471630900 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 29877592 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:09:52 AM UTC 24 |
| Finished | Oct 03 01:09:54 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471630900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.471630900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_alert.1382762986 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 27203149 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382762986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_alert.1382762986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_alert.3511181174 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 24716789 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:08:55 AM UTC 24 |
| Finished | Oct 03 01:08:58 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511181174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.edn_alert.3511181174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_genbits.2195258237 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 35848318 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 01:09:19 AM UTC 24 |
| Finished | Oct 03 01:09:22 AM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195258237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2195258237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_alert_test.1065281298 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 23507393 ps |
| CPU time | 0.94 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:35 AM UTC 24 |
| Peak memory | 216476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065281298 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1065281298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_regwen.2574571981 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 70430116 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:39 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574571981 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.edn_regwen.2574571981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_genbits.3776888 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 51858204 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:10:20 AM UTC 24 |
| Finished | Oct 03 01:10:23 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_ genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 28.edn_genbits.3776888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/77.edn_alert.3053171954 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 241936828 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 01:14:01 AM UTC 24 |
| Finished | Oct 03 01:14:04 AM UTC 24 |
| Peak memory | 232776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053171954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 77.edn_alert.3053171954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/77.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_alert.3103371836 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 32552983 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:09:02 AM UTC 24 |
| Finished | Oct 03 01:09:04 AM UTC 24 |
| Peak memory | 231076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103371836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_alert.3103371836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_disable.828952448 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 15744942 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:09:03 AM UTC 24 |
| Finished | Oct 03 01:09:05 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828952448 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.828952448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_alert.990224394 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 28059790 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:09:05 AM UTC 24 |
| Finished | Oct 03 01:09:08 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990224394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.edn_alert.990224394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/115.edn_alert.1741900254 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 27151721 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:14:44 AM UTC 24 |
| Finished | Oct 03 01:14:47 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741900254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 115.edn_alert.1741900254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/115.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.4141401309 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 195704475 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:09:09 AM UTC 24 |
| Finished | Oct 03 01:09:12 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141401309 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.4141401309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/124.edn_alert.245748810 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 97125497 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:14:49 AM UTC 24 |
| Finished | Oct 03 01:14:52 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245748810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 124.edn_alert.245748810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/124.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_disable.3870549110 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 11125847 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:09:13 AM UTC 24 |
| Finished | Oct 03 01:09:15 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870549110 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3870549110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/130.edn_alert.101119364 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 42272005 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:14:54 AM UTC 24 |
| Finished | Oct 03 01:14:57 AM UTC 24 |
| Peak memory | 231076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101119364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 130.edn_alert.101119364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/130.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/140.edn_alert.3177032816 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 97691097 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:15:01 AM UTC 24 |
| Finished | Oct 03 01:15:03 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177032816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 140.edn_alert.3177032816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/140.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.2843227863 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 46499234 ps |
| CPU time | 2.24 seconds |
| Started | Oct 03 01:09:40 AM UTC 24 |
| Finished | Oct 03 01:09:44 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843227863 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.2843227863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_disable.3585903834 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 39802003 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:09:49 AM UTC 24 |
| Finished | Oct 03 01:09:51 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585903834 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3585903834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_disable.2905409732 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 10643769 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:10:11 AM UTC 24 |
| Finished | Oct 03 01:10:13 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905409732 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2905409732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_err.3097611326 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 23569276 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:43 AM UTC 24 |
| Peak memory | 244692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097611326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.edn_err.3097611326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_disable.654882669 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 12756997 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:11:29 AM UTC 24 |
| Finished | Oct 03 01:11:31 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654882669 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.654882669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/64.edn_err.3628699445 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 33543987 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:13:45 AM UTC 24 |
| Finished | Oct 03 01:13:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628699445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 64.edn_err.3628699445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/64.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/87.edn_err.1220497989 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 20265815 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:14:13 AM UTC 24 |
| Finished | Oct 03 01:14:16 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220497989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 87.edn_err.1220497989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/87.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/94.edn_genbits.3053107360 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 222457700 ps |
| CPU time | 4.98 seconds |
| Started | Oct 03 01:14:21 AM UTC 24 |
| Finished | Oct 03 01:14:27 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053107360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3053107360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/94.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.2078632213 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4458217598 ps |
| CPU time | 111.34 seconds |
| Started | Oct 03 01:09:05 AM UTC 24 |
| Finished | Oct 03 01:10:59 AM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078632213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all _with_rand_reset.2078632213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_genbits.1678283154 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 56849404 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:09:07 AM UTC 24 |
| Finished | Oct 03 01:09:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678283154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1678283154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_intr.1881750436 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 21816313 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:10:15 AM UTC 24 |
| Finished | Oct 03 01:10:18 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881750436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1881750436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_alert.1309227359 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 27566826 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:11:01 AM UTC 24 |
| Finished | Oct 03 01:11:04 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309227359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_alert.1309227359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_genbits.3174139285 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 57900546 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 01:10:03 AM UTC 24 |
| Finished | Oct 03 01:10:06 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174139285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3174139285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/255.edn_genbits.2195024347 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 67387419 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 01:15:56 AM UTC 24 |
| Finished | Oct 03 01:15:59 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195024347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2195024347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/255.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_intr.1173208503 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 21756884 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:09:38 AM UTC 24 |
| Finished | Oct 03 01:09:41 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173208503 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1173208503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1283993472 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 263395402 ps |
| CPU time | 2.51 seconds |
| Started | Oct 03 01:16:37 AM UTC 24 |
| Finished | Oct 03 01:16:41 AM UTC 24 |
| Peak memory | 216852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283993472 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1283993472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/126.edn_genbits.1652613500 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 120693548 ps |
| CPU time | 2.74 seconds |
| Started | Oct 03 01:14:51 AM UTC 24 |
| Finished | Oct 03 01:14:55 AM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652613500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1652613500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/126.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/128.edn_genbits.3616678148 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 73996099 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 01:14:52 AM UTC 24 |
| Finished | Oct 03 01:14:56 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616678148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3616678148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/128.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/129.edn_genbits.2202712880 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 143669063 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 01:14:52 AM UTC 24 |
| Finished | Oct 03 01:14:57 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202712880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2202712880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/129.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/151.edn_genbits.722907740 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 47738940 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:15:08 AM UTC 24 |
| Finished | Oct 03 01:15:11 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722907740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 151.edn_genbits.722907740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/151.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/162.edn_genbits.309292572 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 38739981 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 01:15:15 AM UTC 24 |
| Finished | Oct 03 01:15:18 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309292572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 162.edn_genbits.309292572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/162.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/163.edn_genbits.2346102958 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 40624410 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 01:15:16 AM UTC 24 |
| Finished | Oct 03 01:15:19 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346102958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2346102958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/163.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/171.edn_genbits.2188578082 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 95163710 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:15:21 AM UTC 24 |
| Finished | Oct 03 01:15:24 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188578082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2188578082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/171.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/217.edn_genbits.2277120700 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 49276832 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 01:15:45 AM UTC 24 |
| Finished | Oct 03 01:15:48 AM UTC 24 |
| Peak memory | 229236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277120700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2277120700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/217.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_err.2935629244 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 26729430 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:11:51 AM UTC 24 |
| Finished | Oct 03 01:11:53 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935629244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 41.edn_err.2935629244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_err.3749637855 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 24851320 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:09:02 AM UTC 24 |
| Finished | Oct 03 01:09:04 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749637855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 10.edn_err.3749637855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/132.edn_alert.3152643067 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 206552895 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:14:55 AM UTC 24 |
| Finished | Oct 03 01:14:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152643067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 132.edn_alert.3152643067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/132.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/54.edn_alert.2101226636 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 29299374 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:13:25 AM UTC 24 |
| Finished | Oct 03 01:13:28 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101226636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 54.edn_alert.2101226636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/54.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/144.edn_genbits.26525173 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 45140635 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 01:15:03 AM UTC 24 |
| Finished | Oct 03 01:15:07 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26525173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 144.edn_genbits.26525173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/144.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.760630264 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 24647659 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:16:12 AM UTC 24 |
| Finished | Oct 03 01:16:14 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760630264 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.760630264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.2498898839 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 2085105702 ps |
| CPU time | 7.86 seconds |
| Started | Oct 03 01:16:12 AM UTC 24 |
| Finished | Oct 03 01:16:21 AM UTC 24 |
| Peak memory | 216788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498898839 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2498898839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.839135432 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 21752799 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:16:11 AM UTC 24 |
| Finished | Oct 03 01:16:13 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839135432 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.839135432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1072734186 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 75010451 ps |
| CPU time | 2.2 seconds |
| Started | Oct 03 01:16:13 AM UTC 24 |
| Finished | Oct 03 01:16:16 AM UTC 24 |
| Peak memory | 227148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1072734186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1072734186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.152485416 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 18412345 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:16:11 AM UTC 24 |
| Finished | Oct 03 01:16:13 AM UTC 24 |
| Peak memory | 215816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152485416 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.152485416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.2467419494 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 28526753 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 01:16:13 AM UTC 24 |
| Finished | Oct 03 01:16:16 AM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467419494 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2467419494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.2988020663 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 27374038 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 01:16:10 AM UTC 24 |
| Finished | Oct 03 01:16:14 AM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988020663 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2988020663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.384690085 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 94646221 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 01:16:10 AM UTC 24 |
| Finished | Oct 03 01:16:14 AM UTC 24 |
| Peak memory | 227276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384690085 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.384690085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.3230936255 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 43082802 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 01:16:15 AM UTC 24 |
| Finished | Oct 03 01:16:19 AM UTC 24 |
| Peak memory | 216788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230936255 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3230936255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.1150268525 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 350631524 ps |
| CPU time | 5.75 seconds |
| Started | Oct 03 01:16:14 AM UTC 24 |
| Finished | Oct 03 01:16:21 AM UTC 24 |
| Peak memory | 216788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150268525 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1150268525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.1263163171 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 44686525 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:16:14 AM UTC 24 |
| Finished | Oct 03 01:16:17 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263163171 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1263163171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3542650936 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 24957975 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:16:15 AM UTC 24 |
| Finished | Oct 03 01:16:18 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3542650936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3542650936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.2918911525 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 41191814 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:16:14 AM UTC 24 |
| Finished | Oct 03 01:16:17 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918911525 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2918911525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.3545638494 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 12535398 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:16:14 AM UTC 24 |
| Finished | Oct 03 01:16:17 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545638494 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3545638494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.1701817389 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 58703891 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 01:16:15 AM UTC 24 |
| Finished | Oct 03 01:16:19 AM UTC 24 |
| Peak memory | 217032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701817389 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.1701817389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.2873593357 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 132943150 ps |
| CPU time | 2.81 seconds |
| Started | Oct 03 01:16:13 AM UTC 24 |
| Finished | Oct 03 01:16:17 AM UTC 24 |
| Peak memory | 231176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873593357 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2873593357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.778099109 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 451215945 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 01:16:13 AM UTC 24 |
| Finished | Oct 03 01:16:18 AM UTC 24 |
| Peak memory | 227340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778099109 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.778099109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3036899131 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 32335608 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:16:38 AM UTC 24 |
| Finished | Oct 03 01:16:41 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3036899131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3036899131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.3732625482 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 14337281 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:16:37 AM UTC 24 |
| Finished | Oct 03 01:16:40 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732625482 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3732625482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.3453840217 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 27615867 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:16:37 AM UTC 24 |
| Finished | Oct 03 01:16:40 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453840217 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3453840217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.2764126620 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 55833617 ps |
| CPU time | 2.3 seconds |
| Started | Oct 03 01:16:38 AM UTC 24 |
| Finished | Oct 03 01:16:41 AM UTC 24 |
| Peak memory | 217048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764126620 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.2764126620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1647513852 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 85682776 ps |
| CPU time | 5.44 seconds |
| Started | Oct 03 01:16:36 AM UTC 24 |
| Finished | Oct 03 01:16:43 AM UTC 24 |
| Peak memory | 227204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647513852 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1647513852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2813329508 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 26960971 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:16:41 AM UTC 24 |
| Finished | Oct 03 01:16:44 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2813329508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2813329508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.4143722234 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 14697560 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:16:40 AM UTC 24 |
| Finished | Oct 03 01:16:42 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143722234 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4143722234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1672436151 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 19218288 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 01:16:40 AM UTC 24 |
| Finished | Oct 03 01:16:42 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672436151 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1672436151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.2421189907 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 48921683 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:16:41 AM UTC 24 |
| Finished | Oct 03 01:16:44 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421189907 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.2421189907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3261706513 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 69855465 ps |
| CPU time | 3.05 seconds |
| Started | Oct 03 01:16:39 AM UTC 24 |
| Finished | Oct 03 01:16:43 AM UTC 24 |
| Peak memory | 227136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261706513 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3261706513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1920091096 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 89330026 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 01:16:39 AM UTC 24 |
| Finished | Oct 03 01:16:42 AM UTC 24 |
| Peak memory | 227160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920091096 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1920091096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1773898283 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 190817157 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:16:42 AM UTC 24 |
| Finished | Oct 03 01:16:45 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1773898283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1773898283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3170326036 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 16411319 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 01:16:42 AM UTC 24 |
| Finished | Oct 03 01:16:44 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170326036 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3170326036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.1050504357 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 33985288 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 01:16:42 AM UTC 24 |
| Finished | Oct 03 01:16:44 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050504357 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1050504357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1529658654 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 70221523 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:16:42 AM UTC 24 |
| Finished | Oct 03 01:16:45 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529658654 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.1529658654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.371174735 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 104964966 ps |
| CPU time | 2.57 seconds |
| Started | Oct 03 01:16:41 AM UTC 24 |
| Finished | Oct 03 01:16:45 AM UTC 24 |
| Peak memory | 227140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371174735 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.371174735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3381633005 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 50175414 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 01:16:42 AM UTC 24 |
| Finished | Oct 03 01:16:45 AM UTC 24 |
| Peak memory | 216860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381633005 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3381633005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1957048881 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 18054457 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:16:45 AM UTC 24 |
| Finished | Oct 03 01:16:48 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1957048881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1957048881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.3339857755 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 40355495 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:16:44 AM UTC 24 |
| Finished | Oct 03 01:16:46 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339857755 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3339857755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2336847553 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 22713205 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:16:44 AM UTC 24 |
| Finished | Oct 03 01:16:46 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336847553 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2336847553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2089363769 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 19974820 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:16:44 AM UTC 24 |
| Finished | Oct 03 01:16:47 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089363769 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.2089363769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.205281119 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 214045774 ps |
| CPU time | 3.28 seconds |
| Started | Oct 03 01:16:43 AM UTC 24 |
| Finished | Oct 03 01:16:48 AM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205281119 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.205281119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.3316670569 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 44420156 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 01:16:44 AM UTC 24 |
| Finished | Oct 03 01:16:47 AM UTC 24 |
| Peak memory | 216920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316670569 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3316670569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1360009760 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 23700487 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 01:16:46 AM UTC 24 |
| Finished | Oct 03 01:16:50 AM UTC 24 |
| Peak memory | 227092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1360009760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1360009760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3028895474 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 17113505 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:16:46 AM UTC 24 |
| Finished | Oct 03 01:16:48 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028895474 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3028895474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3818315896 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 28846193 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:16:46 AM UTC 24 |
| Finished | Oct 03 01:16:48 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818315896 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3818315896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.63311341 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 53157637 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:16:46 AM UTC 24 |
| Finished | Oct 03 01:16:49 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63311341 -assert nopostproc +UVM_T ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.63311341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.3819798016 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 48104377 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 01:16:45 AM UTC 24 |
| Finished | Oct 03 01:16:49 AM UTC 24 |
| Peak memory | 227144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819798016 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3819798016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3727743234 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 287910684 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 01:16:45 AM UTC 24 |
| Finished | Oct 03 01:16:50 AM UTC 24 |
| Peak memory | 227088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727743234 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3727743234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1111054071 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 302392161 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 01:16:49 AM UTC 24 |
| Finished | Oct 03 01:16:52 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1111054071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1111054071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3660390956 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 80753004 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:16:47 AM UTC 24 |
| Finished | Oct 03 01:16:50 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660390956 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3660390956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.658079416 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 23407701 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:16:47 AM UTC 24 |
| Finished | Oct 03 01:16:50 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658079416 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.658079416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.951041669 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 33348546 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:16:48 AM UTC 24 |
| Finished | Oct 03 01:16:50 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951041669 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.951041669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3206499776 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 82981555 ps |
| CPU time | 3.95 seconds |
| Started | Oct 03 01:16:46 AM UTC 24 |
| Finished | Oct 03 01:16:51 AM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206499776 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3206499776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.217372845 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 101952187 ps |
| CPU time | 4.11 seconds |
| Started | Oct 03 01:16:47 AM UTC 24 |
| Finished | Oct 03 01:16:52 AM UTC 24 |
| Peak memory | 216848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217372845 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.217372845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4021558039 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 119280880 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:16:51 AM UTC 24 |
| Finished | Oct 03 01:16:54 AM UTC 24 |
| Peak memory | 224684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4021558039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4021558039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.2206870715 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 37749172 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 01:16:50 AM UTC 24 |
| Finished | Oct 03 01:16:52 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206870715 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2206870715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.1455629657 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 17198471 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 01:16:50 AM UTC 24 |
| Finished | Oct 03 01:16:52 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455629657 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1455629657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.2756406503 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 58669950 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:16:50 AM UTC 24 |
| Finished | Oct 03 01:16:52 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756406503 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.2756406503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.3936262210 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 149317534 ps |
| CPU time | 2.94 seconds |
| Started | Oct 03 01:16:49 AM UTC 24 |
| Finished | Oct 03 01:16:53 AM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936262210 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3936262210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1749847701 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 175716381 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:16:50 AM UTC 24 |
| Finished | Oct 03 01:16:53 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749847701 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1749847701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3648207352 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 240040183 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:16:52 AM UTC 24 |
| Finished | Oct 03 01:16:55 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3648207352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3648207352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2665352774 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 18680587 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 01:16:51 AM UTC 24 |
| Finished | Oct 03 01:16:53 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665352774 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2665352774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1094171233 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 14179503 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:16:51 AM UTC 24 |
| Finished | Oct 03 01:16:53 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094171233 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1094171233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.454885147 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 79572595 ps |
| CPU time | 2.42 seconds |
| Started | Oct 03 01:16:52 AM UTC 24 |
| Finished | Oct 03 01:16:56 AM UTC 24 |
| Peak memory | 216916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454885147 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.454885147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3858354932 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 80289719 ps |
| CPU time | 4.55 seconds |
| Started | Oct 03 01:16:51 AM UTC 24 |
| Finished | Oct 03 01:16:57 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858354932 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3858354932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1027722949 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 231426035 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 01:16:51 AM UTC 24 |
| Finished | Oct 03 01:16:54 AM UTC 24 |
| Peak memory | 216988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027722949 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1027722949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3707542160 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 31210264 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:16:54 AM UTC 24 |
| Finished | Oct 03 01:16:56 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3707542160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3707542160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3526966286 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 23176596 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:16:54 AM UTC 24 |
| Finished | Oct 03 01:16:56 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526966286 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3526966286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.25974902 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 41281762 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:16:54 AM UTC 24 |
| Finished | Oct 03 01:16:56 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25974902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.25974902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.2253836490 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 42804248 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 01:16:54 AM UTC 24 |
| Finished | Oct 03 01:16:57 AM UTC 24 |
| Peak memory | 216856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253836490 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.2253836490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.2881628656 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 112002975 ps |
| CPU time | 5.34 seconds |
| Started | Oct 03 01:16:52 AM UTC 24 |
| Finished | Oct 03 01:16:59 AM UTC 24 |
| Peak memory | 227144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881628656 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2881628656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1030930997 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 525773542 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 01:16:53 AM UTC 24 |
| Finished | Oct 03 01:16:57 AM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030930997 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1030930997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1321382534 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 55942465 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:16:56 AM UTC 24 |
| Finished | Oct 03 01:16:59 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1321382534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1321382534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1255045809 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 37103927 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:16:55 AM UTC 24 |
| Finished | Oct 03 01:16:57 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255045809 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1255045809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3535855932 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 10379727 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:16:55 AM UTC 24 |
| Finished | Oct 03 01:16:57 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535855932 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3535855932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.1804279131 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 19943891 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:16:56 AM UTC 24 |
| Finished | Oct 03 01:16:59 AM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804279131 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.1804279131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.1618482260 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 914167262 ps |
| CPU time | 5.7 seconds |
| Started | Oct 03 01:16:55 AM UTC 24 |
| Finished | Oct 03 01:17:02 AM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618482260 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1618482260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.277060168 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 138458555 ps |
| CPU time | 2.88 seconds |
| Started | Oct 03 01:16:55 AM UTC 24 |
| Finished | Oct 03 01:16:59 AM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277060168 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.277060168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.4147565766 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 65589605 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 01:16:19 AM UTC 24 |
| Finished | Oct 03 01:16:23 AM UTC 24 |
| Peak memory | 216788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147565766 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4147565766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.2707197351 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1330129666 ps |
| CPU time | 7.04 seconds |
| Started | Oct 03 01:16:18 AM UTC 24 |
| Finished | Oct 03 01:16:26 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707197351 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2707197351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.4146399297 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 46413454 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:16:18 AM UTC 24 |
| Finished | Oct 03 01:16:20 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146399297 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4146399297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.37786840 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 19865709 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:16:19 AM UTC 24 |
| Finished | Oct 03 01:16:22 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =37786840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.37786840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.2243230723 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 13131053 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:16:18 AM UTC 24 |
| Finished | Oct 03 01:16:21 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243230723 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2243230723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.1799761646 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 81637064 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:16:18 AM UTC 24 |
| Finished | Oct 03 01:16:20 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799761646 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1799761646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.219408027 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 65149124 ps |
| CPU time | 2.21 seconds |
| Started | Oct 03 01:16:19 AM UTC 24 |
| Finished | Oct 03 01:16:23 AM UTC 24 |
| Peak memory | 216784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219408027 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.219408027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.2997503884 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 206074042 ps |
| CPU time | 3.25 seconds |
| Started | Oct 03 01:16:17 AM UTC 24 |
| Finished | Oct 03 01:16:21 AM UTC 24 |
| Peak memory | 227208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997503884 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2997503884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.2517416991 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 613977867 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 01:16:18 AM UTC 24 |
| Finished | Oct 03 01:16:23 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517416991 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2517416991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.2444845777 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 14648692 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:16:57 AM UTC 24 |
| Finished | Oct 03 01:17:00 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444845777 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2444845777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.424106122 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 38027616 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 01:16:57 AM UTC 24 |
| Finished | Oct 03 01:17:00 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424106122 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.424106122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.2239253132 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 15184525 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:16:57 AM UTC 24 |
| Finished | Oct 03 01:17:00 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239253132 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2239253132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.2830689738 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 39526396 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:16:58 AM UTC 24 |
| Finished | Oct 03 01:17:00 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830689738 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2830689738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3848444469 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 38344096 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:16:58 AM UTC 24 |
| Finished | Oct 03 01:17:00 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848444469 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3848444469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.4157813422 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 26592188 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:16:59 AM UTC 24 |
| Finished | Oct 03 01:17:01 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157813422 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4157813422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.700734180 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 18152044 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:16:59 AM UTC 24 |
| Finished | Oct 03 01:17:01 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700734180 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.700734180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1933540576 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 15707222 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:16:59 AM UTC 24 |
| Finished | Oct 03 01:17:01 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933540576 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1933540576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3474894872 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 10381407 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:17:00 AM UTC 24 |
| Finished | Oct 03 01:17:02 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474894872 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3474894872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1982482730 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 162454235 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:17:00 AM UTC 24 |
| Finished | Oct 03 01:17:02 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982482730 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1982482730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.2719052465 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 193314689 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:16:22 AM UTC 24 |
| Finished | Oct 03 01:16:25 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719052465 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2719052465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.367473889 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 182365577 ps |
| CPU time | 6.1 seconds |
| Started | Oct 03 01:16:21 AM UTC 24 |
| Finished | Oct 03 01:16:29 AM UTC 24 |
| Peak memory | 216800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367473889 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.367473889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.1376836831 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 43240721 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:16:21 AM UTC 24 |
| Finished | Oct 03 01:16:25 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376836831 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1376836831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3957626913 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 73665722 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 01:16:24 AM UTC 24 |
| Finished | Oct 03 01:16:27 AM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3957626913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3957626913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.243653268 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 23517808 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:16:21 AM UTC 24 |
| Finished | Oct 03 01:16:24 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243653268 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.243653268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.2977196434 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 27645509 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:16:21 AM UTC 24 |
| Finished | Oct 03 01:16:24 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977196434 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2977196434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1682881524 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 86328017 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:16:23 AM UTC 24 |
| Finished | Oct 03 01:16:26 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682881524 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1682881524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.392603704 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 73928681 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 01:16:20 AM UTC 24 |
| Finished | Oct 03 01:16:26 AM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392603704 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.392603704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2509749123 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 383174344 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 01:16:20 AM UTC 24 |
| Finished | Oct 03 01:16:24 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509749123 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2509749123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1632250745 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 13743054 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:17:00 AM UTC 24 |
| Finished | Oct 03 01:17:02 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632250745 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1632250745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.843550666 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 27464036 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:17:00 AM UTC 24 |
| Finished | Oct 03 01:17:02 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843550666 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.843550666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.2513555903 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 18799767 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:17:00 AM UTC 24 |
| Finished | Oct 03 01:17:02 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513555903 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2513555903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3157824798 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 42030402 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:17:01 AM UTC 24 |
| Finished | Oct 03 01:17:03 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157824798 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3157824798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.838906967 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 15681538 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:17:01 AM UTC 24 |
| Finished | Oct 03 01:17:03 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838906967 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.838906967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3186405449 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 50090354 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:17:01 AM UTC 24 |
| Finished | Oct 03 01:17:04 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186405449 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3186405449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.390304936 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 22612288 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:17:01 AM UTC 24 |
| Finished | Oct 03 01:17:03 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390304936 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.390304936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.2169647859 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 14017725 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:17:02 AM UTC 24 |
| Finished | Oct 03 01:17:05 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169647859 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2169647859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3664530413 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 14592745 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:17:02 AM UTC 24 |
| Finished | Oct 03 01:17:05 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664530413 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3664530413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3792867615 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 40035505 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:17:03 AM UTC 24 |
| Finished | Oct 03 01:17:05 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792867615 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3792867615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.2018661439 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 54142253 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:16:26 AM UTC 24 |
| Finished | Oct 03 01:16:29 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018661439 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2018661439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.313002266 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 76480482 ps |
| CPU time | 4.12 seconds |
| Started | Oct 03 01:16:25 AM UTC 24 |
| Finished | Oct 03 01:16:31 AM UTC 24 |
| Peak memory | 216860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313002266 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.313002266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.3393108839 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 17705836 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:16:25 AM UTC 24 |
| Finished | Oct 03 01:16:28 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393108839 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3393108839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1758721899 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 80794098 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:16:26 AM UTC 24 |
| Finished | Oct 03 01:16:29 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1758721899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1758721899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.820086038 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 15126814 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:16:25 AM UTC 24 |
| Finished | Oct 03 01:16:28 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820086038 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.820086038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.3584956775 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 51987568 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:16:24 AM UTC 24 |
| Finished | Oct 03 01:16:27 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584956775 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3584956775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3681712751 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 96613218 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:16:26 AM UTC 24 |
| Finished | Oct 03 01:16:29 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681712751 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3681712751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.4286659605 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 32369840 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 01:16:24 AM UTC 24 |
| Finished | Oct 03 01:16:27 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286659605 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4286659605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.3706943121 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 254658192 ps |
| CPU time | 3.33 seconds |
| Started | Oct 03 01:16:24 AM UTC 24 |
| Finished | Oct 03 01:16:29 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706943121 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3706943121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.3425955780 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 22896245 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:17:03 AM UTC 24 |
| Finished | Oct 03 01:17:05 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425955780 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3425955780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2534134513 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 46802576 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:17:03 AM UTC 24 |
| Finished | Oct 03 01:17:05 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534134513 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2534134513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.984495683 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 74472918 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:17:03 AM UTC 24 |
| Finished | Oct 03 01:17:05 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984495683 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.984495683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2334755053 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 43165444 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:17:04 AM UTC 24 |
| Finished | Oct 03 01:17:06 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334755053 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2334755053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3764167290 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 34078422 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:17:04 AM UTC 24 |
| Finished | Oct 03 01:17:06 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764167290 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3764167290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.611471594 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 122762287 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:17:04 AM UTC 24 |
| Finished | Oct 03 01:17:06 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611471594 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.611471594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1650255535 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 35015300 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:17:04 AM UTC 24 |
| Finished | Oct 03 01:17:06 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650255535 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1650255535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.317104147 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 19854468 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:17:05 AM UTC 24 |
| Finished | Oct 03 01:17:07 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317104147 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.317104147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3537922362 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 10827660 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:17:05 AM UTC 24 |
| Finished | Oct 03 01:17:07 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537922362 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3537922362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1783727611 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 53672675 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:17:05 AM UTC 24 |
| Finished | Oct 03 01:17:07 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783727611 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1783727611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4285893086 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 30625011 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:16:29 AM UTC 24 |
| Finished | Oct 03 01:16:31 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4285893086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4285893086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.4029123687 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 29225280 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:16:29 AM UTC 24 |
| Finished | Oct 03 01:16:31 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029123687 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4029123687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.1205417471 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 24691062 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 01:16:27 AM UTC 24 |
| Finished | Oct 03 01:16:30 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205417471 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1205417471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.4198775967 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 41465889 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:16:29 AM UTC 24 |
| Finished | Oct 03 01:16:31 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198775967 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.4198775967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.2461848866 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 52170414 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:16:26 AM UTC 24 |
| Finished | Oct 03 01:16:29 AM UTC 24 |
| Peak memory | 224924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461848866 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2461848866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2989271913 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 23482455 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:16:30 AM UTC 24 |
| Finished | Oct 03 01:16:33 AM UTC 24 |
| Peak memory | 227036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2989271913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2989271913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.1448855652 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 25055665 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:16:30 AM UTC 24 |
| Finished | Oct 03 01:16:32 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448855652 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1448855652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.247959685 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 30986401 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:16:30 AM UTC 24 |
| Finished | Oct 03 01:16:32 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247959685 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.247959685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.2151978044 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 26009529 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:16:30 AM UTC 24 |
| Finished | Oct 03 01:16:33 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151978044 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.2151978044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.386557196 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 201749445 ps |
| CPU time | 3.13 seconds |
| Started | Oct 03 01:16:29 AM UTC 24 |
| Finished | Oct 03 01:16:33 AM UTC 24 |
| Peak memory | 227144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386557196 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.386557196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.3280357441 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 179231728 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 01:16:30 AM UTC 24 |
| Finished | Oct 03 01:16:33 AM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280357441 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3280357441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2089902703 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 30499399 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:16:32 AM UTC 24 |
| Finished | Oct 03 01:16:35 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2089902703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2089902703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.2901373842 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 83037757 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:16:32 AM UTC 24 |
| Finished | Oct 03 01:16:35 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901373842 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2901373842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.556488084 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 47841989 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:16:31 AM UTC 24 |
| Finished | Oct 03 01:16:34 AM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556488084 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.556488084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2015439994 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 112937168 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:16:32 AM UTC 24 |
| Finished | Oct 03 01:16:35 AM UTC 24 |
| Peak memory | 214036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015439994 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.2015439994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2820096243 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 35433769 ps |
| CPU time | 2.51 seconds |
| Started | Oct 03 01:16:30 AM UTC 24 |
| Finished | Oct 03 01:16:34 AM UTC 24 |
| Peak memory | 227208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820096243 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2820096243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1125157466 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 160881157 ps |
| CPU time | 3.13 seconds |
| Started | Oct 03 01:16:31 AM UTC 24 |
| Finished | Oct 03 01:16:35 AM UTC 24 |
| Peak memory | 216856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125157466 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1125157466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3207213803 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 104466822 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:16:34 AM UTC 24 |
| Finished | Oct 03 01:16:37 AM UTC 24 |
| Peak memory | 224956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3207213803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3207213803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2785946912 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 73427055 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:16:34 AM UTC 24 |
| Finished | Oct 03 01:16:36 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785946912 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2785946912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2157217281 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 30736050 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:16:34 AM UTC 24 |
| Finished | Oct 03 01:16:36 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157217281 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2157217281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.1070918409 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 51526546 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:16:34 AM UTC 24 |
| Finished | Oct 03 01:16:37 AM UTC 24 |
| Peak memory | 214736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070918409 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.1070918409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.824284684 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 26193731 ps |
| CPU time | 2.46 seconds |
| Started | Oct 03 01:16:33 AM UTC 24 |
| Finished | Oct 03 01:16:36 AM UTC 24 |
| Peak memory | 227152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824284684 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.824284684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.1125027923 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 83772954 ps |
| CPU time | 2.67 seconds |
| Started | Oct 03 01:16:34 AM UTC 24 |
| Finished | Oct 03 01:16:38 AM UTC 24 |
| Peak memory | 216792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125027923 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1125027923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3577408072 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 40773881 ps |
| CPU time | 2.3 seconds |
| Started | Oct 03 01:16:36 AM UTC 24 |
| Finished | Oct 03 01:16:40 AM UTC 24 |
| Peak memory | 227148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3577408072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3577408072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3600297437 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 24900240 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:16:36 AM UTC 24 |
| Finished | Oct 03 01:16:39 AM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600297437 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3600297437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3243128688 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 13244639 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:16:35 AM UTC 24 |
| Finished | Oct 03 01:16:38 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243128688 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3243128688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.2956595341 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 36794279 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:16:36 AM UTC 24 |
| Finished | Oct 03 01:16:39 AM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956595341 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.2956595341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.1534121313 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 356149005 ps |
| CPU time | 4.59 seconds |
| Started | Oct 03 01:16:35 AM UTC 24 |
| Finished | Oct 03 01:16:41 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534121313 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1534121313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1304779450 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 107085519 ps |
| CPU time | 4.19 seconds |
| Started | Oct 03 01:16:35 AM UTC 24 |
| Finished | Oct 03 01:16:41 AM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304779450 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1304779450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_disable.2414671645 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11043533 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:36 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414671645 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2414671645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_err.2407857118 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 22671264 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:36 AM UTC 24 |
| Peak memory | 246684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407857118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.edn_err.2407857118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_genbits.2530740261 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 77103719 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:08:32 AM UTC 24 |
| Finished | Oct 03 01:08:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530740261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2530740261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_intr.544300752 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 26649200 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544300752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.544300752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_sec_cm.784874183 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 474550633 ps |
| CPU time | 8.81 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:44 AM UTC 24 |
| Peak memory | 258740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784874183 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.784874183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_smoke.4285607370 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 147899283 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:08:31 AM UTC 24 |
| Finished | Oct 03 01:08:34 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285607370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_smoke.4285607370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/0.edn_stress_all.445190879 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 244268507 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 01:08:32 AM UTC 24 |
| Finished | Oct 03 01:08:35 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445190879 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.445190879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_alert.2625106358 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 99712713 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:08:34 AM UTC 24 |
| Finished | Oct 03 01:08:37 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625106358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_alert.2625106358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_alert_test.625212353 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 14970950 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 01:08:36 AM UTC 24 |
| Finished | Oct 03 01:08:38 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625212353 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.625212353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_disable.3727987643 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 30994110 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 01:08:35 AM UTC 24 |
| Finished | Oct 03 01:08:38 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727987643 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3727987643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.1034629676 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 153881594 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:08:36 AM UTC 24 |
| Finished | Oct 03 01:08:38 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034629676 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1034629676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_err.1531144567 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 137460342 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 01:08:34 AM UTC 24 |
| Finished | Oct 03 01:08:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531144567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.edn_err.1531144567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_intr.4179796770 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 29812237 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 01:08:34 AM UTC 24 |
| Finished | Oct 03 01:08:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179796770 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4179796770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_regwen.1351277029 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 23628129 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:36 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351277029 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.edn_regwen.1351277029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/1.edn_smoke.1934197415 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 23009711 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 01:08:33 AM UTC 24 |
| Finished | Oct 03 01:08:36 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934197415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_smoke.1934197415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_alert_test.4135407651 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 26362495 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:09:03 AM UTC 24 |
| Finished | Oct 03 01:09:05 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135407651 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4135407651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.3829749827 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 183945452 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:09:03 AM UTC 24 |
| Finished | Oct 03 01:09:05 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829749827 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.3829749827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_genbits.1701062550 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 69414976 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:09:00 AM UTC 24 |
| Finished | Oct 03 01:09:03 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701062550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1701062550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_intr.721367646 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 43550340 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:09:01 AM UTC 24 |
| Finished | Oct 03 01:09:04 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721367646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.721367646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_smoke.2079848938 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 24815185 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:09:00 AM UTC 24 |
| Finished | Oct 03 01:09:03 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079848938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_smoke.2079848938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_stress_all.1715690622 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 758999692 ps |
| CPU time | 6.05 seconds |
| Started | Oct 03 01:09:00 AM UTC 24 |
| Finished | Oct 03 01:09:07 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715690622 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1715690622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.411378837 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 5355575184 ps |
| CPU time | 112.81 seconds |
| Started | Oct 03 01:09:00 AM UTC 24 |
| Finished | Oct 03 01:10:55 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411378837 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_ with_rand_reset.411378837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/100.edn_alert.2419272061 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 134774573 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 01:14:30 AM UTC 24 |
| Finished | Oct 03 01:14:32 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419272061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 100.edn_alert.2419272061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/100.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/100.edn_genbits.2390176684 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 41378915 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 01:14:30 AM UTC 24 |
| Finished | Oct 03 01:14:33 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390176684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2390176684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/100.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/101.edn_alert.238799872 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 31026013 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:14:31 AM UTC 24 |
| Finished | Oct 03 01:14:34 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238799872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 101.edn_alert.238799872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/101.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/101.edn_genbits.2123605259 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 58337134 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:14:31 AM UTC 24 |
| Finished | Oct 03 01:14:33 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123605259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2123605259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/101.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/102.edn_alert.485750561 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 24130706 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:14:32 AM UTC 24 |
| Finished | Oct 03 01:14:35 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485750561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 102.edn_alert.485750561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/102.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/102.edn_genbits.981219539 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 69728749 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:14:31 AM UTC 24 |
| Finished | Oct 03 01:14:33 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981219539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 102.edn_genbits.981219539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/102.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/103.edn_alert.2321303330 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 33782872 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:14:33 AM UTC 24 |
| Finished | Oct 03 01:14:36 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321303330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 103.edn_alert.2321303330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/103.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/103.edn_genbits.4224870952 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 227041047 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:14:32 AM UTC 24 |
| Finished | Oct 03 01:14:34 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224870952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4224870952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/103.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/104.edn_alert.3903453673 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 71882404 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:14:33 AM UTC 24 |
| Finished | Oct 03 01:14:36 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903453673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 104.edn_alert.3903453673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/104.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/104.edn_genbits.46305794 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 39779821 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:14:33 AM UTC 24 |
| Finished | Oct 03 01:14:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46305794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 104.edn_genbits.46305794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/104.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/105.edn_alert.2785650703 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 49533610 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 01:14:34 AM UTC 24 |
| Finished | Oct 03 01:14:37 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785650703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 105.edn_alert.2785650703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/105.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/105.edn_genbits.2147294263 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 370819998 ps |
| CPU time | 3.49 seconds |
| Started | Oct 03 01:14:33 AM UTC 24 |
| Finished | Oct 03 01:14:38 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147294263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2147294263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/105.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/106.edn_alert.589480694 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 22617892 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:14:34 AM UTC 24 |
| Finished | Oct 03 01:14:37 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589480694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 106.edn_alert.589480694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/106.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/106.edn_genbits.2556898226 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 100598772 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:14:34 AM UTC 24 |
| Finished | Oct 03 01:14:38 AM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556898226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2556898226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/106.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/107.edn_alert.3893929570 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 33835521 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:14:36 AM UTC 24 |
| Finished | Oct 03 01:14:38 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893929570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 107.edn_alert.3893929570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/107.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/107.edn_genbits.2644559722 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 102005154 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 01:14:35 AM UTC 24 |
| Finished | Oct 03 01:14:40 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644559722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2644559722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/107.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/108.edn_alert.752899396 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 95429316 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:14:37 AM UTC 24 |
| Finished | Oct 03 01:14:39 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752899396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 108.edn_alert.752899396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/108.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/108.edn_genbits.371983184 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 96343879 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 01:14:37 AM UTC 24 |
| Finished | Oct 03 01:14:42 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371983184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 108.edn_genbits.371983184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/108.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/109.edn_alert.813520916 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 25890477 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:14:38 AM UTC 24 |
| Finished | Oct 03 01:14:41 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813520916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 109.edn_alert.813520916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/109.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/109.edn_genbits.1726010713 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 78855305 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:14:37 AM UTC 24 |
| Finished | Oct 03 01:14:39 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726010713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1726010713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/109.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_alert_test.2890717358 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 140311460 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:09:07 AM UTC 24 |
| Finished | Oct 03 01:09:09 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890717358 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2890717358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_disable.3346267301 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 28516851 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 01:09:05 AM UTC 24 |
| Finished | Oct 03 01:09:08 AM UTC 24 |
| Peak memory | 226988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346267301 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3346267301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_err.431611422 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 43421500 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:09:05 AM UTC 24 |
| Finished | Oct 03 01:09:08 AM UTC 24 |
| Peak memory | 242892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431611422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 11.edn_err.431611422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_genbits.1337945202 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 35587902 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:09:04 AM UTC 24 |
| Finished | Oct 03 01:09:07 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337945202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1337945202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_intr.2841090901 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 23967860 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:09:05 AM UTC 24 |
| Finished | Oct 03 01:09:08 AM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841090901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2841090901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_smoke.1699598900 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 50478812 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:09:04 AM UTC 24 |
| Finished | Oct 03 01:09:06 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699598900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_smoke.1699598900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/11.edn_stress_all.140771329 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1029653262 ps |
| CPU time | 4.93 seconds |
| Started | Oct 03 01:09:04 AM UTC 24 |
| Finished | Oct 03 01:09:10 AM UTC 24 |
| Peak memory | 228032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140771329 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.140771329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/11.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/110.edn_alert.157581684 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 175772603 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:14:39 AM UTC 24 |
| Finished | Oct 03 01:14:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157581684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 110.edn_alert.157581684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/110.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/110.edn_genbits.25513827 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 96222713 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:14:38 AM UTC 24 |
| Finished | Oct 03 01:14:41 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25513827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 110.edn_genbits.25513827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/110.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/111.edn_alert.1398209793 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 44579460 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:14:39 AM UTC 24 |
| Finished | Oct 03 01:14:42 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398209793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 111.edn_alert.1398209793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/111.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/111.edn_genbits.2503150861 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 69147321 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 01:14:39 AM UTC 24 |
| Finished | Oct 03 01:14:43 AM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503150861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2503150861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/111.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/112.edn_alert.4106125732 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 40703344 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:14:40 AM UTC 24 |
| Finished | Oct 03 01:14:43 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106125732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 112.edn_alert.4106125732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/112.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/112.edn_genbits.1901104544 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 124748221 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:14:40 AM UTC 24 |
| Finished | Oct 03 01:14:43 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901104544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1901104544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/112.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/113.edn_alert.3853902094 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 166661360 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:14:41 AM UTC 24 |
| Finished | Oct 03 01:14:44 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853902094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 113.edn_alert.3853902094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/113.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/113.edn_genbits.3596463446 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 231611795 ps |
| CPU time | 2.64 seconds |
| Started | Oct 03 01:14:40 AM UTC 24 |
| Finished | Oct 03 01:14:44 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596463446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3596463446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/113.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/114.edn_alert.854989023 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 46237724 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:14:42 AM UTC 24 |
| Finished | Oct 03 01:14:46 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854989023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 114.edn_alert.854989023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/114.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/114.edn_genbits.1241456442 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 214750514 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:14:42 AM UTC 24 |
| Finished | Oct 03 01:14:45 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241456442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1241456442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/114.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/115.edn_genbits.2702067373 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 57177022 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 01:14:43 AM UTC 24 |
| Finished | Oct 03 01:14:46 AM UTC 24 |
| Peak memory | 230156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702067373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2702067373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/115.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/116.edn_alert.3083767330 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 145618528 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:14:44 AM UTC 24 |
| Finished | Oct 03 01:14:47 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083767330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 116.edn_alert.3083767330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/116.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/116.edn_genbits.1742865710 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 63599479 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:14:44 AM UTC 24 |
| Finished | Oct 03 01:14:47 AM UTC 24 |
| Peak memory | 227188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742865710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1742865710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/116.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/117.edn_alert.3338006417 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 93834593 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:14:45 AM UTC 24 |
| Finished | Oct 03 01:14:48 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338006417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 117.edn_alert.3338006417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/117.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/117.edn_genbits.2023160465 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 174407569 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 01:14:44 AM UTC 24 |
| Finished | Oct 03 01:14:47 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023160465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2023160465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/117.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/118.edn_alert.3686277822 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 97735627 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:14:45 AM UTC 24 |
| Finished | Oct 03 01:14:48 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686277822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 118.edn_alert.3686277822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/118.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/118.edn_genbits.1789164992 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 33444280 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:14:45 AM UTC 24 |
| Finished | Oct 03 01:14:47 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789164992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1789164992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/118.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/119.edn_alert.2538134659 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 82896271 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:14:46 AM UTC 24 |
| Finished | Oct 03 01:14:49 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538134659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 119.edn_alert.2538134659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/119.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/119.edn_genbits.1870279140 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 53367289 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 01:14:45 AM UTC 24 |
| Finished | Oct 03 01:14:48 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870279140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1870279140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/119.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_alert_test.2732190971 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 91376274 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:09:10 AM UTC 24 |
| Finished | Oct 03 01:09:13 AM UTC 24 |
| Peak memory | 227120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732190971 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2732190971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_err.1141825523 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 27287005 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:09:09 AM UTC 24 |
| Finished | Oct 03 01:09:12 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141825523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 12.edn_err.1141825523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_intr.363639435 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 36779199 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:09:09 AM UTC 24 |
| Finished | Oct 03 01:09:11 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363639435 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.363639435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_smoke.902677324 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 18423733 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 01:09:07 AM UTC 24 |
| Finished | Oct 03 01:09:09 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902677324 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.edn_smoke.902677324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_stress_all.3781839273 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 196174040 ps |
| CPU time | 5.34 seconds |
| Started | Oct 03 01:09:08 AM UTC 24 |
| Finished | Oct 03 01:09:14 AM UTC 24 |
| Peak memory | 230224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781839273 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3781839273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.2947613713 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9298344669 ps |
| CPU time | 33.07 seconds |
| Started | Oct 03 01:09:08 AM UTC 24 |
| Finished | Oct 03 01:09:42 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947613713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all _with_rand_reset.2947613713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/120.edn_alert.3008553672 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 101614676 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:14:47 AM UTC 24 |
| Finished | Oct 03 01:14:50 AM UTC 24 |
| Peak memory | 228980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008553672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 120.edn_alert.3008553672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/120.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/120.edn_genbits.1372562420 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 48407189 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 01:14:46 AM UTC 24 |
| Finished | Oct 03 01:14:49 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372562420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1372562420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/120.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/121.edn_alert.418838472 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 42130840 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:14:47 AM UTC 24 |
| Finished | Oct 03 01:14:50 AM UTC 24 |
| Peak memory | 226948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418838472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 121.edn_alert.418838472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/121.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/121.edn_genbits.245708065 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 108550701 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:14:47 AM UTC 24 |
| Finished | Oct 03 01:14:50 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245708065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 121.edn_genbits.245708065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/121.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/122.edn_alert.2182637954 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 70122803 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:14:49 AM UTC 24 |
| Finished | Oct 03 01:14:51 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182637954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 122.edn_alert.2182637954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/122.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/122.edn_genbits.200702240 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 77065725 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:14:47 AM UTC 24 |
| Finished | Oct 03 01:14:50 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200702240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 122.edn_genbits.200702240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/122.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/123.edn_alert.4125418595 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 32389043 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:14:49 AM UTC 24 |
| Finished | Oct 03 01:14:52 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125418595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 123.edn_alert.4125418595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/123.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/123.edn_genbits.1648540218 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 46490611 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 01:14:49 AM UTC 24 |
| Finished | Oct 03 01:14:52 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648540218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1648540218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/123.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/124.edn_genbits.1185378501 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 69347585 ps |
| CPU time | 2.43 seconds |
| Started | Oct 03 01:14:49 AM UTC 24 |
| Finished | Oct 03 01:14:52 AM UTC 24 |
| Peak memory | 230284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185378501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1185378501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/124.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/125.edn_alert.432476826 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 39359180 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:14:50 AM UTC 24 |
| Finished | Oct 03 01:14:53 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432476826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 125.edn_alert.432476826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/125.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/125.edn_genbits.4263635295 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 109304499 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 01:14:50 AM UTC 24 |
| Finished | Oct 03 01:14:53 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263635295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4263635295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/125.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/126.edn_alert.4071616470 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 137100360 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:14:51 AM UTC 24 |
| Finished | Oct 03 01:14:54 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071616470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 126.edn_alert.4071616470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/126.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/127.edn_alert.4102980304 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 122734923 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:14:51 AM UTC 24 |
| Finished | Oct 03 01:14:54 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102980304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 127.edn_alert.4102980304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/127.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/127.edn_genbits.3979719222 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 96209561 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:14:51 AM UTC 24 |
| Finished | Oct 03 01:14:54 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979719222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3979719222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/127.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/128.edn_alert.2150274922 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 35548664 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:14:52 AM UTC 24 |
| Finished | Oct 03 01:14:55 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150274922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 128.edn_alert.2150274922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/128.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/129.edn_alert.1094873073 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 81635723 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:14:53 AM UTC 24 |
| Finished | Oct 03 01:14:56 AM UTC 24 |
| Peak memory | 229312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094873073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 129.edn_alert.1094873073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/129.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_alert.1225779395 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 41414092 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:09:13 AM UTC 24 |
| Finished | Oct 03 01:09:16 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225779395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_alert.1225779395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_alert_test.574857478 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 64191292 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:09:14 AM UTC 24 |
| Finished | Oct 03 01:09:16 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574857478 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.574857478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.3667463927 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 47071540 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 01:09:14 AM UTC 24 |
| Finished | Oct 03 01:09:17 AM UTC 24 |
| Peak memory | 228700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667463927 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.3667463927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_err.3893439847 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 71614659 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:09:13 AM UTC 24 |
| Finished | Oct 03 01:09:15 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893439847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 13.edn_err.3893439847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_genbits.1361100883 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 71931751 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:09:10 AM UTC 24 |
| Finished | Oct 03 01:09:13 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361100883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1361100883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_smoke.3187139518 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 18315141 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:09:10 AM UTC 24 |
| Finished | Oct 03 01:09:13 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187139518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_smoke.3187139518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_stress_all.3969079238 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 199333257 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 01:09:10 AM UTC 24 |
| Finished | Oct 03 01:09:14 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969079238 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3969079238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.1348890214 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 4787110673 ps |
| CPU time | 128.85 seconds |
| Started | Oct 03 01:09:13 AM UTC 24 |
| Finished | Oct 03 01:11:24 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348890214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all _with_rand_reset.1348890214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/130.edn_genbits.4664400 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 36854982 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 01:14:53 AM UTC 24 |
| Finished | Oct 03 01:14:57 AM UTC 24 |
| Peak memory | 229260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4664400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_ genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 130.edn_genbits.4664400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/130.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/131.edn_alert.1854696275 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 22824719 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:14:55 AM UTC 24 |
| Finished | Oct 03 01:14:57 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854696275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 131.edn_alert.1854696275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/131.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/131.edn_genbits.3191468825 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 42781921 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 01:14:55 AM UTC 24 |
| Finished | Oct 03 01:14:58 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191468825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3191468825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/131.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/132.edn_genbits.3884637229 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 263661504 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:14:55 AM UTC 24 |
| Finished | Oct 03 01:14:58 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884637229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3884637229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/132.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/133.edn_alert.2978938831 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 85312918 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:14:56 AM UTC 24 |
| Finished | Oct 03 01:14:59 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978938831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 133.edn_alert.2978938831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/133.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/133.edn_genbits.2007614496 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 72719548 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 01:14:56 AM UTC 24 |
| Finished | Oct 03 01:14:59 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007614496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2007614496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/133.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/134.edn_alert.2493877830 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 52996778 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 01:14:57 AM UTC 24 |
| Finished | Oct 03 01:15:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493877830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 134.edn_alert.2493877830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/134.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/134.edn_genbits.770884612 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 97171098 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:14:57 AM UTC 24 |
| Finished | Oct 03 01:15:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770884612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 134.edn_genbits.770884612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/134.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/135.edn_alert.738468584 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 49033604 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 01:14:57 AM UTC 24 |
| Finished | Oct 03 01:15:00 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738468584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 135.edn_alert.738468584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/135.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/135.edn_genbits.394130193 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 138159888 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:14:57 AM UTC 24 |
| Finished | Oct 03 01:15:00 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394130193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 135.edn_genbits.394130193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/135.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/136.edn_alert.650211988 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 78670628 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:14:58 AM UTC 24 |
| Finished | Oct 03 01:15:01 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650211988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 136.edn_alert.650211988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/136.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/136.edn_genbits.27634576 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 46925344 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 01:14:58 AM UTC 24 |
| Finished | Oct 03 01:15:02 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27634576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 136.edn_genbits.27634576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/136.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/137.edn_alert.2022836364 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 45978103 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:14:59 AM UTC 24 |
| Finished | Oct 03 01:15:01 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022836364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 137.edn_alert.2022836364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/137.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/137.edn_genbits.4092983909 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 34490525 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:14:58 AM UTC 24 |
| Finished | Oct 03 01:15:01 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092983909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4092983909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/137.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/138.edn_alert.3120437238 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 66579632 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:15:00 AM UTC 24 |
| Finished | Oct 03 01:15:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120437238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 138.edn_alert.3120437238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/138.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/138.edn_genbits.3498110304 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 71967996 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:15:00 AM UTC 24 |
| Finished | Oct 03 01:15:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498110304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3498110304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/138.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/139.edn_alert.2191856292 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 35145080 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:15:01 AM UTC 24 |
| Finished | Oct 03 01:15:03 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191856292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 139.edn_alert.2191856292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/139.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/139.edn_genbits.1232737402 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 55573378 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:15:00 AM UTC 24 |
| Finished | Oct 03 01:15:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232737402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1232737402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/139.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_alert.4235678537 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 74369753 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:09:16 AM UTC 24 |
| Finished | Oct 03 01:09:19 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235678537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_alert.4235678537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_alert_test.3236095724 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 99078615 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:09:18 AM UTC 24 |
| Finished | Oct 03 01:09:20 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236095724 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3236095724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_disable.3055533851 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 39797150 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:09:17 AM UTC 24 |
| Finished | Oct 03 01:09:20 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055533851 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3055533851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.1150310031 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 89056818 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:09:17 AM UTC 24 |
| Finished | Oct 03 01:09:20 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150310031 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.1150310031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_err.3718320509 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 19149275 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:09:16 AM UTC 24 |
| Finished | Oct 03 01:09:19 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718320509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 14.edn_err.3718320509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_genbits.2654569609 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 38572580 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 01:09:15 AM UTC 24 |
| Finished | Oct 03 01:09:18 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654569609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2654569609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_intr.1577625516 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 21327628 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 01:09:16 AM UTC 24 |
| Finished | Oct 03 01:09:19 AM UTC 24 |
| Peak memory | 228792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577625516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1577625516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_smoke.1626797389 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 16041360 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:09:14 AM UTC 24 |
| Finished | Oct 03 01:09:16 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626797389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_smoke.1626797389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_stress_all.203857320 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 303585815 ps |
| CPU time | 7.91 seconds |
| Started | Oct 03 01:09:15 AM UTC 24 |
| Finished | Oct 03 01:09:24 AM UTC 24 |
| Peak memory | 228108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203857320 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.203857320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.3777677375 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1540697200 ps |
| CPU time | 38.92 seconds |
| Started | Oct 03 01:09:16 AM UTC 24 |
| Finished | Oct 03 01:09:57 AM UTC 24 |
| Peak memory | 232096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777677375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all _with_rand_reset.3777677375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/140.edn_genbits.4094806810 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 28764668 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:15:01 AM UTC 24 |
| Finished | Oct 03 01:15:04 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094806810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4094806810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/140.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/141.edn_alert.237489137 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 31938636 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 01:15:02 AM UTC 24 |
| Finished | Oct 03 01:15:05 AM UTC 24 |
| Peak memory | 232772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237489137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 141.edn_alert.237489137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/141.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/141.edn_genbits.3625592299 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 31511410 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:15:01 AM UTC 24 |
| Finished | Oct 03 01:15:04 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625592299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3625592299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/141.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/142.edn_alert.2275271154 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 51090935 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:15:02 AM UTC 24 |
| Finished | Oct 03 01:15:05 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275271154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 142.edn_alert.2275271154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/142.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/142.edn_genbits.4035423314 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 31228592 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:15:02 AM UTC 24 |
| Finished | Oct 03 01:15:05 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035423314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4035423314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/142.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/143.edn_alert.3044743267 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 23846154 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:15:03 AM UTC 24 |
| Finished | Oct 03 01:15:06 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044743267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 143.edn_alert.3044743267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/143.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/143.edn_genbits.3990676700 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 46796187 ps |
| CPU time | 2.51 seconds |
| Started | Oct 03 01:15:03 AM UTC 24 |
| Finished | Oct 03 01:15:07 AM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990676700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3990676700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/143.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/144.edn_alert.3394393578 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 194880044 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:15:03 AM UTC 24 |
| Finished | Oct 03 01:15:06 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394393578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 144.edn_alert.3394393578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/144.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/145.edn_alert.2559324192 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 221249506 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:15:05 AM UTC 24 |
| Finished | Oct 03 01:15:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559324192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 145.edn_alert.2559324192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/145.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/145.edn_genbits.3600107530 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 40778942 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:15:05 AM UTC 24 |
| Finished | Oct 03 01:15:07 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600107530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3600107530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/145.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/146.edn_alert.4149411121 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 36248628 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 01:15:05 AM UTC 24 |
| Finished | Oct 03 01:15:07 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149411121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 146.edn_alert.4149411121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/146.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/146.edn_genbits.3392643933 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 97373527 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 01:15:05 AM UTC 24 |
| Finished | Oct 03 01:15:08 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392643933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3392643933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/146.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/147.edn_alert.909282323 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 266576726 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:15:06 AM UTC 24 |
| Finished | Oct 03 01:15:09 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909282323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 147.edn_alert.909282323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/147.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/147.edn_genbits.3545056057 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 61572308 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 01:15:05 AM UTC 24 |
| Finished | Oct 03 01:15:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545056057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3545056057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/147.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/148.edn_alert.1354853810 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 37105373 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 01:15:06 AM UTC 24 |
| Finished | Oct 03 01:15:09 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354853810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 148.edn_alert.1354853810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/148.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/148.edn_genbits.4280850568 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 87591164 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 01:15:06 AM UTC 24 |
| Finished | Oct 03 01:15:09 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280850568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4280850568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/148.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/149.edn_alert.4096106990 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 24235331 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:15:07 AM UTC 24 |
| Finished | Oct 03 01:15:10 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096106990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 149.edn_alert.4096106990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/149.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/149.edn_genbits.2095352953 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 29057930 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:15:07 AM UTC 24 |
| Finished | Oct 03 01:15:10 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095352953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2095352953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/149.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_alert_test.3954804354 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 19320283 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:09:22 AM UTC 24 |
| Finished | Oct 03 01:09:25 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954804354 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3954804354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_disable.661345812 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 18134817 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:09:21 AM UTC 24 |
| Finished | Oct 03 01:09:23 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661345812 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.661345812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2075388768 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 30472679 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:09:21 AM UTC 24 |
| Finished | Oct 03 01:09:24 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075388768 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2075388768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_err.4151412817 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 56051821 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:09:21 AM UTC 24 |
| Finished | Oct 03 01:09:24 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151412817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 15.edn_err.4151412817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_intr.231210151 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 20068422 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:09:20 AM UTC 24 |
| Finished | Oct 03 01:09:22 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231210151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.231210151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_smoke.1199416484 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 30926469 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:09:19 AM UTC 24 |
| Finished | Oct 03 01:09:21 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199416484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.edn_smoke.1199416484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/15.edn_stress_all.3084418501 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 177205314 ps |
| CPU time | 5 seconds |
| Started | Oct 03 01:09:20 AM UTC 24 |
| Finished | Oct 03 01:09:26 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084418501 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3084418501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/15.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/150.edn_alert.3864972359 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 219310426 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:15:07 AM UTC 24 |
| Finished | Oct 03 01:15:10 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864972359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 150.edn_alert.3864972359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/150.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/150.edn_genbits.93565836 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 138520973 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:15:07 AM UTC 24 |
| Finished | Oct 03 01:15:10 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93565836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 150.edn_genbits.93565836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/150.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/151.edn_alert.1289446739 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 38599761 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 01:15:09 AM UTC 24 |
| Finished | Oct 03 01:15:11 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289446739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 151.edn_alert.1289446739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/151.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/152.edn_alert.470460226 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 179870132 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:15:09 AM UTC 24 |
| Finished | Oct 03 01:15:12 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470460226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 152.edn_alert.470460226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/152.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/152.edn_genbits.2275666585 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 64227999 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:15:09 AM UTC 24 |
| Finished | Oct 03 01:15:11 AM UTC 24 |
| Peak memory | 226948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275666585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2275666585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/152.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/153.edn_alert.2147871903 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 74912212 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 01:15:10 AM UTC 24 |
| Finished | Oct 03 01:15:13 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147871903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 153.edn_alert.2147871903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/153.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/153.edn_genbits.2106439421 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 112610712 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:15:09 AM UTC 24 |
| Finished | Oct 03 01:15:11 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106439421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2106439421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/153.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/154.edn_alert.1406444109 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 96102808 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:15:10 AM UTC 24 |
| Finished | Oct 03 01:15:13 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406444109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 154.edn_alert.1406444109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/154.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/154.edn_genbits.1028838915 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 44588161 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:15:10 AM UTC 24 |
| Finished | Oct 03 01:15:12 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028838915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1028838915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/154.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/155.edn_alert.466626268 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 79587271 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:15:11 AM UTC 24 |
| Finished | Oct 03 01:15:14 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466626268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 155.edn_alert.466626268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/155.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/155.edn_genbits.3755085969 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 39115134 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:15:11 AM UTC 24 |
| Finished | Oct 03 01:15:14 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755085969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3755085969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/155.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/156.edn_alert.1174742139 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 37211969 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 01:15:11 AM UTC 24 |
| Finished | Oct 03 01:15:14 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174742139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 156.edn_alert.1174742139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/156.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/156.edn_genbits.3527771160 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 80875753 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:15:11 AM UTC 24 |
| Finished | Oct 03 01:15:14 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527771160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3527771160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/156.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/157.edn_alert.3456298470 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 46662620 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:15:12 AM UTC 24 |
| Finished | Oct 03 01:15:15 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456298470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 157.edn_alert.3456298470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/157.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/157.edn_genbits.3977575284 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 69989890 ps |
| CPU time | 3.09 seconds |
| Started | Oct 03 01:15:12 AM UTC 24 |
| Finished | Oct 03 01:15:17 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977575284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3977575284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/157.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/158.edn_alert.4088428802 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 101727938 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:12 AM UTC 24 |
| Finished | Oct 03 01:15:15 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088428802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 158.edn_alert.4088428802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/158.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/158.edn_genbits.413235914 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 38504536 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:15:12 AM UTC 24 |
| Finished | Oct 03 01:15:15 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413235914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 158.edn_genbits.413235914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/158.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/159.edn_alert.2112339733 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 24165386 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 01:15:14 AM UTC 24 |
| Finished | Oct 03 01:15:16 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112339733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 159.edn_alert.2112339733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/159.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/159.edn_genbits.3255181815 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 24445088 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:15:12 AM UTC 24 |
| Finished | Oct 03 01:15:15 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255181815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3255181815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/159.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_alert.2300710046 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 40243486 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:09:25 AM UTC 24 |
| Finished | Oct 03 01:09:27 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300710046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_alert.2300710046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_alert_test.883926995 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 72114669 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:09:27 AM UTC 24 |
| Finished | Oct 03 01:09:30 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883926995 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.883926995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_disable.3075096110 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 12934351 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:09:26 AM UTC 24 |
| Finished | Oct 03 01:09:28 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075096110 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3075096110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.1010591984 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 26666438 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:09:26 AM UTC 24 |
| Finished | Oct 03 01:09:28 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010591984 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.1010591984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_err.357532968 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 201627935 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 01:09:25 AM UTC 24 |
| Finished | Oct 03 01:09:28 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357532968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 16.edn_err.357532968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_genbits.3263800442 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 56821683 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 01:09:24 AM UTC 24 |
| Finished | Oct 03 01:09:27 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263800442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3263800442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_intr.548035075 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 36826379 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:09:25 AM UTC 24 |
| Finished | Oct 03 01:09:27 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548035075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.548035075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_smoke.3460217078 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 29697405 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:09:22 AM UTC 24 |
| Finished | Oct 03 01:09:25 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460217078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_smoke.3460217078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/16.edn_stress_all.54039032 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 123745535 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 01:09:25 AM UTC 24 |
| Finished | Oct 03 01:09:28 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54039032 -assert nopostproc +UVM_TESTNAME=edn_s tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.54039032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/16.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/160.edn_alert.4107686228 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 38374687 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:15:14 AM UTC 24 |
| Finished | Oct 03 01:15:16 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107686228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 160.edn_alert.4107686228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/160.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/160.edn_genbits.1708303734 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 70050571 ps |
| CPU time | 2.24 seconds |
| Started | Oct 03 01:15:14 AM UTC 24 |
| Finished | Oct 03 01:15:17 AM UTC 24 |
| Peak memory | 230168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708303734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1708303734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/160.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/161.edn_alert.2687464355 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 27711764 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:15:15 AM UTC 24 |
| Finished | Oct 03 01:15:18 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687464355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 161.edn_alert.2687464355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/161.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/161.edn_genbits.1127308984 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 173087633 ps |
| CPU time | 3.95 seconds |
| Started | Oct 03 01:15:15 AM UTC 24 |
| Finished | Oct 03 01:15:20 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127308984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1127308984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/161.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/162.edn_alert.3438547240 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 52722344 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:15:15 AM UTC 24 |
| Finished | Oct 03 01:15:18 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438547240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 162.edn_alert.3438547240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/162.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/163.edn_alert.1018358815 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 52537423 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:16 AM UTC 24 |
| Finished | Oct 03 01:15:19 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018358815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 163.edn_alert.1018358815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/163.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/164.edn_alert.3400365252 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 79141517 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:15:16 AM UTC 24 |
| Finished | Oct 03 01:15:19 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400365252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 164.edn_alert.3400365252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/164.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/164.edn_genbits.4179079434 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 47638837 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:15:16 AM UTC 24 |
| Finished | Oct 03 01:15:19 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179079434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4179079434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/164.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/165.edn_alert.925256306 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 47616678 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:15:17 AM UTC 24 |
| Finished | Oct 03 01:15:20 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925256306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 165.edn_alert.925256306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/165.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/165.edn_genbits.161200588 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 54522387 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:15:17 AM UTC 24 |
| Finished | Oct 03 01:15:20 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161200588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 165.edn_genbits.161200588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/165.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/166.edn_alert.3806710829 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 42293636 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:15:17 AM UTC 24 |
| Finished | Oct 03 01:15:20 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806710829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 166.edn_alert.3806710829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/166.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/166.edn_genbits.1281728088 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 36387916 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:15:17 AM UTC 24 |
| Finished | Oct 03 01:15:20 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281728088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1281728088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/166.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/167.edn_alert.1294239443 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 98405295 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:15:19 AM UTC 24 |
| Finished | Oct 03 01:15:21 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294239443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 167.edn_alert.1294239443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/167.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/167.edn_genbits.3936802733 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 41574934 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:15:19 AM UTC 24 |
| Finished | Oct 03 01:15:22 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936802733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3936802733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/167.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/168.edn_alert.1306219790 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 33638140 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:15:20 AM UTC 24 |
| Finished | Oct 03 01:15:22 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306219790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 168.edn_alert.1306219790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/168.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/168.edn_genbits.3442733476 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 63432951 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:15:19 AM UTC 24 |
| Finished | Oct 03 01:15:21 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442733476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3442733476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/168.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/169.edn_alert.2166413788 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 26030922 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:15:20 AM UTC 24 |
| Finished | Oct 03 01:15:23 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166413788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 169.edn_alert.2166413788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/169.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/169.edn_genbits.2015127534 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 133889257 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:15:20 AM UTC 24 |
| Finished | Oct 03 01:15:22 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015127534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2015127534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/169.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_alert.47198530 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 59235498 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:09:29 AM UTC 24 |
| Finished | Oct 03 01:09:31 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47198530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.47198530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_alert_test.2149836735 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 17275750 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:09:31 AM UTC 24 |
| Finished | Oct 03 01:09:34 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149836735 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2149836735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_disable.2953644442 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 26434633 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 01:09:30 AM UTC 24 |
| Finished | Oct 03 01:09:32 AM UTC 24 |
| Peak memory | 226924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953644442 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2953644442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.2958950 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 75557655 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:09:30 AM UTC 24 |
| Finished | Oct 03 01:09:33 AM UTC 24 |
| Peak memory | 226824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958950 -assert nopostproc +UVM_TESTNAME=edn_disabl e_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.2958950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_err.2375516101 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 121897341 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:09:30 AM UTC 24 |
| Finished | Oct 03 01:09:32 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375516101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 17.edn_err.2375516101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_genbits.3203439405 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 47212278 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 01:09:27 AM UTC 24 |
| Finished | Oct 03 01:09:31 AM UTC 24 |
| Peak memory | 232188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203439405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3203439405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_intr.3667823734 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 34287851 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:09:29 AM UTC 24 |
| Finished | Oct 03 01:09:31 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667823734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3667823734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_smoke.2060153824 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 24143620 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:09:27 AM UTC 24 |
| Finished | Oct 03 01:09:30 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060153824 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.edn_smoke.2060153824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_stress_all.211467995 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 421536626 ps |
| CPU time | 6.16 seconds |
| Started | Oct 03 01:09:28 AM UTC 24 |
| Finished | Oct 03 01:09:36 AM UTC 24 |
| Peak memory | 228032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211467995 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.211467995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.4057137704 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 11075653260 ps |
| CPU time | 83.16 seconds |
| Started | Oct 03 01:09:29 AM UTC 24 |
| Finished | Oct 03 01:10:54 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057137704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all _with_rand_reset.4057137704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/170.edn_alert.291007162 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 29846962 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:15:21 AM UTC 24 |
| Finished | Oct 03 01:15:23 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291007162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 170.edn_alert.291007162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/170.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/170.edn_genbits.3293219169 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 27393515 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:15:21 AM UTC 24 |
| Finished | Oct 03 01:15:24 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293219169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3293219169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/170.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/171.edn_alert.3265600977 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 230834235 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:15:21 AM UTC 24 |
| Finished | Oct 03 01:15:24 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265600977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 171.edn_alert.3265600977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/171.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/172.edn_alert.3078423977 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 54760752 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:15:21 AM UTC 24 |
| Finished | Oct 03 01:15:24 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078423977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 172.edn_alert.3078423977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/172.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/172.edn_genbits.4021351507 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 67140905 ps |
| CPU time | 2.21 seconds |
| Started | Oct 03 01:15:21 AM UTC 24 |
| Finished | Oct 03 01:15:24 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021351507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4021351507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/172.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/173.edn_alert.4165483205 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 83563176 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:15:22 AM UTC 24 |
| Finished | Oct 03 01:15:25 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165483205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 173.edn_alert.4165483205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/173.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/173.edn_genbits.1070976283 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 33701016 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 01:15:22 AM UTC 24 |
| Finished | Oct 03 01:15:25 AM UTC 24 |
| Peak memory | 231056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070976283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1070976283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/173.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/174.edn_alert.314086156 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 100147603 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:23 AM UTC 24 |
| Finished | Oct 03 01:15:26 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314086156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 174.edn_alert.314086156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/174.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/174.edn_genbits.3900056344 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 528981229 ps |
| CPU time | 5.05 seconds |
| Started | Oct 03 01:15:22 AM UTC 24 |
| Finished | Oct 03 01:15:28 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900056344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3900056344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/174.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/175.edn_alert.249220427 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 28795935 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:15:24 AM UTC 24 |
| Finished | Oct 03 01:15:26 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249220427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 175.edn_alert.249220427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/175.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/175.edn_genbits.1249397531 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 56215389 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:15:23 AM UTC 24 |
| Finished | Oct 03 01:15:26 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249397531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1249397531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/175.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/176.edn_alert.1828181200 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 48209393 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:15:25 AM UTC 24 |
| Finished | Oct 03 01:15:27 AM UTC 24 |
| Peak memory | 228916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828181200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 176.edn_alert.1828181200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/176.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/176.edn_genbits.3516864037 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 54042734 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:15:25 AM UTC 24 |
| Finished | Oct 03 01:15:27 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516864037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3516864037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/176.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/177.edn_alert.18007564 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 27512211 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:15:25 AM UTC 24 |
| Finished | Oct 03 01:15:28 AM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18007564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.18007564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/177.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/177.edn_genbits.2500498583 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 88365633 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 01:15:25 AM UTC 24 |
| Finished | Oct 03 01:15:28 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500498583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2500498583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/177.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/178.edn_alert.2562040286 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 46280848 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:15:26 AM UTC 24 |
| Finished | Oct 03 01:15:29 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562040286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 178.edn_alert.2562040286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/178.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/178.edn_genbits.831551032 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 39744431 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:15:25 AM UTC 24 |
| Finished | Oct 03 01:15:27 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831551032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 178.edn_genbits.831551032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/178.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/179.edn_alert.3208032703 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 27506270 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:15:26 AM UTC 24 |
| Finished | Oct 03 01:15:29 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208032703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 179.edn_alert.3208032703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/179.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/179.edn_genbits.3571065704 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 333257303 ps |
| CPU time | 2.77 seconds |
| Started | Oct 03 01:15:26 AM UTC 24 |
| Finished | Oct 03 01:15:30 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571065704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3571065704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/179.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_alert.2901597526 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 66136773 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 01:09:33 AM UTC 24 |
| Finished | Oct 03 01:09:37 AM UTC 24 |
| Peak memory | 232712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901597526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_alert.2901597526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_alert_test.34385802 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 24558460 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 01:09:37 AM UTC 24 |
| Finished | Oct 03 01:09:39 AM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34385802 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.34385802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_disable.1295962275 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 11603751 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:09:35 AM UTC 24 |
| Finished | Oct 03 01:09:37 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295962275 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1295962275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_err.760749620 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 46456214 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:09:33 AM UTC 24 |
| Finished | Oct 03 01:09:36 AM UTC 24 |
| Peak memory | 246676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760749620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 18.edn_err.760749620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_genbits.2839031507 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 37795878 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 01:09:32 AM UTC 24 |
| Finished | Oct 03 01:09:35 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839031507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2839031507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_intr.864856395 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 34332986 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:09:33 AM UTC 24 |
| Finished | Oct 03 01:09:36 AM UTC 24 |
| Peak memory | 238344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864856395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.864856395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_smoke.1790628009 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 22811431 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:09:31 AM UTC 24 |
| Finished | Oct 03 01:09:34 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790628009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_smoke.1790628009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/18.edn_stress_all.406758570 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 511773065 ps |
| CPU time | 7.38 seconds |
| Started | Oct 03 01:09:32 AM UTC 24 |
| Finished | Oct 03 01:09:41 AM UTC 24 |
| Peak memory | 228032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406758570 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.406758570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/18.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/180.edn_alert.399037669 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 79133182 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:15:27 AM UTC 24 |
| Finished | Oct 03 01:15:30 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399037669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 180.edn_alert.399037669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/180.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/180.edn_genbits.1154171248 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 55896606 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 01:15:27 AM UTC 24 |
| Finished | Oct 03 01:15:30 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154171248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1154171248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/180.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/181.edn_alert.281898021 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 30438780 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:15:28 AM UTC 24 |
| Finished | Oct 03 01:15:31 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281898021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 181.edn_alert.281898021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/181.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/181.edn_genbits.1499198924 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 36836477 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:15:27 AM UTC 24 |
| Finished | Oct 03 01:15:30 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499198924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1499198924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/181.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/182.edn_alert.4139661869 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 29174411 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 01:15:28 AM UTC 24 |
| Finished | Oct 03 01:15:31 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139661869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 182.edn_alert.4139661869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/182.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/182.edn_genbits.2957531541 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 37229693 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:15:28 AM UTC 24 |
| Finished | Oct 03 01:15:31 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957531541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2957531541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/182.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/183.edn_alert.2053512349 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 26608141 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:15:29 AM UTC 24 |
| Finished | Oct 03 01:15:32 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053512349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 183.edn_alert.2053512349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/183.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/183.edn_genbits.209411215 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 58879513 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:15:29 AM UTC 24 |
| Finished | Oct 03 01:15:31 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209411215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 183.edn_genbits.209411215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/183.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/184.edn_alert.1665290759 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 26933205 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:15:30 AM UTC 24 |
| Finished | Oct 03 01:15:32 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665290759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 184.edn_alert.1665290759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/184.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/184.edn_genbits.3617447820 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 327109085 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:15:30 AM UTC 24 |
| Finished | Oct 03 01:15:33 AM UTC 24 |
| Peak memory | 229180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617447820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3617447820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/184.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/185.edn_alert.4217203865 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 49242391 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:15:31 AM UTC 24 |
| Finished | Oct 03 01:15:34 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217203865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 185.edn_alert.4217203865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/185.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/185.edn_genbits.3511349555 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 74100391 ps |
| CPU time | 4.42 seconds |
| Started | Oct 03 01:15:30 AM UTC 24 |
| Finished | Oct 03 01:15:36 AM UTC 24 |
| Peak memory | 230224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511349555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3511349555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/185.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/186.edn_alert.2288317764 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 28272003 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:15:31 AM UTC 24 |
| Finished | Oct 03 01:15:34 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288317764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 186.edn_alert.2288317764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/186.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/186.edn_genbits.54248417 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 110651871 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:15:31 AM UTC 24 |
| Finished | Oct 03 01:15:34 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54248417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 186.edn_genbits.54248417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/186.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/187.edn_alert.2676825335 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 77132698 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:15:32 AM UTC 24 |
| Finished | Oct 03 01:15:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676825335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 187.edn_alert.2676825335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/187.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/187.edn_genbits.2506117713 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 53757464 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 01:15:31 AM UTC 24 |
| Finished | Oct 03 01:15:34 AM UTC 24 |
| Peak memory | 228100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506117713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2506117713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/187.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/188.edn_alert.4259012951 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 296319312 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:15:32 AM UTC 24 |
| Finished | Oct 03 01:15:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259012951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 188.edn_alert.4259012951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/188.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/188.edn_genbits.3996503164 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 37467079 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:32 AM UTC 24 |
| Finished | Oct 03 01:15:35 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996503164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3996503164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/188.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/189.edn_alert.3278213993 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 74099920 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:15:32 AM UTC 24 |
| Finished | Oct 03 01:15:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278213993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 189.edn_alert.3278213993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/189.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/189.edn_genbits.1563638403 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 70137937 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:15:32 AM UTC 24 |
| Finished | Oct 03 01:15:35 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563638403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1563638403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/189.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_alert.3659592688 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 61631920 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:09:38 AM UTC 24 |
| Finished | Oct 03 01:09:41 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659592688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_alert.3659592688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_alert_test.1957310105 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 26452707 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 01:09:40 AM UTC 24 |
| Finished | Oct 03 01:09:43 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957310105 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1957310105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_disable.2138638528 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 72274174 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:09:40 AM UTC 24 |
| Finished | Oct 03 01:09:43 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138638528 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2138638528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_err.2858854594 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 47656364 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 01:09:39 AM UTC 24 |
| Finished | Oct 03 01:09:42 AM UTC 24 |
| Peak memory | 242952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858854594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 19.edn_err.2858854594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_genbits.2714304776 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 39288492 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:09:37 AM UTC 24 |
| Finished | Oct 03 01:09:40 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714304776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2714304776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_smoke.3440474505 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 18284606 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:09:37 AM UTC 24 |
| Finished | Oct 03 01:09:39 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440474505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_smoke.3440474505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_stress_all.1388631994 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 229939914 ps |
| CPU time | 6.33 seconds |
| Started | Oct 03 01:09:37 AM UTC 24 |
| Finished | Oct 03 01:09:44 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388631994 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1388631994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.781887409 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7973805855 ps |
| CPU time | 40.16 seconds |
| Started | Oct 03 01:09:38 AM UTC 24 |
| Finished | Oct 03 01:10:20 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781887409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_ with_rand_reset.781887409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/190.edn_alert.2639154007 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 48840087 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:15:34 AM UTC 24 |
| Finished | Oct 03 01:15:36 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639154007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 190.edn_alert.2639154007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/190.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/190.edn_genbits.3684037929 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 51765154 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:15:32 AM UTC 24 |
| Finished | Oct 03 01:15:35 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684037929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3684037929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/190.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/191.edn_alert.470363324 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 73468667 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:15:35 AM UTC 24 |
| Finished | Oct 03 01:15:38 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470363324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 191.edn_alert.470363324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/191.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/191.edn_genbits.2460139100 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 56471341 ps |
| CPU time | 3.04 seconds |
| Started | Oct 03 01:15:34 AM UTC 24 |
| Finished | Oct 03 01:15:38 AM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460139100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2460139100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/191.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/192.edn_alert.4154140364 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 75106764 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:15:35 AM UTC 24 |
| Finished | Oct 03 01:15:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154140364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 192.edn_alert.4154140364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/192.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/192.edn_genbits.1939951844 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 65843398 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 01:15:35 AM UTC 24 |
| Finished | Oct 03 01:15:38 AM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939951844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1939951844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/192.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/193.edn_alert.495979770 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 89475282 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:39 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495979770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 193.edn_alert.495979770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/193.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/193.edn_genbits.2842348767 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 62868088 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:39 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842348767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2842348767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/193.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/194.edn_alert.3594288054 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 27332230 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:39 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594288054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 194.edn_alert.3594288054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/194.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/194.edn_genbits.2572887398 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 77531219 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:38 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572887398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2572887398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/194.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/195.edn_alert.1784487430 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 85993432 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:39 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784487430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 195.edn_alert.1784487430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/195.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/195.edn_genbits.2764218998 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 59688004 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:39 AM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764218998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2764218998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/195.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/196.edn_alert.4264245927 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 37248250 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:15:37 AM UTC 24 |
| Finished | Oct 03 01:15:40 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264245927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 196.edn_alert.4264245927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/196.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/196.edn_genbits.501573901 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 41046759 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 01:15:36 AM UTC 24 |
| Finished | Oct 03 01:15:39 AM UTC 24 |
| Peak memory | 230288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501573901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 196.edn_genbits.501573901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/196.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/197.edn_alert.706908374 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 28320647 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:15:38 AM UTC 24 |
| Finished | Oct 03 01:15:41 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706908374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 197.edn_alert.706908374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/197.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/197.edn_genbits.3755361928 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 73209294 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:15:37 AM UTC 24 |
| Finished | Oct 03 01:15:40 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755361928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3755361928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/197.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/198.edn_alert.2193615002 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 28304410 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 01:15:39 AM UTC 24 |
| Finished | Oct 03 01:15:41 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193615002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 198.edn_alert.2193615002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/198.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/198.edn_genbits.1679187606 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 134147870 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:15:39 AM UTC 24 |
| Finished | Oct 03 01:15:41 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679187606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1679187606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/198.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/199.edn_alert.4200333763 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 23286550 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:43 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200333763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 199.edn_alert.4200333763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/199.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/199.edn_genbits.3465168978 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 43939537 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:15:39 AM UTC 24 |
| Finished | Oct 03 01:15:41 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465168978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3465168978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/199.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_alert_test.4095739140 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 12646372 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 01:08:38 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095739140 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.4095739140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_disable.2172259655 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 41746831 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172259655 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2172259655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.671862064 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 101159800 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671862064 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.671862064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_err.2316181925 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 49254193 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:39 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316181925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.edn_err.2316181925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_genbits.1711600897 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 200390158 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 230244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711600897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1711600897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_intr.2666713169 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 55471333 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:40 AM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666713169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2666713169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/2.edn_smoke.1263675859 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 23213811 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:08:37 AM UTC 24 |
| Finished | Oct 03 01:08:39 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263675859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_smoke.1263675859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/2.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_alert.2578809083 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 46843383 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:09:44 AM UTC 24 |
| Finished | Oct 03 01:09:47 AM UTC 24 |
| Peak memory | 231076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578809083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_alert.2578809083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_alert_test.1373365504 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 58124177 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:09:45 AM UTC 24 |
| Finished | Oct 03 01:09:47 AM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373365504 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1373365504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_disable.2152967141 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 187753407 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:09:45 AM UTC 24 |
| Finished | Oct 03 01:09:47 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152967141 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2152967141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.1550857492 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 97222011 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:09:45 AM UTC 24 |
| Finished | Oct 03 01:09:48 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550857492 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.1550857492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_err.2283951884 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 18030199 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:09:44 AM UTC 24 |
| Finished | Oct 03 01:09:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283951884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 20.edn_err.2283951884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_genbits.856321240 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 100713768 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:09:41 AM UTC 24 |
| Finished | Oct 03 01:09:44 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856321240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.edn_genbits.856321240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_intr.2880835655 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 22069711 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:09:43 AM UTC 24 |
| Finished | Oct 03 01:09:45 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880835655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2880835655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_smoke.3113160807 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 45832391 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:09:41 AM UTC 24 |
| Finished | Oct 03 01:09:44 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113160807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_smoke.3113160807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_stress_all.3271243589 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 480641524 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 01:09:42 AM UTC 24 |
| Finished | Oct 03 01:09:45 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271243589 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3271243589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.3155569204 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 7314331391 ps |
| CPU time | 97.33 seconds |
| Started | Oct 03 01:09:43 AM UTC 24 |
| Finished | Oct 03 01:11:22 AM UTC 24 |
| Peak memory | 230436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155569204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all _with_rand_reset.3155569204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/200.edn_genbits.2373575489 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 40198144 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:43 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373575489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2373575489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/200.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/201.edn_genbits.764867291 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 88974957 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:43 AM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764867291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 201.edn_genbits.764867291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/201.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/202.edn_genbits.3043985786 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 39033916 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:43 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043985786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3043985786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/202.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/203.edn_genbits.2725967849 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 36954001 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:43 AM UTC 24 |
| Peak memory | 232332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725967849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2725967849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/203.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/204.edn_genbits.2735787156 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 178154524 ps |
| CPU time | 4.4 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:45 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735787156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2735787156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/204.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/205.edn_genbits.3314249825 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 46897670 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 01:15:40 AM UTC 24 |
| Finished | Oct 03 01:15:44 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314249825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3314249825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/205.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/206.edn_genbits.3662494071 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 92963448 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:15:41 AM UTC 24 |
| Finished | Oct 03 01:15:44 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662494071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3662494071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/206.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/207.edn_genbits.4077018086 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 288881566 ps |
| CPU time | 6.39 seconds |
| Started | Oct 03 01:15:41 AM UTC 24 |
| Finished | Oct 03 01:15:49 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077018086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.4077018086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/207.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/208.edn_genbits.3033901755 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 109722931 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 01:15:42 AM UTC 24 |
| Finished | Oct 03 01:15:45 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033901755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3033901755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/208.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/209.edn_genbits.431884198 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 135476547 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:15:42 AM UTC 24 |
| Finished | Oct 03 01:15:45 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431884198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 209.edn_genbits.431884198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/209.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_alert.137920316 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 23337931 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:09:48 AM UTC 24 |
| Finished | Oct 03 01:09:51 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137920316 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 21.edn_alert.137920316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_alert_test.1509517962 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 41413258 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:09:50 AM UTC 24 |
| Finished | Oct 03 01:09:52 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509517962 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1509517962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.3839279443 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 29667740 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:09:49 AM UTC 24 |
| Finished | Oct 03 01:09:51 AM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839279443 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.3839279443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_err.1055386324 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 84130044 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:09:48 AM UTC 24 |
| Finished | Oct 03 01:09:51 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055386324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 21.edn_err.1055386324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_genbits.4161502344 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 43996436 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 01:09:46 AM UTC 24 |
| Finished | Oct 03 01:09:49 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161502344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4161502344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_intr.2282677341 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 31626205 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 01:09:47 AM UTC 24 |
| Finished | Oct 03 01:09:49 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282677341 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2282677341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_smoke.1385331594 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 30060775 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:09:45 AM UTC 24 |
| Finished | Oct 03 01:09:47 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385331594 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.edn_smoke.1385331594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/21.edn_stress_all.3551498898 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 255522401 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 01:09:46 AM UTC 24 |
| Finished | Oct 03 01:09:50 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551498898 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3551498898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/21.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/210.edn_genbits.3287531171 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 34821423 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:15:42 AM UTC 24 |
| Finished | Oct 03 01:15:45 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287531171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3287531171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/210.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/211.edn_genbits.135889138 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 46651337 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 01:15:42 AM UTC 24 |
| Finished | Oct 03 01:15:46 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135889138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 211.edn_genbits.135889138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/211.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/212.edn_genbits.795746651 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 45886724 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 01:15:44 AM UTC 24 |
| Finished | Oct 03 01:15:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795746651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 212.edn_genbits.795746651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/212.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/213.edn_genbits.1598699614 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 88981472 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:15:44 AM UTC 24 |
| Finished | Oct 03 01:15:47 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598699614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1598699614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/213.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/214.edn_genbits.2314731510 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 31410854 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:15:44 AM UTC 24 |
| Finished | Oct 03 01:15:47 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314731510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2314731510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/214.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/215.edn_genbits.759338462 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 47515642 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 01:15:44 AM UTC 24 |
| Finished | Oct 03 01:15:47 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759338462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 215.edn_genbits.759338462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/215.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/216.edn_genbits.2001375252 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 55242103 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 01:15:44 AM UTC 24 |
| Finished | Oct 03 01:15:47 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001375252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2001375252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/216.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/218.edn_genbits.677282666 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 62185815 ps |
| CPU time | 3.22 seconds |
| Started | Oct 03 01:15:45 AM UTC 24 |
| Finished | Oct 03 01:15:49 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677282666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 218.edn_genbits.677282666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/218.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/219.edn_genbits.817482732 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 71454899 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 01:15:46 AM UTC 24 |
| Finished | Oct 03 01:15:49 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817482732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 219.edn_genbits.817482732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/219.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_alert.900883491 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 176389320 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:09:52 AM UTC 24 |
| Finished | Oct 03 01:09:55 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900883491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 22.edn_alert.900883491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_alert_test.58972834 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 18710706 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:09:55 AM UTC 24 |
| Finished | Oct 03 01:09:58 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58972834 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.58972834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.3109082388 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 48944113 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:09:54 AM UTC 24 |
| Finished | Oct 03 01:09:57 AM UTC 24 |
| Peak memory | 227096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109082388 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.3109082388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_err.3437135258 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 67586475 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:09:52 AM UTC 24 |
| Finished | Oct 03 01:09:55 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437135258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 22.edn_err.3437135258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_genbits.465178846 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 52005905 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 01:09:51 AM UTC 24 |
| Finished | Oct 03 01:09:54 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465178846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.edn_genbits.465178846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_smoke.3860107018 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 17407448 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:09:51 AM UTC 24 |
| Finished | Oct 03 01:09:53 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860107018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.edn_smoke.3860107018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/22.edn_stress_all.447097090 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 169515697 ps |
| CPU time | 4.9 seconds |
| Started | Oct 03 01:09:51 AM UTC 24 |
| Finished | Oct 03 01:09:57 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447097090 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.447097090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/22.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/220.edn_genbits.868908953 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 33666218 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:15:46 AM UTC 24 |
| Finished | Oct 03 01:15:49 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868908953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 220.edn_genbits.868908953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/220.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/221.edn_genbits.99322096 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 43287300 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 01:15:46 AM UTC 24 |
| Finished | Oct 03 01:15:49 AM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99322096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 221.edn_genbits.99322096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/221.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/222.edn_genbits.1905350099 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 316001446 ps |
| CPU time | 3.55 seconds |
| Started | Oct 03 01:15:46 AM UTC 24 |
| Finished | Oct 03 01:15:51 AM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905350099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1905350099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/222.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/223.edn_genbits.3639809168 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 34120128 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 01:15:47 AM UTC 24 |
| Finished | Oct 03 01:15:50 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639809168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3639809168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/223.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/224.edn_genbits.817205259 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 76950354 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:15:47 AM UTC 24 |
| Finished | Oct 03 01:15:50 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817205259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 224.edn_genbits.817205259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/224.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/225.edn_genbits.1726737789 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 132651983 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 01:15:47 AM UTC 24 |
| Finished | Oct 03 01:15:50 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726737789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1726737789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/225.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/226.edn_genbits.3441708820 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 83533746 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 01:15:47 AM UTC 24 |
| Finished | Oct 03 01:15:51 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441708820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3441708820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/226.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/227.edn_genbits.1560054705 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 73415932 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:15:49 AM UTC 24 |
| Finished | Oct 03 01:15:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560054705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1560054705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/227.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/228.edn_genbits.4173023976 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 61128745 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 01:15:49 AM UTC 24 |
| Finished | Oct 03 01:15:52 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173023976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4173023976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/228.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/229.edn_genbits.3287834070 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 176082556 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:15:49 AM UTC 24 |
| Finished | Oct 03 01:15:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287834070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3287834070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/229.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_alert.2660978002 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 26599307 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:09:57 AM UTC 24 |
| Finished | Oct 03 01:10:00 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660978002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.edn_alert.2660978002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_alert_test.374105057 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 23459517 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:09:58 AM UTC 24 |
| Finished | Oct 03 01:10:01 AM UTC 24 |
| Peak memory | 227276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374105057 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.374105057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_disable.3693178682 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 21419638 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 01:09:58 AM UTC 24 |
| Finished | Oct 03 01:10:00 AM UTC 24 |
| Peak memory | 216956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693178682 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3693178682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.2947244641 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 54944961 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:09:58 AM UTC 24 |
| Finished | Oct 03 01:10:01 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947244641 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.2947244641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_err.2375408915 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 28530128 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:09:57 AM UTC 24 |
| Finished | Oct 03 01:10:00 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375408915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 23.edn_err.2375408915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_genbits.2798521401 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 92043345 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 01:09:55 AM UTC 24 |
| Finished | Oct 03 01:09:59 AM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798521401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2798521401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_intr.1780132280 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 28855408 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:09:57 AM UTC 24 |
| Finished | Oct 03 01:10:00 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780132280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1780132280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_smoke.845285799 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 52746778 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:09:55 AM UTC 24 |
| Finished | Oct 03 01:09:58 AM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845285799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 23.edn_smoke.845285799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_stress_all.3302252047 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1930731545 ps |
| CPU time | 4.99 seconds |
| Started | Oct 03 01:09:56 AM UTC 24 |
| Finished | Oct 03 01:10:02 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302252047 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3302252047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.184189291 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 4929241635 ps |
| CPU time | 118.32 seconds |
| Started | Oct 03 01:09:56 AM UTC 24 |
| Finished | Oct 03 01:11:56 AM UTC 24 |
| Peak memory | 232360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184189291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_ with_rand_reset.184189291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/230.edn_genbits.2426207229 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 44842979 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 01:15:50 AM UTC 24 |
| Finished | Oct 03 01:15:53 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426207229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2426207229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/230.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/231.edn_genbits.372823786 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 74406495 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 01:15:50 AM UTC 24 |
| Finished | Oct 03 01:15:54 AM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372823786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 231.edn_genbits.372823786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/231.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/232.edn_genbits.1615725427 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 54896235 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:15:50 AM UTC 24 |
| Finished | Oct 03 01:15:53 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615725427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1615725427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/232.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/233.edn_genbits.2387275627 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 67968468 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:15:50 AM UTC 24 |
| Finished | Oct 03 01:15:53 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387275627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2387275627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/233.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/234.edn_genbits.1190926401 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 239042153 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:50 AM UTC 24 |
| Finished | Oct 03 01:15:53 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190926401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1190926401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/234.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/235.edn_genbits.1103056554 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 57808461 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:15:51 AM UTC 24 |
| Finished | Oct 03 01:15:53 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103056554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1103056554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/235.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/236.edn_genbits.3831735270 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 156341527 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:15:51 AM UTC 24 |
| Finished | Oct 03 01:15:54 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831735270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3831735270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/236.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/237.edn_genbits.1409302854 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 28837953 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:15:51 AM UTC 24 |
| Finished | Oct 03 01:15:54 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409302854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1409302854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/237.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/238.edn_genbits.1092660001 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 198019829 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 01:15:51 AM UTC 24 |
| Finished | Oct 03 01:15:56 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092660001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1092660001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/238.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/239.edn_genbits.3583097976 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 55364347 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 01:15:51 AM UTC 24 |
| Finished | Oct 03 01:15:54 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583097976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3583097976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/239.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_alert.3129930674 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 74858856 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:10:02 AM UTC 24 |
| Finished | Oct 03 01:10:05 AM UTC 24 |
| Peak memory | 231004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129930674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.edn_alert.3129930674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_alert_test.1178539678 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 57524418 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 01:10:02 AM UTC 24 |
| Finished | Oct 03 01:10:04 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178539678 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1178539678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_disable.3574886408 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 18317698 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 01:10:02 AM UTC 24 |
| Finished | Oct 03 01:10:04 AM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574886408 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3574886408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.3230522532 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 46152815 ps |
| CPU time | 2.21 seconds |
| Started | Oct 03 01:10:02 AM UTC 24 |
| Finished | Oct 03 01:10:05 AM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230522532 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3230522532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_err.996748629 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 23296085 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:10:02 AM UTC 24 |
| Finished | Oct 03 01:10:04 AM UTC 24 |
| Peak memory | 238344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996748629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 24.edn_err.996748629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_genbits.3621569537 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 30299244 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:09:59 AM UTC 24 |
| Finished | Oct 03 01:10:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621569537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3621569537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_intr.1952593445 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 62518840 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:10:01 AM UTC 24 |
| Finished | Oct 03 01:10:03 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952593445 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1952593445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_smoke.4223759207 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 31739051 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:09:58 AM UTC 24 |
| Finished | Oct 03 01:10:01 AM UTC 24 |
| Peak memory | 226920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223759207 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.edn_smoke.4223759207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/24.edn_stress_all.3805849872 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 321508157 ps |
| CPU time | 7.24 seconds |
| Started | Oct 03 01:09:59 AM UTC 24 |
| Finished | Oct 03 01:10:08 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805849872 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3805849872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/24.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/240.edn_genbits.4139652207 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 48192246 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 01:15:52 AM UTC 24 |
| Finished | Oct 03 01:15:56 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139652207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4139652207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/240.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/241.edn_genbits.2089399589 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 181754365 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:15:52 AM UTC 24 |
| Finished | Oct 03 01:15:55 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089399589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2089399589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/241.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/242.edn_genbits.1798676 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 60033353 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:15:52 AM UTC 24 |
| Finished | Oct 03 01:15:55 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_ genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 242.edn_genbits.1798676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/242.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/243.edn_genbits.1470040011 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 52121600 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 01:15:54 AM UTC 24 |
| Finished | Oct 03 01:15:57 AM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470040011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1470040011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/243.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/244.edn_genbits.2219150782 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 36875278 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:15:54 AM UTC 24 |
| Finished | Oct 03 01:15:56 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219150782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2219150782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/244.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/245.edn_genbits.2491578095 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 35944886 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:15:54 AM UTC 24 |
| Finished | Oct 03 01:15:57 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491578095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2491578095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/245.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/246.edn_genbits.1870561877 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 53710816 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:15:54 AM UTC 24 |
| Finished | Oct 03 01:15:56 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870561877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1870561877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/246.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/247.edn_genbits.1611874043 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 86425672 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 01:15:55 AM UTC 24 |
| Finished | Oct 03 01:15:58 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611874043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1611874043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/247.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/248.edn_genbits.19582619 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 55336927 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:15:55 AM UTC 24 |
| Finished | Oct 03 01:15:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19582619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 248.edn_genbits.19582619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/248.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/249.edn_genbits.3830160650 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 111188788 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 01:15:55 AM UTC 24 |
| Finished | Oct 03 01:15:58 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830160650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3830160650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/249.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_alert.2485196540 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 32292195 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:10:05 AM UTC 24 |
| Finished | Oct 03 01:10:08 AM UTC 24 |
| Peak memory | 228964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485196540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.edn_alert.2485196540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_alert_test.800389236 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 30298713 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:10:08 AM UTC 24 |
| Finished | Oct 03 01:10:10 AM UTC 24 |
| Peak memory | 216928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800389236 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.800389236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_disable.1535307637 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 11118414 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:10:06 AM UTC 24 |
| Finished | Oct 03 01:10:09 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535307637 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1535307637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.593713013 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 27962565 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:10:06 AM UTC 24 |
| Finished | Oct 03 01:10:09 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593713013 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.593713013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_err.1918151845 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 75326111 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:10:05 AM UTC 24 |
| Finished | Oct 03 01:10:08 AM UTC 24 |
| Peak memory | 242856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918151845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 25.edn_err.1918151845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_intr.4105268130 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 22567606 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 01:10:05 AM UTC 24 |
| Finished | Oct 03 01:10:08 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105268130 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.4105268130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_smoke.2815145640 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 29984208 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:10:03 AM UTC 24 |
| Finished | Oct 03 01:10:06 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815145640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.edn_smoke.2815145640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/25.edn_stress_all.1505439018 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 565833705 ps |
| CPU time | 4.91 seconds |
| Started | Oct 03 01:10:04 AM UTC 24 |
| Finished | Oct 03 01:10:10 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505439018 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1505439018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/25.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/250.edn_genbits.3573097565 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 62460248 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:15:55 AM UTC 24 |
| Finished | Oct 03 01:15:57 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573097565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3573097565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/250.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/251.edn_genbits.2485137090 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 16120196 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 01:15:55 AM UTC 24 |
| Finished | Oct 03 01:15:57 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485137090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2485137090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/251.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/252.edn_genbits.4082494310 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 110130823 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 01:15:56 AM UTC 24 |
| Finished | Oct 03 01:15:59 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082494310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4082494310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/252.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/253.edn_genbits.1658851489 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 90988855 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:15:56 AM UTC 24 |
| Finished | Oct 03 01:15:59 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658851489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1658851489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/253.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/254.edn_genbits.2047637476 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 102363800 ps |
| CPU time | 3.26 seconds |
| Started | Oct 03 01:15:56 AM UTC 24 |
| Finished | Oct 03 01:16:00 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047637476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2047637476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/254.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/256.edn_genbits.3750858768 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 60796295 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:15:57 AM UTC 24 |
| Finished | Oct 03 01:16:00 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750858768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3750858768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/256.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/257.edn_genbits.3865565992 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 67165819 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:15:57 AM UTC 24 |
| Finished | Oct 03 01:16:00 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865565992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3865565992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/257.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/258.edn_genbits.2537948143 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 51243270 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 01:15:57 AM UTC 24 |
| Finished | Oct 03 01:16:01 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537948143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2537948143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/258.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/259.edn_genbits.1560433470 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 51894731 ps |
| CPU time | 3.12 seconds |
| Started | Oct 03 01:15:58 AM UTC 24 |
| Finished | Oct 03 01:16:02 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560433470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1560433470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/259.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_alert_test.557288423 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 18315064 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:10:13 AM UTC 24 |
| Finished | Oct 03 01:10:16 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557288423 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.557288423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.2664013390 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 68505157 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 01:10:12 AM UTC 24 |
| Finished | Oct 03 01:10:15 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664013390 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.2664013390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_err.4227663788 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 23330496 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:10:11 AM UTC 24 |
| Finished | Oct 03 01:10:14 AM UTC 24 |
| Peak memory | 238096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227663788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 26.edn_err.4227663788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_genbits.4059868539 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 45659771 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 01:10:09 AM UTC 24 |
| Finished | Oct 03 01:10:12 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059868539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4059868539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_intr.439922458 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 21211185 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:10:10 AM UTC 24 |
| Finished | Oct 03 01:10:13 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439922458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.439922458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_smoke.360294259 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 84684963 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:10:09 AM UTC 24 |
| Finished | Oct 03 01:10:11 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360294259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 26.edn_smoke.360294259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/26.edn_stress_all.1495212585 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 72605092 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:10:09 AM UTC 24 |
| Finished | Oct 03 01:10:12 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495212585 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1495212585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/26.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/260.edn_genbits.1428202274 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 47137561 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:15:58 AM UTC 24 |
| Finished | Oct 03 01:16:00 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428202274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1428202274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/260.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/261.edn_genbits.935139361 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 276262210 ps |
| CPU time | 4.17 seconds |
| Started | Oct 03 01:15:59 AM UTC 24 |
| Finished | Oct 03 01:16:04 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935139361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 261.edn_genbits.935139361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/261.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/262.edn_genbits.1692857422 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 137831788 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:15:59 AM UTC 24 |
| Finished | Oct 03 01:16:02 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692857422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1692857422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/262.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/263.edn_genbits.1956420830 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 93195471 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:15:59 AM UTC 24 |
| Finished | Oct 03 01:16:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956420830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1956420830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/263.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/264.edn_genbits.3846089493 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 103831750 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:15:59 AM UTC 24 |
| Finished | Oct 03 01:16:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846089493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3846089493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/264.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/265.edn_genbits.3350192513 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 213513610 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:15:59 AM UTC 24 |
| Finished | Oct 03 01:16:02 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350192513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3350192513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/265.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/266.edn_genbits.3960990121 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 47927474 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 01:16:00 AM UTC 24 |
| Finished | Oct 03 01:16:04 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960990121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3960990121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/266.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/267.edn_genbits.2341930376 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 23613596 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:16:00 AM UTC 24 |
| Finished | Oct 03 01:16:03 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341930376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2341930376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/267.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/268.edn_genbits.1216847575 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 45421206 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 01:16:00 AM UTC 24 |
| Finished | Oct 03 01:16:04 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216847575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1216847575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/268.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/269.edn_genbits.7384956 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 42359830 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 01:16:00 AM UTC 24 |
| Finished | Oct 03 01:16:04 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7384956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_ genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 269.edn_genbits.7384956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/269.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_alert.1410253376 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 46592997 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:10:16 AM UTC 24 |
| Finished | Oct 03 01:10:19 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410253376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.edn_alert.1410253376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_alert_test.3215955353 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 11861824 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:10:19 AM UTC 24 |
| Finished | Oct 03 01:10:21 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215955353 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3215955353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_disable.3823948620 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 67052028 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:10:17 AM UTC 24 |
| Finished | Oct 03 01:10:19 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823948620 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3823948620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1983040907 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 78572959 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:10:17 AM UTC 24 |
| Finished | Oct 03 01:10:20 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983040907 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1983040907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_err.2522022364 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 32779615 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:10:17 AM UTC 24 |
| Finished | Oct 03 01:10:20 AM UTC 24 |
| Peak memory | 238180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522022364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 27.edn_err.2522022364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_genbits.4243196220 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 67605146 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 01:10:13 AM UTC 24 |
| Finished | Oct 03 01:10:16 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243196220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4243196220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_smoke.1292679011 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 37465680 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:10:13 AM UTC 24 |
| Finished | Oct 03 01:10:16 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292679011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.edn_smoke.1292679011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_stress_all.274752087 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 366638967 ps |
| CPU time | 9.22 seconds |
| Started | Oct 03 01:10:13 AM UTC 24 |
| Finished | Oct 03 01:10:24 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274752087 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.274752087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.1770110615 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 43001476214 ps |
| CPU time | 140.73 seconds |
| Started | Oct 03 01:10:15 AM UTC 24 |
| Finished | Oct 03 01:12:38 AM UTC 24 |
| Peak memory | 230428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770110615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all _with_rand_reset.1770110615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/270.edn_genbits.49786680 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 102976437 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:16:01 AM UTC 24 |
| Finished | Oct 03 01:16:04 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49786680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 270.edn_genbits.49786680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/270.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/271.edn_genbits.3398290497 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 95419544 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 01:16:02 AM UTC 24 |
| Finished | Oct 03 01:16:05 AM UTC 24 |
| Peak memory | 230232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398290497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3398290497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/271.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/272.edn_genbits.2802216034 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 41328653 ps |
| CPU time | 2.42 seconds |
| Started | Oct 03 01:16:02 AM UTC 24 |
| Finished | Oct 03 01:16:05 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802216034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2802216034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/272.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/273.edn_genbits.1891503546 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 116832976 ps |
| CPU time | 2.67 seconds |
| Started | Oct 03 01:16:02 AM UTC 24 |
| Finished | Oct 03 01:16:05 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891503546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1891503546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/273.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/274.edn_genbits.1332163994 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 188122997 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:16:03 AM UTC 24 |
| Finished | Oct 03 01:16:06 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332163994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1332163994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/274.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/275.edn_genbits.1102886799 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 70945357 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:16:03 AM UTC 24 |
| Finished | Oct 03 01:16:05 AM UTC 24 |
| Peak memory | 226960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102886799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1102886799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/275.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/276.edn_genbits.3684068163 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 84457439 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:16:03 AM UTC 24 |
| Finished | Oct 03 01:16:05 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684068163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3684068163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/276.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/277.edn_genbits.4084197854 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 81452994 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:16:03 AM UTC 24 |
| Finished | Oct 03 01:16:06 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084197854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4084197854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/277.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/278.edn_genbits.135324022 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 44756206 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 01:16:03 AM UTC 24 |
| Finished | Oct 03 01:16:06 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135324022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 278.edn_genbits.135324022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/278.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/279.edn_genbits.2627878154 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 128104727 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 01:16:04 AM UTC 24 |
| Finished | Oct 03 01:16:07 AM UTC 24 |
| Peak memory | 230208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627878154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2627878154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/279.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_alert.301979324 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 62120576 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:10:22 AM UTC 24 |
| Finished | Oct 03 01:10:25 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301979324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 28.edn_alert.301979324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_alert_test.3587916628 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 32743286 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 01:10:25 AM UTC 24 |
| Finished | Oct 03 01:10:27 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587916628 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3587916628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_disable.2391836680 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 135675844 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:10:24 AM UTC 24 |
| Finished | Oct 03 01:10:26 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391836680 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2391836680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.2692933247 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 58468770 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:10:25 AM UTC 24 |
| Finished | Oct 03 01:10:27 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692933247 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2692933247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_err.147752197 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 53752048 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 01:10:22 AM UTC 24 |
| Finished | Oct 03 01:10:25 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147752197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 28.edn_err.147752197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_intr.504882140 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 47892671 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:10:21 AM UTC 24 |
| Finished | Oct 03 01:10:24 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504882140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.504882140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_smoke.3939554348 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 17517376 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:10:19 AM UTC 24 |
| Finished | Oct 03 01:10:22 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939554348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.edn_smoke.3939554348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_stress_all.3440524572 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 267758001 ps |
| CPU time | 4.88 seconds |
| Started | Oct 03 01:10:20 AM UTC 24 |
| Finished | Oct 03 01:10:26 AM UTC 24 |
| Peak memory | 228100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440524572 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3440524572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.4274367947 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2460986853 ps |
| CPU time | 62.98 seconds |
| Started | Oct 03 01:10:21 AM UTC 24 |
| Finished | Oct 03 01:11:26 AM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274367947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all _with_rand_reset.4274367947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/280.edn_genbits.895104797 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5220699909 ps |
| CPU time | 99.68 seconds |
| Started | Oct 03 01:16:04 AM UTC 24 |
| Finished | Oct 03 01:17:46 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895104797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 280.edn_genbits.895104797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/280.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/281.edn_genbits.1170500097 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 51845389 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:16:04 AM UTC 24 |
| Finished | Oct 03 01:16:07 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170500097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1170500097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/281.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/282.edn_genbits.2989837260 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 64202988 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 01:16:05 AM UTC 24 |
| Finished | Oct 03 01:16:08 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989837260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2989837260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/282.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/283.edn_genbits.3476547145 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 45241495 ps |
| CPU time | 2.21 seconds |
| Started | Oct 03 01:16:05 AM UTC 24 |
| Finished | Oct 03 01:16:09 AM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476547145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3476547145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/283.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/284.edn_genbits.3073787932 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 53357586 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:16:05 AM UTC 24 |
| Finished | Oct 03 01:16:08 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073787932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3073787932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/284.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/285.edn_genbits.276313588 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 35672547 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:16:05 AM UTC 24 |
| Finished | Oct 03 01:16:08 AM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276313588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 285.edn_genbits.276313588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/285.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/286.edn_genbits.3966493100 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 21165180 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:16:07 AM UTC 24 |
| Finished | Oct 03 01:16:09 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966493100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3966493100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/286.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/287.edn_genbits.3977207767 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 70183345 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 01:16:07 AM UTC 24 |
| Finished | Oct 03 01:16:10 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977207767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3977207767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/287.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/288.edn_genbits.2802390288 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 33413551 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:16:07 AM UTC 24 |
| Finished | Oct 03 01:16:09 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802390288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2802390288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/288.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/289.edn_genbits.3475399810 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 135281757 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:16:07 AM UTC 24 |
| Finished | Oct 03 01:16:09 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475399810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3475399810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/289.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_alert.829039724 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 31505961 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:10:28 AM UTC 24 |
| Finished | Oct 03 01:10:31 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829039724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 29.edn_alert.829039724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_alert_test.1006138836 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 56951119 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:10:33 AM UTC 24 |
| Finished | Oct 03 01:10:35 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006138836 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1006138836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_disable.2800745133 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 19189110 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:10:31 AM UTC 24 |
| Finished | Oct 03 01:10:33 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800745133 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2800745133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.31519046 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 142965636 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 01:10:31 AM UTC 24 |
| Finished | Oct 03 01:10:34 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31519046 -assert nopostproc +UVM_TESTNAME=edn_disab le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.31519046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_err.2796412078 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 24754101 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 01:10:29 AM UTC 24 |
| Finished | Oct 03 01:10:32 AM UTC 24 |
| Peak memory | 238348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796412078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 29.edn_err.2796412078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_genbits.3429266205 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 83693193 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 01:10:26 AM UTC 24 |
| Finished | Oct 03 01:10:30 AM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429266205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3429266205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_intr.2725300367 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 55467397 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:10:28 AM UTC 24 |
| Finished | Oct 03 01:10:31 AM UTC 24 |
| Peak memory | 237180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725300367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2725300367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_smoke.4277023010 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 24750408 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:10:26 AM UTC 24 |
| Finished | Oct 03 01:10:28 AM UTC 24 |
| Peak memory | 226920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277023010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.edn_smoke.4277023010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_stress_all.2324982503 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 621299164 ps |
| CPU time | 8.29 seconds |
| Started | Oct 03 01:10:27 AM UTC 24 |
| Finished | Oct 03 01:10:36 AM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324982503 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2324982503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.2650643275 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2446784147 ps |
| CPU time | 41.97 seconds |
| Started | Oct 03 01:10:27 AM UTC 24 |
| Finished | Oct 03 01:11:11 AM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650643275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all _with_rand_reset.2650643275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/290.edn_genbits.4247211258 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 31897041 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 01:16:07 AM UTC 24 |
| Finished | Oct 03 01:16:10 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247211258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4247211258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/290.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/291.edn_genbits.1804859360 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 46618634 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:16:07 AM UTC 24 |
| Finished | Oct 03 01:16:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804859360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1804859360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/291.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/292.edn_genbits.2870231498 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 106390758 ps |
| CPU time | 3.41 seconds |
| Started | Oct 03 01:16:08 AM UTC 24 |
| Finished | Oct 03 01:16:12 AM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870231498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2870231498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/292.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/293.edn_genbits.60346575 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 51032894 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 01:16:08 AM UTC 24 |
| Finished | Oct 03 01:16:11 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60346575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 293.edn_genbits.60346575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/293.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/294.edn_genbits.2307477674 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 33934236 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:16:08 AM UTC 24 |
| Finished | Oct 03 01:16:11 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307477674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2307477674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/294.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/295.edn_genbits.2533031517 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 693226994 ps |
| CPU time | 7.62 seconds |
| Started | Oct 03 01:16:09 AM UTC 24 |
| Finished | Oct 03 01:16:18 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533031517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2533031517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/295.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/296.edn_genbits.51091685 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 53038427 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 01:16:09 AM UTC 24 |
| Finished | Oct 03 01:16:12 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51091685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 296.edn_genbits.51091685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/296.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/297.edn_genbits.1742600650 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 94943836 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:16:09 AM UTC 24 |
| Finished | Oct 03 01:16:12 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742600650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1742600650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/297.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/298.edn_genbits.328375711 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 43464797 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:16:09 AM UTC 24 |
| Finished | Oct 03 01:16:12 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328375711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 298.edn_genbits.328375711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/298.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/299.edn_genbits.2583414777 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 261493489 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:16:10 AM UTC 24 |
| Finished | Oct 03 01:16:13 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583414777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2583414777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/299.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_alert_test.2307873549 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 38282189 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:44 AM UTC 24 |
| Peak memory | 216992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307873549 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2307873549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_disable.3598675926 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11911045 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:43 AM UTC 24 |
| Peak memory | 226992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598675926 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3598675926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.267724104 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 23501803 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:44 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267724104 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.267724104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_genbits.4241252344 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 44104289 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:08:38 AM UTC 24 |
| Finished | Oct 03 01:08:41 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241252344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4241252344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_intr.4070468560 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 36062506 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 01:08:40 AM UTC 24 |
| Finished | Oct 03 01:08:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070468560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4070468560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_regwen.602898624 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 39549187 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 01:08:38 AM UTC 24 |
| Finished | Oct 03 01:08:41 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602898624 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_regwen.602898624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_sec_cm.3590944868 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 644878202 ps |
| CPU time | 10.39 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590944868 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3590944868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_smoke.2954372952 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 21932547 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:08:38 AM UTC 24 |
| Finished | Oct 03 01:08:41 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954372952 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_smoke.2954372952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_stress_all.1865939851 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 323708928 ps |
| CPU time | 4.79 seconds |
| Started | Oct 03 01:08:39 AM UTC 24 |
| Finished | Oct 03 01:08:44 AM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865939851 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1865939851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.4243890162 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12545588996 ps |
| CPU time | 46.87 seconds |
| Started | Oct 03 01:08:40 AM UTC 24 |
| Finished | Oct 03 01:09:28 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243890162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_ with_rand_reset.4243890162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_alert.602342898 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 97544960 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:10:36 AM UTC 24 |
| Finished | Oct 03 01:10:39 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602342898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 30.edn_alert.602342898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_alert_test.842493667 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 51258733 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:10:39 AM UTC 24 |
| Finished | Oct 03 01:10:42 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842493667 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.842493667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_disable.3674879587 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 24143903 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:10:37 AM UTC 24 |
| Finished | Oct 03 01:10:40 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674879587 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3674879587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.155841217 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 116405042 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:10:37 AM UTC 24 |
| Finished | Oct 03 01:10:40 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155841217 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.155841217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_err.3197707339 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 35578722 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:10:36 AM UTC 24 |
| Finished | Oct 03 01:10:38 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197707339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 30.edn_err.3197707339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_genbits.2182648290 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 28793448 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:10:33 AM UTC 24 |
| Finished | Oct 03 01:10:35 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182648290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2182648290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_intr.3164961390 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 29688866 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:10:36 AM UTC 24 |
| Finished | Oct 03 01:10:38 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164961390 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3164961390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_smoke.1003333028 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 47963959 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:10:33 AM UTC 24 |
| Finished | Oct 03 01:10:35 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003333028 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.edn_smoke.1003333028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/30.edn_stress_all.1368459355 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 279751498 ps |
| CPU time | 7.43 seconds |
| Started | Oct 03 01:10:34 AM UTC 24 |
| Finished | Oct 03 01:10:42 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368459355 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1368459355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/30.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_alert.1928605820 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 41480890 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:10:43 AM UTC 24 |
| Finished | Oct 03 01:10:45 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928605820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_alert.1928605820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_alert_test.1824513738 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 69759324 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:10:45 AM UTC 24 |
| Finished | Oct 03 01:10:47 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824513738 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1824513738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_disable.2357585878 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 12858959 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:10:44 AM UTC 24 |
| Finished | Oct 03 01:10:46 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357585878 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2357585878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.3720126988 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 35746412 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:10:44 AM UTC 24 |
| Finished | Oct 03 01:10:47 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720126988 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.3720126988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_err.377932573 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 87242805 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 01:10:43 AM UTC 24 |
| Finished | Oct 03 01:10:46 AM UTC 24 |
| Peak memory | 243256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377932573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 31.edn_err.377932573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_genbits.2323507696 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 50224326 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 01:10:39 AM UTC 24 |
| Finished | Oct 03 01:10:43 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323507696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2323507696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_intr.3924685446 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 30296981 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:10:43 AM UTC 24 |
| Finished | Oct 03 01:10:45 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924685446 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3924685446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_smoke.989808391 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 20334121 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:10:39 AM UTC 24 |
| Finished | Oct 03 01:10:42 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989808391 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 31.edn_smoke.989808391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_stress_all.3108240677 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 39980749 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:10:41 AM UTC 24 |
| Finished | Oct 03 01:10:43 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108240677 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3108240677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.2457154167 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 6927728629 ps |
| CPU time | 98.29 seconds |
| Started | Oct 03 01:10:41 AM UTC 24 |
| Finished | Oct 03 01:12:21 AM UTC 24 |
| Peak memory | 230280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457154167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all _with_rand_reset.2457154167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_alert.2183742439 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 24469422 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:10:49 AM UTC 24 |
| Finished | Oct 03 01:10:51 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183742439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_alert.2183742439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_alert_test.3969799283 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 15136728 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:10:52 AM UTC 24 |
| Finished | Oct 03 01:10:54 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969799283 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3969799283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_disable.3607598295 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 17083412 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:10:51 AM UTC 24 |
| Finished | Oct 03 01:10:53 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607598295 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3607598295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1615641552 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 187238067 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:10:52 AM UTC 24 |
| Finished | Oct 03 01:10:54 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615641552 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1615641552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_err.1843776451 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 18980457 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:10:50 AM UTC 24 |
| Finished | Oct 03 01:10:52 AM UTC 24 |
| Peak memory | 238280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843776451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 32.edn_err.1843776451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_genbits.3396087512 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 102282402 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 01:10:46 AM UTC 24 |
| Finished | Oct 03 01:10:51 AM UTC 24 |
| Peak memory | 232092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396087512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3396087512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_intr.3910689386 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 33723768 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:10:48 AM UTC 24 |
| Finished | Oct 03 01:10:50 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910689386 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3910689386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_smoke.2719836413 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 66999143 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:10:46 AM UTC 24 |
| Finished | Oct 03 01:10:49 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719836413 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_smoke.2719836413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/32.edn_stress_all.3447906264 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 517173901 ps |
| CPU time | 7.75 seconds |
| Started | Oct 03 01:10:46 AM UTC 24 |
| Finished | Oct 03 01:10:55 AM UTC 24 |
| Peak memory | 228064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447906264 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3447906264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/32.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_alert.4057308954 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 63300379 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:10:56 AM UTC 24 |
| Finished | Oct 03 01:10:59 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057308954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_alert.4057308954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_alert_test.2007029363 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 28862913 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 01:10:59 AM UTC 24 |
| Finished | Oct 03 01:11:01 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007029363 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2007029363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_disable.686135329 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 17817625 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 01:10:56 AM UTC 24 |
| Finished | Oct 03 01:10:59 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686135329 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.686135329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.872669455 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 32044416 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:10:58 AM UTC 24 |
| Finished | Oct 03 01:11:00 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872669455 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.872669455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_err.1075981374 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 37716163 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:10:56 AM UTC 24 |
| Finished | Oct 03 01:10:59 AM UTC 24 |
| Peak memory | 246620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075981374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 33.edn_err.1075981374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_genbits.2748994290 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 37572133 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:10:54 AM UTC 24 |
| Finished | Oct 03 01:10:57 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748994290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2748994290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_intr.3938936559 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 36863390 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 01:10:55 AM UTC 24 |
| Finished | Oct 03 01:10:57 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938936559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3938936559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_smoke.328990076 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 93712815 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:10:53 AM UTC 24 |
| Finished | Oct 03 01:10:55 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328990076 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 33.edn_smoke.328990076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/33.edn_stress_all.1261967614 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 139543248 ps |
| CPU time | 3.3 seconds |
| Started | Oct 03 01:10:55 AM UTC 24 |
| Finished | Oct 03 01:10:59 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261967614 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1261967614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/33.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_alert_test.688307764 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 17159300 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:11:04 AM UTC 24 |
| Finished | Oct 03 01:11:07 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688307764 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.688307764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_disable.3624019008 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 13544569 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:11:03 AM UTC 24 |
| Finished | Oct 03 01:11:05 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624019008 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3624019008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_err.4241713303 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 20712759 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:11:02 AM UTC 24 |
| Finished | Oct 03 01:11:05 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241713303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 34.edn_err.4241713303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_genbits.3640637935 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 115043765 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:11:00 AM UTC 24 |
| Finished | Oct 03 01:11:03 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640637935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3640637935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_intr.39493828 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 57594363 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 01:11:01 AM UTC 24 |
| Finished | Oct 03 01:11:03 AM UTC 24 |
| Peak memory | 237168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39493828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 34.edn_intr.39493828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_smoke.4203517769 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 31458402 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:11:00 AM UTC 24 |
| Finished | Oct 03 01:11:02 AM UTC 24 |
| Peak memory | 226920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203517769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_smoke.4203517769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/34.edn_stress_all.1651365710 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 187992480 ps |
| CPU time | 3.29 seconds |
| Started | Oct 03 01:11:00 AM UTC 24 |
| Finished | Oct 03 01:11:04 AM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651365710 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1651365710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/34.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_alert.3582955746 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 305744242 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 01:11:08 AM UTC 24 |
| Finished | Oct 03 01:11:11 AM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582955746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.edn_alert.3582955746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_alert_test.257336674 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 22149197 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:11:11 AM UTC 24 |
| Finished | Oct 03 01:11:13 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257336674 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.257336674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_disable.3208359482 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 30057247 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:11:09 AM UTC 24 |
| Finished | Oct 03 01:11:11 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208359482 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3208359482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.3933696873 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 59697053 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:11:10 AM UTC 24 |
| Finished | Oct 03 01:11:13 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933696873 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.3933696873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_err.2586122935 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 19101359 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:11:08 AM UTC 24 |
| Finished | Oct 03 01:11:10 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586122935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 35.edn_err.2586122935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_genbits.3341236358 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 32887749 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:11:05 AM UTC 24 |
| Finished | Oct 03 01:11:08 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341236358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3341236358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_intr.3262826205 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 21775642 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:11:07 AM UTC 24 |
| Finished | Oct 03 01:11:09 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262826205 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3262826205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_smoke.3840178059 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 45532745 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:11:04 AM UTC 24 |
| Finished | Oct 03 01:11:07 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840178059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.edn_smoke.3840178059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_stress_all.3515416205 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 302602879 ps |
| CPU time | 5.64 seconds |
| Started | Oct 03 01:11:05 AM UTC 24 |
| Finished | Oct 03 01:11:12 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515416205 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3515416205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.4174728244 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1957571851 ps |
| CPU time | 38.35 seconds |
| Started | Oct 03 01:11:07 AM UTC 24 |
| Finished | Oct 03 01:11:46 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174728244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all _with_rand_reset.4174728244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_alert.2168717460 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 90119714 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:11:14 AM UTC 24 |
| Finished | Oct 03 01:11:17 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168717460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.edn_alert.2168717460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_alert_test.732774625 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 228288756 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:11:18 AM UTC 24 |
| Finished | Oct 03 01:11:20 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732774625 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.732774625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_disable.830310668 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 18791611 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:11:15 AM UTC 24 |
| Finished | Oct 03 01:11:18 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830310668 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.830310668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.2239059532 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 39767297 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:11:17 AM UTC 24 |
| Finished | Oct 03 01:11:19 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239059532 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.2239059532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_err.3931389587 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 24958969 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:11:14 AM UTC 24 |
| Finished | Oct 03 01:11:17 AM UTC 24 |
| Peak memory | 246860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931389587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 36.edn_err.3931389587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_genbits.1910102379 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 74504209 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:11:12 AM UTC 24 |
| Finished | Oct 03 01:11:15 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910102379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1910102379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_intr.775274544 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 40763825 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:11:13 AM UTC 24 |
| Finished | Oct 03 01:11:16 AM UTC 24 |
| Peak memory | 238224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775274544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.775274544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_smoke.169994143 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 33138832 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:11:11 AM UTC 24 |
| Finished | Oct 03 01:11:13 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169994143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 36.edn_smoke.169994143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/36.edn_stress_all.400455310 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3965795488 ps |
| CPU time | 6.78 seconds |
| Started | Oct 03 01:11:12 AM UTC 24 |
| Finished | Oct 03 01:11:20 AM UTC 24 |
| Peak memory | 228112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400455310 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.400455310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/36.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_alert.2074961119 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 49315994 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:11:21 AM UTC 24 |
| Finished | Oct 03 01:11:24 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074961119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.edn_alert.2074961119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_alert_test.3939244304 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 102119469 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 01:11:25 AM UTC 24 |
| Finished | Oct 03 01:11:28 AM UTC 24 |
| Peak memory | 216372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939244304 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3939244304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_disable.1355570706 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 60942926 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:11:23 AM UTC 24 |
| Finished | Oct 03 01:11:26 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355570706 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1355570706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.3770596308 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 61234982 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:11:24 AM UTC 24 |
| Finished | Oct 03 01:11:27 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770596308 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.3770596308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_err.1150285882 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 19640527 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:11:22 AM UTC 24 |
| Finished | Oct 03 01:11:25 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150285882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 37.edn_err.1150285882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_genbits.1856987574 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 38609572 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:11:19 AM UTC 24 |
| Finished | Oct 03 01:11:22 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856987574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1856987574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_intr.2068534407 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 31661598 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:11:21 AM UTC 24 |
| Finished | Oct 03 01:11:23 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068534407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2068534407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_smoke.447952252 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 15343110 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:11:18 AM UTC 24 |
| Finished | Oct 03 01:11:20 AM UTC 24 |
| Peak memory | 226912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447952252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 37.edn_smoke.447952252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/37.edn_stress_all.650368996 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 289404866 ps |
| CPU time | 7.31 seconds |
| Started | Oct 03 01:11:20 AM UTC 24 |
| Finished | Oct 03 01:11:28 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650368996 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.650368996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/37.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_alert.3911676349 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 28644366 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:11:29 AM UTC 24 |
| Finished | Oct 03 01:11:32 AM UTC 24 |
| Peak memory | 231076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911676349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_alert.3911676349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_alert_test.2708999426 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 27069538 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:11:31 AM UTC 24 |
| Finished | Oct 03 01:11:33 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708999426 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2708999426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.145921862 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 61502699 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:11:30 AM UTC 24 |
| Finished | Oct 03 01:11:33 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145921862 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.145921862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_err.628793457 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 25726435 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:11:29 AM UTC 24 |
| Finished | Oct 03 01:11:31 AM UTC 24 |
| Peak memory | 238224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628793457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 38.edn_err.628793457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_genbits.4063269024 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 252207403 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:11:26 AM UTC 24 |
| Finished | Oct 03 01:11:29 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063269024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4063269024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_intr.2026565892 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 26614081 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:11:28 AM UTC 24 |
| Finished | Oct 03 01:11:31 AM UTC 24 |
| Peak memory | 237368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026565892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2026565892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_smoke.2318935918 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 24925676 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:11:25 AM UTC 24 |
| Finished | Oct 03 01:11:28 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318935918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_smoke.2318935918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_stress_all.2973296422 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 683926343 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 01:11:27 AM UTC 24 |
| Finished | Oct 03 01:11:31 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973296422 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2973296422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.3164013952 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 10172227347 ps |
| CPU time | 73.05 seconds |
| Started | Oct 03 01:11:27 AM UTC 24 |
| Finished | Oct 03 01:12:41 AM UTC 24 |
| Peak memory | 234388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164013952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all _with_rand_reset.3164013952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_alert.4129960645 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 65487818 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:11:34 AM UTC 24 |
| Finished | Oct 03 01:11:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129960645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_alert.4129960645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_alert_test.490871437 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 40063222 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:11:38 AM UTC 24 |
| Finished | Oct 03 01:11:40 AM UTC 24 |
| Peak memory | 227360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490871437 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.490871437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_disable.3713373756 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 12253037 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:11:37 AM UTC 24 |
| Finished | Oct 03 01:11:39 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713373756 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3713373756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.114563886 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 43427219 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:11:37 AM UTC 24 |
| Finished | Oct 03 01:11:39 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114563886 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.114563886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_err.1224580226 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 19588457 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:11:35 AM UTC 24 |
| Finished | Oct 03 01:11:39 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224580226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 39.edn_err.1224580226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_genbits.2490965139 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 34060654 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 01:11:32 AM UTC 24 |
| Finished | Oct 03 01:11:35 AM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490965139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2490965139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_intr.2232494434 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 25240637 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:11:33 AM UTC 24 |
| Finished | Oct 03 01:11:36 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232494434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2232494434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_smoke.2761514551 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 39210564 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 01:11:32 AM UTC 24 |
| Finished | Oct 03 01:11:34 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761514551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_smoke.2761514551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_stress_all.3836579193 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 243419957 ps |
| CPU time | 6.7 seconds |
| Started | Oct 03 01:11:32 AM UTC 24 |
| Finished | Oct 03 01:11:40 AM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836579193 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3836579193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.3480331678 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2736137986 ps |
| CPU time | 88.55 seconds |
| Started | Oct 03 01:11:32 AM UTC 24 |
| Finished | Oct 03 01:13:03 AM UTC 24 |
| Peak memory | 230432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480331678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all _with_rand_reset.3480331678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_alert.2335376573 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 25064259 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:45 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335376573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_alert.2335376573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_alert_test.1789863151 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 121177276 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:08:45 AM UTC 24 |
| Finished | Oct 03 01:08:47 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789863151 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1789863151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_err.3591200454 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 23460268 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:45 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591200454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.edn_err.3591200454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_genbits.786852120 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 44527988 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:45 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786852120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.edn_genbits.786852120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_intr.3657413670 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 24169538 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:45 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657413670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3657413670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_regwen.1747481683 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 48525179 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:45 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747481683 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.edn_regwen.1747481683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_sec_cm.3038830954 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 845140103 ps |
| CPU time | 4.65 seconds |
| Started | Oct 03 01:08:44 AM UTC 24 |
| Finished | Oct 03 01:08:49 AM UTC 24 |
| Peak memory | 258744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038830954 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3038830954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_smoke.1051396785 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 110741524 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 01:08:41 AM UTC 24 |
| Finished | Oct 03 01:08:43 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051396785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_smoke.1051396785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_stress_all.2612582338 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 190006463 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:08:47 AM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612582338 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2612582338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.1658684428 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2519980977 ps |
| CPU time | 71.2 seconds |
| Started | Oct 03 01:08:42 AM UTC 24 |
| Finished | Oct 03 01:09:55 AM UTC 24 |
| Peak memory | 232532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658684428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_ with_rand_reset.1658684428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_alert.792078771 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 27113518 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:11:43 AM UTC 24 |
| Finished | Oct 03 01:11:46 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792078771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 40.edn_alert.792078771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_alert_test.4214423889 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 24059493 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:11:47 AM UTC 24 |
| Finished | Oct 03 01:11:50 AM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214423889 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.4214423889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_disable.1548955563 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 13735469 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:11:44 AM UTC 24 |
| Finished | Oct 03 01:11:47 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548955563 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1548955563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.860466512 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 183785089 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:11:46 AM UTC 24 |
| Finished | Oct 03 01:11:49 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860466512 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.860466512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_err.1117766678 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 29115841 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:11:43 AM UTC 24 |
| Finished | Oct 03 01:11:46 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117766678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 40.edn_err.1117766678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_genbits.526496874 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 62987614 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:11:40 AM UTC 24 |
| Finished | Oct 03 01:11:43 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526496874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.edn_genbits.526496874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_intr.955207958 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 21024448 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 01:11:41 AM UTC 24 |
| Finished | Oct 03 01:11:44 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955207958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.955207958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_smoke.1732634274 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 18982964 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:11:40 AM UTC 24 |
| Finished | Oct 03 01:11:43 AM UTC 24 |
| Peak memory | 226920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732634274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.edn_smoke.1732634274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_stress_all.2936416956 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 203247029 ps |
| CPU time | 5.91 seconds |
| Started | Oct 03 01:11:41 AM UTC 24 |
| Finished | Oct 03 01:11:48 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936416956 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2936416956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.2026446486 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 11337188905 ps |
| CPU time | 107.23 seconds |
| Started | Oct 03 01:11:41 AM UTC 24 |
| Finished | Oct 03 01:13:31 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026446486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all _with_rand_reset.2026446486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_alert.541722963 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 116513690 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:11:51 AM UTC 24 |
| Finished | Oct 03 01:11:53 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541722963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 41.edn_alert.541722963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_alert_test.4018914055 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 25473453 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:11:54 AM UTC 24 |
| Finished | Oct 03 01:11:56 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018914055 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4018914055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_disable.623777319 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 13725827 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 01:11:53 AM UTC 24 |
| Finished | Oct 03 01:11:55 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623777319 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.623777319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.1539665863 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 191609221 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 01:11:54 AM UTC 24 |
| Finished | Oct 03 01:11:57 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539665863 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.1539665863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_genbits.1142886329 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 44483502 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:11:48 AM UTC 24 |
| Finished | Oct 03 01:11:50 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142886329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1142886329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_intr.1812695610 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 21410795 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:11:51 AM UTC 24 |
| Finished | Oct 03 01:11:54 AM UTC 24 |
| Peak memory | 237424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812695610 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1812695610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_smoke.1315056761 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 49188613 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:11:47 AM UTC 24 |
| Finished | Oct 03 01:11:50 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315056761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.edn_smoke.1315056761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_stress_all.2341389095 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 105389770 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 01:11:49 AM UTC 24 |
| Finished | Oct 03 01:11:52 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341389095 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2341389095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.2864753295 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3396075877 ps |
| CPU time | 104.62 seconds |
| Started | Oct 03 01:11:50 AM UTC 24 |
| Finished | Oct 03 01:13:37 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864753295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all _with_rand_reset.2864753295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_alert.1672860656 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 31094693 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:11:58 AM UTC 24 |
| Finished | Oct 03 01:12:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672860656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_alert.1672860656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_alert_test.1768782491 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 19878200 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:12:02 AM UTC 24 |
| Finished | Oct 03 01:12:04 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768782491 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1768782491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_disable.2527859354 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 70656071 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 01:12:01 AM UTC 24 |
| Finished | Oct 03 01:12:03 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527859354 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2527859354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.4048127165 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 147330914 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:12:01 AM UTC 24 |
| Finished | Oct 03 01:12:03 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048127165 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.4048127165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_err.3790386768 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 40449215 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:12:00 AM UTC 24 |
| Finished | Oct 03 01:12:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790386768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 42.edn_err.3790386768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_genbits.681244734 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 73678851 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:11:56 AM UTC 24 |
| Finished | Oct 03 01:11:59 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681244734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.edn_genbits.681244734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_intr.3448870674 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 32520758 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:11:57 AM UTC 24 |
| Finished | Oct 03 01:12:00 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448870674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3448870674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_smoke.2156551940 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 15254918 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:11:54 AM UTC 24 |
| Finished | Oct 03 01:11:57 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156551940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_smoke.2156551940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_stress_all.3183107976 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 221718475 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 01:11:57 AM UTC 24 |
| Finished | Oct 03 01:12:01 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183107976 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3183107976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.2789526218 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5232747792 ps |
| CPU time | 50.74 seconds |
| Started | Oct 03 01:11:57 AM UTC 24 |
| Finished | Oct 03 01:12:50 AM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789526218 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all _with_rand_reset.2789526218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_alert_test.3316425695 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 52146620 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:12:12 AM UTC 24 |
| Finished | Oct 03 01:12:14 AM UTC 24 |
| Peak memory | 227276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316425695 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3316425695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.1406898851 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 71050793 ps |
| CPU time | 2 seconds |
| Started | Oct 03 01:12:10 AM UTC 24 |
| Finished | Oct 03 01:12:13 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406898851 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.1406898851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_err.1268221555 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 31115836 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 01:12:08 AM UTC 24 |
| Finished | Oct 03 01:12:11 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268221555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 43.edn_err.1268221555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_genbits.3723754462 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 68767411 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:12:04 AM UTC 24 |
| Finished | Oct 03 01:12:07 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723754462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3723754462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_intr.319845215 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 20772442 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:12:06 AM UTC 24 |
| Finished | Oct 03 01:12:09 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319845215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.319845215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_smoke.3033367809 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 29676817 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:12:03 AM UTC 24 |
| Finished | Oct 03 01:12:05 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033367809 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.edn_smoke.3033367809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_stress_all.2833667071 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 158414742 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 01:12:04 AM UTC 24 |
| Finished | Oct 03 01:12:07 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833667071 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2833667071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.2221159393 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4185195956 ps |
| CPU time | 103.01 seconds |
| Started | Oct 03 01:12:05 AM UTC 24 |
| Finished | Oct 03 01:13:51 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221159393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all _with_rand_reset.2221159393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_alert.3470559293 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 25358027 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:12:22 AM UTC 24 |
| Finished | Oct 03 01:12:25 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470559293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.edn_alert.3470559293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_alert_test.3742262819 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 39072537 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:12:25 AM UTC 24 |
| Finished | Oct 03 01:12:28 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742262819 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3742262819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_disable.3206752139 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 12501621 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:12:22 AM UTC 24 |
| Finished | Oct 03 01:12:25 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206752139 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3206752139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_err.4136323572 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 28841114 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:12:22 AM UTC 24 |
| Finished | Oct 03 01:12:25 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136323572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 44.edn_err.4136323572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_intr.861286506 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 21966972 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 01:12:19 AM UTC 24 |
| Finished | Oct 03 01:12:21 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861286506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.861286506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_smoke.47214487 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 15853261 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:12:13 AM UTC 24 |
| Finished | Oct 03 01:12:15 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47214487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.47214487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/44.edn_stress_all.1482628982 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 542292893 ps |
| CPU time | 4.87 seconds |
| Started | Oct 03 01:12:15 AM UTC 24 |
| Finished | Oct 03 01:12:21 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482628982 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1482628982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/44.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_alert.3999602307 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 27105733 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:12:33 AM UTC 24 |
| Finished | Oct 03 01:12:35 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999602307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.edn_alert.3999602307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_alert_test.3009123601 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 15147512 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:12:39 AM UTC 24 |
| Finished | Oct 03 01:12:41 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009123601 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3009123601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_disable.183900868 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 17207704 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:12:36 AM UTC 24 |
| Finished | Oct 03 01:12:38 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183900868 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.183900868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3438163350 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 40638836 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 01:12:38 AM UTC 24 |
| Finished | Oct 03 01:12:41 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438163350 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3438163350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_err.913736777 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 57113603 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:12:35 AM UTC 24 |
| Finished | Oct 03 01:12:37 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913736777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 45.edn_err.913736777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_genbits.1117038351 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 71023738 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:12:28 AM UTC 24 |
| Finished | Oct 03 01:12:31 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117038351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1117038351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_intr.1188899124 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 25582925 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:12:32 AM UTC 24 |
| Finished | Oct 03 01:12:34 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188899124 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1188899124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_smoke.3996041197 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 60379071 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:12:25 AM UTC 24 |
| Finished | Oct 03 01:12:28 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996041197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.edn_smoke.3996041197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/45.edn_stress_all.1794656946 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 364282493 ps |
| CPU time | 10.67 seconds |
| Started | Oct 03 01:12:28 AM UTC 24 |
| Finished | Oct 03 01:12:40 AM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794656946 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1794656946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_alert.2167642053 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 24152225 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:12:42 AM UTC 24 |
| Finished | Oct 03 01:12:45 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167642053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_alert.2167642053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_alert_test.484377894 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 22890208 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:12:46 AM UTC 24 |
| Finished | Oct 03 01:12:48 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484377894 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.484377894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_disable.1898788769 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 56616275 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:12:46 AM UTC 24 |
| Finished | Oct 03 01:12:48 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898788769 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1898788769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.3158208795 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 34248117 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 01:12:46 AM UTC 24 |
| Finished | Oct 03 01:12:48 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158208795 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.3158208795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_err.2514411159 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 20687477 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:12:46 AM UTC 24 |
| Finished | Oct 03 01:12:48 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514411159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 46.edn_err.2514411159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_genbits.542614004 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 102381818 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 01:12:41 AM UTC 24 |
| Finished | Oct 03 01:12:44 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542614004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.edn_genbits.542614004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_intr.1321371766 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 40165344 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:12:42 AM UTC 24 |
| Finished | Oct 03 01:12:45 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321371766 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1321371766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_smoke.1247171881 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 46496555 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:12:39 AM UTC 24 |
| Finished | Oct 03 01:12:41 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247171881 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_smoke.1247171881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_stress_all.32637909 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 42832031 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 01:12:42 AM UTC 24 |
| Finished | Oct 03 01:12:45 AM UTC 24 |
| Peak memory | 226900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32637909 -assert nopostproc +UVM_TESTNAME=edn_s tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.32637909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.435931876 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 7538611113 ps |
| CPU time | 118.7 seconds |
| Started | Oct 03 01:12:42 AM UTC 24 |
| Finished | Oct 03 01:14:43 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435931876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_ with_rand_reset.435931876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_alert.3633787077 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 151314685 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 01:12:49 AM UTC 24 |
| Finished | Oct 03 01:12:53 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633787077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_alert.3633787077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_alert_test.2529796932 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 19094397 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:12:55 AM UTC 24 |
| Finished | Oct 03 01:12:57 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529796932 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2529796932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_disable.858156335 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 11863921 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 01:12:53 AM UTC 24 |
| Finished | Oct 03 01:12:56 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858156335 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.858156335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.3573501084 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 47222606 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:12:53 AM UTC 24 |
| Finished | Oct 03 01:12:56 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573501084 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.3573501084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_err.4032068532 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 20092477 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:12:50 AM UTC 24 |
| Finished | Oct 03 01:12:53 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032068532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 47.edn_err.4032068532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_genbits.3858426927 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 45827788 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 01:12:49 AM UTC 24 |
| Finished | Oct 03 01:12:53 AM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858426927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3858426927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_intr.4271944010 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 54874992 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:12:49 AM UTC 24 |
| Finished | Oct 03 01:12:53 AM UTC 24 |
| Peak memory | 237360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271944010 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4271944010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_smoke.1686516942 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 22306125 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:12:46 AM UTC 24 |
| Finished | Oct 03 01:12:48 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686516942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_smoke.1686516942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_stress_all.1370624404 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 233213795 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 01:12:49 AM UTC 24 |
| Finished | Oct 03 01:12:55 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370624404 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1370624404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.3384466277 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 19102903610 ps |
| CPU time | 108.95 seconds |
| Started | Oct 03 01:12:49 AM UTC 24 |
| Finished | Oct 03 01:14:41 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384466277 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all _with_rand_reset.3384466277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_alert.3621030059 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 25910324 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:12:58 AM UTC 24 |
| Finished | Oct 03 01:13:01 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621030059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.edn_alert.3621030059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_alert_test.1656848445 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 16347287 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 01:13:03 AM UTC 24 |
| Finished | Oct 03 01:13:06 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656848445 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1656848445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_disable.2082750423 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 42079096 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 01:13:01 AM UTC 24 |
| Finished | Oct 03 01:13:04 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082750423 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2082750423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.2890219799 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 32784848 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:13:02 AM UTC 24 |
| Finished | Oct 03 01:13:05 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890219799 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.2890219799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_err.24909850 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 34887028 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:13:00 AM UTC 24 |
| Finished | Oct 03 01:13:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24909850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 48.edn_err.24909850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_genbits.2392661081 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 70273571 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 01:12:56 AM UTC 24 |
| Finished | Oct 03 01:12:59 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392661081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2392661081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_intr.3095282052 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 36809861 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 01:12:58 AM UTC 24 |
| Finished | Oct 03 01:13:00 AM UTC 24 |
| Peak memory | 226976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095282052 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3095282052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_smoke.4206772450 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 19438006 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:12:55 AM UTC 24 |
| Finished | Oct 03 01:12:57 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206772450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.edn_smoke.4206772450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_stress_all.3018864911 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 148515746 ps |
| CPU time | 4.64 seconds |
| Started | Oct 03 01:12:57 AM UTC 24 |
| Finished | Oct 03 01:13:02 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018864911 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3018864911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.2503126797 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 23242125167 ps |
| CPU time | 151.39 seconds |
| Started | Oct 03 01:12:57 AM UTC 24 |
| Finished | Oct 03 01:15:31 AM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503126797 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all _with_rand_reset.2503126797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_alert.2346241642 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 289098406 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:13:07 AM UTC 24 |
| Finished | Oct 03 01:13:09 AM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346241642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_alert.2346241642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_alert_test.3491824788 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 22983459 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 01:13:11 AM UTC 24 |
| Finished | Oct 03 01:13:13 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491824788 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3491824788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_disable.3104403531 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 39026784 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:13:10 AM UTC 24 |
| Finished | Oct 03 01:13:12 AM UTC 24 |
| Peak memory | 226832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104403531 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3104403531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.2824249789 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 91622804 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:13:11 AM UTC 24 |
| Finished | Oct 03 01:13:14 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824249789 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.2824249789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_err.3249808010 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 23353803 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:13:10 AM UTC 24 |
| Finished | Oct 03 01:13:12 AM UTC 24 |
| Peak memory | 228840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249808010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 49.edn_err.3249808010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_genbits.3967730394 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 186887097 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 01:13:04 AM UTC 24 |
| Finished | Oct 03 01:13:10 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967730394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3967730394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_intr.564802038 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 29881339 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:13:07 AM UTC 24 |
| Finished | Oct 03 01:13:09 AM UTC 24 |
| Peak memory | 226620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564802038 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.564802038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_smoke.1126321991 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 68955244 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:13:03 AM UTC 24 |
| Finished | Oct 03 01:13:06 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126321991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_smoke.1126321991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/49.edn_stress_all.1323509497 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 503714997 ps |
| CPU time | 3.35 seconds |
| Started | Oct 03 01:13:05 AM UTC 24 |
| Finished | Oct 03 01:13:09 AM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323509497 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1323509497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/49.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_alert.3427979641 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 36299542 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:08:46 AM UTC 24 |
| Finished | Oct 03 01:08:49 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427979641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_alert.3427979641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_alert_test.1622905732 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 16737161 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 01:08:46 AM UTC 24 |
| Finished | Oct 03 01:08:49 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622905732 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1622905732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_disable.3321962714 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 32827812 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 01:08:46 AM UTC 24 |
| Finished | Oct 03 01:08:48 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321962714 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3321962714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_err.987290809 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 19108400 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:08:46 AM UTC 24 |
| Finished | Oct 03 01:08:49 AM UTC 24 |
| Peak memory | 228960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987290809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 5.edn_err.987290809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_genbits.1188394359 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49953956 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 01:08:45 AM UTC 24 |
| Finished | Oct 03 01:08:48 AM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188394359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1188394359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_intr.1417864826 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 30761405 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:08:46 AM UTC 24 |
| Finished | Oct 03 01:08:49 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417864826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1417864826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_regwen.1078522501 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 18465904 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:08:45 AM UTC 24 |
| Finished | Oct 03 01:08:47 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078522501 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 5.edn_regwen.1078522501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_smoke.4174801912 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 34936144 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 01:08:45 AM UTC 24 |
| Finished | Oct 03 01:08:47 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174801912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_smoke.4174801912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_stress_all.1398532736 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 137261401 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 01:08:45 AM UTC 24 |
| Finished | Oct 03 01:08:49 AM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398532736 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1398532736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.820253062 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 10177371103 ps |
| CPU time | 65.82 seconds |
| Started | Oct 03 01:08:46 AM UTC 24 |
| Finished | Oct 03 01:09:54 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820253062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_w ith_rand_reset.820253062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/50.edn_alert.740510074 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 60424838 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:13:13 AM UTC 24 |
| Finished | Oct 03 01:13:16 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740510074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 50.edn_alert.740510074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/50.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/50.edn_err.1303738875 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 21296741 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 01:13:14 AM UTC 24 |
| Finished | Oct 03 01:13:17 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303738875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 50.edn_err.1303738875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/50.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/50.edn_genbits.2301382542 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 100319765 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 01:13:13 AM UTC 24 |
| Finished | Oct 03 01:13:18 AM UTC 24 |
| Peak memory | 228128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301382542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2301382542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/50.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/51.edn_alert.2469549658 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 90884513 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:13:16 AM UTC 24 |
| Finished | Oct 03 01:13:19 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469549658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 51.edn_alert.2469549658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/51.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/51.edn_err.862072554 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 28599348 ps |
| CPU time | 1 seconds |
| Started | Oct 03 01:13:17 AM UTC 24 |
| Finished | Oct 03 01:13:19 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862072554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 51.edn_err.862072554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/51.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/51.edn_genbits.1725688088 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 78711572 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 01:13:14 AM UTC 24 |
| Finished | Oct 03 01:13:18 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725688088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1725688088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/51.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/52.edn_alert.1449296624 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 180220629 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:13:19 AM UTC 24 |
| Finished | Oct 03 01:13:21 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449296624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 52.edn_alert.1449296624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/52.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/52.edn_err.3564829700 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 19285162 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:13:20 AM UTC 24 |
| Finished | Oct 03 01:13:22 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564829700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 52.edn_err.3564829700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/52.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/52.edn_genbits.3956382084 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 142827624 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:13:18 AM UTC 24 |
| Finished | Oct 03 01:13:21 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956382084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3956382084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/52.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/53.edn_alert.1036864938 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 81402808 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:13:22 AM UTC 24 |
| Finished | Oct 03 01:13:25 AM UTC 24 |
| Peak memory | 231032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036864938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 53.edn_alert.1036864938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/53.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/53.edn_err.3822454451 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 20478750 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:13:22 AM UTC 24 |
| Finished | Oct 03 01:13:25 AM UTC 24 |
| Peak memory | 231044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822454451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 53.edn_err.3822454451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/53.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/53.edn_genbits.1155981245 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 56693667 ps |
| CPU time | 2.65 seconds |
| Started | Oct 03 01:13:21 AM UTC 24 |
| Finished | Oct 03 01:13:24 AM UTC 24 |
| Peak memory | 230196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155981245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1155981245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/53.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/54.edn_err.2517905495 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 24700446 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:13:25 AM UTC 24 |
| Finished | Oct 03 01:13:28 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517905495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 54.edn_err.2517905495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/54.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/54.edn_genbits.3760381745 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 157415883 ps |
| CPU time | 5.05 seconds |
| Started | Oct 03 01:13:23 AM UTC 24 |
| Finished | Oct 03 01:13:29 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760381745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3760381745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/54.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/55.edn_alert.566701232 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 72364756 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:13:28 AM UTC 24 |
| Finished | Oct 03 01:13:31 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566701232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 55.edn_alert.566701232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/55.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/55.edn_err.4282504804 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 32867245 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:13:29 AM UTC 24 |
| Finished | Oct 03 01:13:32 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282504804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 55.edn_err.4282504804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/55.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/55.edn_genbits.3597306864 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 66427418 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 01:13:26 AM UTC 24 |
| Finished | Oct 03 01:13:29 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597306864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3597306864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/55.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/56.edn_alert.2808027308 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 23015518 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:13:30 AM UTC 24 |
| Finished | Oct 03 01:13:33 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808027308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 56.edn_alert.2808027308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/56.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/56.edn_err.4149974403 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 30321574 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:13:31 AM UTC 24 |
| Finished | Oct 03 01:13:34 AM UTC 24 |
| Peak memory | 246620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149974403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 56.edn_err.4149974403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/56.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/56.edn_genbits.648603786 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 50969854 ps |
| CPU time | 2.68 seconds |
| Started | Oct 03 01:13:29 AM UTC 24 |
| Finished | Oct 03 01:13:33 AM UTC 24 |
| Peak memory | 230240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648603786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 56.edn_genbits.648603786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/56.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/57.edn_alert.3609842190 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 24588884 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:13:33 AM UTC 24 |
| Finished | Oct 03 01:13:36 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609842190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 57.edn_alert.3609842190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/57.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/57.edn_err.871927138 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 101252294 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 01:13:33 AM UTC 24 |
| Finished | Oct 03 01:13:36 AM UTC 24 |
| Peak memory | 243252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871927138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 57.edn_err.871927138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/57.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/57.edn_genbits.390989263 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 56672671 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 01:13:32 AM UTC 24 |
| Finished | Oct 03 01:13:35 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390989263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 57.edn_genbits.390989263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/57.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/58.edn_alert.3521492991 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 179125843 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 01:13:34 AM UTC 24 |
| Finished | Oct 03 01:13:37 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521492991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 58.edn_alert.3521492991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/58.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/58.edn_err.2481249330 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 20099497 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 01:13:35 AM UTC 24 |
| Finished | Oct 03 01:13:38 AM UTC 24 |
| Peak memory | 238328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481249330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 58.edn_err.2481249330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/58.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/58.edn_genbits.342050077 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 48334512 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:13:34 AM UTC 24 |
| Finished | Oct 03 01:13:37 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342050077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 58.edn_genbits.342050077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/58.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/59.edn_alert.1772405029 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 96202299 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:13:36 AM UTC 24 |
| Finished | Oct 03 01:13:39 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772405029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 59.edn_alert.1772405029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/59.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/59.edn_err.1126988156 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 29850984 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:13:36 AM UTC 24 |
| Finished | Oct 03 01:13:39 AM UTC 24 |
| Peak memory | 238216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126988156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 59.edn_err.1126988156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/59.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/59.edn_genbits.211753285 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 37820821 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:13:36 AM UTC 24 |
| Finished | Oct 03 01:13:39 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211753285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 59.edn_genbits.211753285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/59.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_alert.611978415 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 29841720 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:08:49 AM UTC 24 |
| Finished | Oct 03 01:08:52 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611978415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.edn_alert.611978415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_alert_test.2713882685 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 52752999 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713882685 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2713882685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_disable.970573166 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 11546663 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 227020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970573166 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.970573166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.542268172 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 29188894 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542268172 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.542268172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_err.279706734 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 239519053 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 242900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279706734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 6.edn_err.279706734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_genbits.2722742832 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 38323470 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:08:48 AM UTC 24 |
| Finished | Oct 03 01:08:50 AM UTC 24 |
| Peak memory | 229260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722742832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2722742832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_intr.2952496544 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 42547670 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:08:49 AM UTC 24 |
| Finished | Oct 03 01:08:51 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952496544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2952496544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_regwen.736901161 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 20717846 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 01:08:47 AM UTC 24 |
| Finished | Oct 03 01:08:50 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736901161 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_regwen.736901161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_smoke.2535181479 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 27772984 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 01:08:47 AM UTC 24 |
| Finished | Oct 03 01:08:50 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535181479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_smoke.2535181479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/6.edn_stress_all.3482231013 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 396232905 ps |
| CPU time | 3.61 seconds |
| Started | Oct 03 01:08:49 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482231013 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3482231013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/60.edn_alert.31631919 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 86804390 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:13:37 AM UTC 24 |
| Finished | Oct 03 01:13:40 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31631919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.31631919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/60.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/60.edn_err.2971233392 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 44709171 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 01:13:38 AM UTC 24 |
| Finished | Oct 03 01:13:40 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971233392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 60.edn_err.2971233392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/60.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/60.edn_genbits.4185461045 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 37547013 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 01:13:37 AM UTC 24 |
| Finished | Oct 03 01:13:40 AM UTC 24 |
| Peak memory | 230168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185461045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.4185461045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/60.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/61.edn_alert.2575656386 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 43667859 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 01:13:40 AM UTC 24 |
| Finished | Oct 03 01:13:42 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575656386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 61.edn_alert.2575656386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/61.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/61.edn_err.825392246 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 42148143 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:13:40 AM UTC 24 |
| Finished | Oct 03 01:13:42 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825392246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 61.edn_err.825392246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/61.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/61.edn_genbits.3080391457 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 45584349 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 01:13:39 AM UTC 24 |
| Finished | Oct 03 01:13:42 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080391457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3080391457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/61.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/62.edn_alert.73474744 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 70357827 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 01:13:41 AM UTC 24 |
| Finished | Oct 03 01:13:43 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73474744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.73474744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/62.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/62.edn_err.70773380 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 19801198 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 01:13:41 AM UTC 24 |
| Finished | Oct 03 01:13:44 AM UTC 24 |
| Peak memory | 237172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70773380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 62.edn_err.70773380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/62.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/62.edn_genbits.2885946698 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 86515694 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 01:13:40 AM UTC 24 |
| Finished | Oct 03 01:13:44 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885946698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2885946698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/62.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/63.edn_alert.1450800835 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 49631070 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 01:13:42 AM UTC 24 |
| Finished | Oct 03 01:13:45 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450800835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 63.edn_alert.1450800835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/63.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/63.edn_err.3035989047 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 36116492 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:13:43 AM UTC 24 |
| Finished | Oct 03 01:13:46 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035989047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 63.edn_err.3035989047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/63.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/63.edn_genbits.4127215499 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 122786037 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:13:41 AM UTC 24 |
| Finished | Oct 03 01:13:44 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127215499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4127215499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/63.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/64.edn_alert.3163450578 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 72108758 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:13:44 AM UTC 24 |
| Finished | Oct 03 01:13:46 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163450578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 64.edn_alert.3163450578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/64.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/64.edn_genbits.324262803 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 38861435 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 01:13:43 AM UTC 24 |
| Finished | Oct 03 01:13:47 AM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324262803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 64.edn_genbits.324262803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/64.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/65.edn_alert.3146310919 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 28178721 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 01:13:45 AM UTC 24 |
| Finished | Oct 03 01:13:47 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146310919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 65.edn_alert.3146310919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/65.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/65.edn_err.2776913508 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 21495092 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:13:45 AM UTC 24 |
| Finished | Oct 03 01:13:47 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776913508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 65.edn_err.2776913508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/65.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/65.edn_genbits.957597944 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 34693236 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 01:13:45 AM UTC 24 |
| Finished | Oct 03 01:13:48 AM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957597944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 65.edn_genbits.957597944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/65.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/66.edn_alert.2725792418 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 24434013 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:13:47 AM UTC 24 |
| Finished | Oct 03 01:13:50 AM UTC 24 |
| Peak memory | 228900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725792418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 66.edn_alert.2725792418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/66.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/66.edn_err.274449812 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 20897026 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 01:13:47 AM UTC 24 |
| Finished | Oct 03 01:13:49 AM UTC 24 |
| Peak memory | 228888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274449812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 66.edn_err.274449812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/66.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/66.edn_genbits.1323693138 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 87125894 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:13:46 AM UTC 24 |
| Finished | Oct 03 01:13:49 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323693138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1323693138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/66.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/67.edn_alert.1867836227 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 92217778 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:13:48 AM UTC 24 |
| Finished | Oct 03 01:13:51 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867836227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 67.edn_alert.1867836227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/67.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/67.edn_err.3079513577 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 61823719 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:13:48 AM UTC 24 |
| Finished | Oct 03 01:13:51 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079513577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 67.edn_err.3079513577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/67.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/67.edn_genbits.4241814788 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 75201881 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:13:48 AM UTC 24 |
| Finished | Oct 03 01:13:51 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241814788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4241814788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/67.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/68.edn_alert.2805609158 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 45328902 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:13:49 AM UTC 24 |
| Finished | Oct 03 01:13:52 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805609158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 68.edn_alert.2805609158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/68.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/68.edn_err.3202960959 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 34314763 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:13:49 AM UTC 24 |
| Finished | Oct 03 01:13:52 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202960959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 68.edn_err.3202960959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/68.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/68.edn_genbits.3871919412 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 85521113 ps |
| CPU time | 2.53 seconds |
| Started | Oct 03 01:13:48 AM UTC 24 |
| Finished | Oct 03 01:13:52 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871919412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3871919412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/68.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/69.edn_alert.306479577 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 82713430 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:13:50 AM UTC 24 |
| Finished | Oct 03 01:13:53 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306479577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 69.edn_alert.306479577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/69.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/69.edn_err.4025108354 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 46140741 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:13:52 AM UTC 24 |
| Finished | Oct 03 01:13:54 AM UTC 24 |
| Peak memory | 238280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025108354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 69.edn_err.4025108354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/69.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/69.edn_genbits.3426125824 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 242261078 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:13:50 AM UTC 24 |
| Finished | Oct 03 01:13:53 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426125824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3426125824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/69.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_alert.3053397169 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 24988734 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:08:51 AM UTC 24 |
| Finished | Oct 03 01:08:55 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053397169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_alert.3053397169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_alert_test.1831550082 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 13942003 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:08:54 AM UTC 24 |
| Finished | Oct 03 01:08:56 AM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831550082 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1831550082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_disable.2680280244 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 11603391 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 01:08:53 AM UTC 24 |
| Finished | Oct 03 01:08:55 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680280244 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2680280244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.1749418540 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 161747037 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:08:54 AM UTC 24 |
| Finished | Oct 03 01:08:56 AM UTC 24 |
| Peak memory | 232408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749418540 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.1749418540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_genbits.535290941 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 40673103 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535290941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.edn_genbits.535290941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_intr.3387754782 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 27750843 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:08:51 AM UTC 24 |
| Finished | Oct 03 01:08:54 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387754782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3387754782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_regwen.741502140 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 23320420 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741502140 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_regwen.741502140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_smoke.3284561677 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 19645017 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:53 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284561677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_smoke.3284561677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_stress_all.3203181068 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 316250852 ps |
| CPU time | 6.07 seconds |
| Started | Oct 03 01:08:50 AM UTC 24 |
| Finished | Oct 03 01:08:58 AM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203181068 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3203181068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.2217969601 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3655179105 ps |
| CPU time | 54.97 seconds |
| Started | Oct 03 01:08:51 AM UTC 24 |
| Finished | Oct 03 01:09:48 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217969601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_ with_rand_reset.2217969601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/70.edn_alert.3131081204 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 22236221 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:13:52 AM UTC 24 |
| Finished | Oct 03 01:13:54 AM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131081204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 70.edn_alert.3131081204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/70.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/70.edn_err.2102111416 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 43958079 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 01:13:52 AM UTC 24 |
| Finished | Oct 03 01:13:54 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102111416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 70.edn_err.2102111416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/70.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/70.edn_genbits.2854971548 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 86535386 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 01:13:52 AM UTC 24 |
| Finished | Oct 03 01:13:55 AM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854971548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2854971548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/70.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/71.edn_alert.3878222664 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 112105218 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:13:53 AM UTC 24 |
| Finished | Oct 03 01:13:56 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878222664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 71.edn_alert.3878222664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/71.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/71.edn_err.506653013 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 19575667 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:13:53 AM UTC 24 |
| Finished | Oct 03 01:13:56 AM UTC 24 |
| Peak memory | 238276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506653013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 71.edn_err.506653013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/71.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/71.edn_genbits.1576540180 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 61277771 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 01:13:53 AM UTC 24 |
| Finished | Oct 03 01:13:56 AM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576540180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1576540180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/71.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/72.edn_alert.1945310861 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 23194386 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 01:13:54 AM UTC 24 |
| Finished | Oct 03 01:13:57 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945310861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 72.edn_alert.1945310861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/72.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/72.edn_err.1297206453 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 27857747 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 01:13:55 AM UTC 24 |
| Finished | Oct 03 01:13:57 AM UTC 24 |
| Peak memory | 238036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297206453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 72.edn_err.1297206453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/72.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/72.edn_genbits.1462546979 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 72966707 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 01:13:54 AM UTC 24 |
| Finished | Oct 03 01:13:57 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462546979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1462546979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/72.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/73.edn_alert.2762270767 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 70484355 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:13:55 AM UTC 24 |
| Finished | Oct 03 01:13:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762270767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 73.edn_alert.2762270767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/73.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/73.edn_err.928639414 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 21830169 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 01:13:56 AM UTC 24 |
| Finished | Oct 03 01:13:59 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928639414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 73.edn_err.928639414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/73.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/73.edn_genbits.1994495283 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 49869467 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:13:55 AM UTC 24 |
| Finished | Oct 03 01:13:58 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994495283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1994495283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/73.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/74.edn_alert.3166640492 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 30075287 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:13:56 AM UTC 24 |
| Finished | Oct 03 01:13:59 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166640492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 74.edn_alert.3166640492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/74.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/74.edn_err.1216594375 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 18403231 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:13:58 AM UTC 24 |
| Finished | Oct 03 01:14:00 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216594375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 74.edn_err.1216594375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/74.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/74.edn_genbits.2035538706 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 105073137 ps |
| CPU time | 2.98 seconds |
| Started | Oct 03 01:13:56 AM UTC 24 |
| Finished | Oct 03 01:14:00 AM UTC 24 |
| Peak memory | 232064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035538706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2035538706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/74.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/75.edn_alert.956235801 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 26337197 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:13:58 AM UTC 24 |
| Finished | Oct 03 01:14:01 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956235801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 75.edn_alert.956235801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/75.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/75.edn_err.3633527216 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 55076512 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 01:13:59 AM UTC 24 |
| Finished | Oct 03 01:14:01 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633527216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 75.edn_err.3633527216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/75.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/75.edn_genbits.113918287 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 47267551 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 01:13:58 AM UTC 24 |
| Finished | Oct 03 01:14:00 AM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113918287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 75.edn_genbits.113918287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/75.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/76.edn_alert.4257105779 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 49745492 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:13:59 AM UTC 24 |
| Finished | Oct 03 01:14:02 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257105779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 76.edn_alert.4257105779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/76.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/76.edn_err.1962289792 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 82778785 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 01:14:00 AM UTC 24 |
| Finished | Oct 03 01:14:02 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962289792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 76.edn_err.1962289792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/76.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/76.edn_genbits.4195436458 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 65233252 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 01:13:59 AM UTC 24 |
| Finished | Oct 03 01:14:02 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195436458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.4195436458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/76.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/77.edn_err.531255827 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 63049312 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:14:01 AM UTC 24 |
| Finished | Oct 03 01:14:03 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531255827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 77.edn_err.531255827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/77.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/77.edn_genbits.146907167 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 51820421 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 01:14:00 AM UTC 24 |
| Finished | Oct 03 01:14:03 AM UTC 24 |
| Peak memory | 230232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146907167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 77.edn_genbits.146907167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/77.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/78.edn_alert.2869151465 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 162626477 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:14:01 AM UTC 24 |
| Finished | Oct 03 01:14:04 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869151465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 78.edn_alert.2869151465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/78.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/78.edn_err.3472797149 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 22067815 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:14:02 AM UTC 24 |
| Finished | Oct 03 01:14:05 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472797149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 78.edn_err.3472797149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/78.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/78.edn_genbits.1256092381 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 59954932 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:14:01 AM UTC 24 |
| Finished | Oct 03 01:14:04 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256092381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1256092381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/78.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/79.edn_alert.2081095354 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 70860557 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:14:03 AM UTC 24 |
| Finished | Oct 03 01:14:06 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081095354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 79.edn_alert.2081095354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/79.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/79.edn_err.3429248264 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 22398143 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:14:04 AM UTC 24 |
| Finished | Oct 03 01:14:06 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429248264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 79.edn_err.3429248264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/79.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/79.edn_genbits.1994658964 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 51648535 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:14:02 AM UTC 24 |
| Finished | Oct 03 01:14:05 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994658964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1994658964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/79.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_alert_test.652260629 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 30310400 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 01:08:56 AM UTC 24 |
| Finished | Oct 03 01:08:59 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652260629 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.652260629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_disable.3236906777 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 46326791 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 01:08:55 AM UTC 24 |
| Finished | Oct 03 01:08:58 AM UTC 24 |
| Peak memory | 227028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236906777 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3236906777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_err.3435368604 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 63066008 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:08:55 AM UTC 24 |
| Finished | Oct 03 01:08:57 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435368604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 8.edn_err.3435368604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_genbits.2489094177 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 103533777 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 01:08:54 AM UTC 24 |
| Finished | Oct 03 01:08:57 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489094177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2489094177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_intr.1043428480 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 31065370 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 01:08:55 AM UTC 24 |
| Finished | Oct 03 01:08:58 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043428480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1043428480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_regwen.2412659191 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 28964579 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:08:54 AM UTC 24 |
| Finished | Oct 03 01:08:56 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412659191 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 8.edn_regwen.2412659191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_smoke.256038658 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 171712751 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 01:08:54 AM UTC 24 |
| Finished | Oct 03 01:08:56 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256038658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.edn_smoke.256038658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/8.edn_stress_all.2859352884 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 116080944 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 01:08:54 AM UTC 24 |
| Finished | Oct 03 01:08:58 AM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859352884 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2859352884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/8.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/80.edn_alert.442026211 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 32548715 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 01:14:05 AM UTC 24 |
| Finished | Oct 03 01:14:08 AM UTC 24 |
| Peak memory | 228684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442026211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 80.edn_alert.442026211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/80.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/80.edn_err.3362520564 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 35991318 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 01:14:05 AM UTC 24 |
| Finished | Oct 03 01:14:07 AM UTC 24 |
| Peak memory | 244812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362520564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 80.edn_err.3362520564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/80.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/80.edn_genbits.1915660659 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 48928674 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 01:14:04 AM UTC 24 |
| Finished | Oct 03 01:14:07 AM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915660659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1915660659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/80.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/81.edn_alert.2332378354 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 96051603 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:14:05 AM UTC 24 |
| Finished | Oct 03 01:14:08 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332378354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 81.edn_alert.2332378354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/81.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/81.edn_err.3686145917 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 27860314 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 01:14:06 AM UTC 24 |
| Finished | Oct 03 01:14:09 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686145917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 81.edn_err.3686145917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/81.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/81.edn_genbits.4174708199 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 71803141 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 01:14:05 AM UTC 24 |
| Finished | Oct 03 01:14:09 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174708199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4174708199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/81.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/82.edn_alert.3452814078 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 125047850 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:14:07 AM UTC 24 |
| Finished | Oct 03 01:14:10 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452814078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 82.edn_alert.3452814078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/82.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/82.edn_err.1150522094 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 26379204 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 01:14:07 AM UTC 24 |
| Finished | Oct 03 01:14:10 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150522094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 82.edn_err.1150522094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/82.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/82.edn_genbits.3569411039 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 139047739 ps |
| CPU time | 4.45 seconds |
| Started | Oct 03 01:14:06 AM UTC 24 |
| Finished | Oct 03 01:14:11 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569411039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3569411039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/82.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/83.edn_alert.3774666123 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 69931373 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 01:14:08 AM UTC 24 |
| Finished | Oct 03 01:14:11 AM UTC 24 |
| Peak memory | 226980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774666123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 83.edn_alert.3774666123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/83.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/83.edn_err.1145181085 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 31257924 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:14:08 AM UTC 24 |
| Finished | Oct 03 01:14:11 AM UTC 24 |
| Peak memory | 238328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145181085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 83.edn_err.1145181085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/83.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/83.edn_genbits.3143137765 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 61828455 ps |
| CPU time | 3.05 seconds |
| Started | Oct 03 01:14:07 AM UTC 24 |
| Finished | Oct 03 01:14:11 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143137765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3143137765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/83.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/84.edn_alert.1364781475 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 173987808 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 01:14:09 AM UTC 24 |
| Finished | Oct 03 01:14:12 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364781475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 84.edn_alert.1364781475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/84.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/84.edn_err.3750465748 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 19541074 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 01:14:10 AM UTC 24 |
| Finished | Oct 03 01:14:12 AM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750465748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 84.edn_err.3750465748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/84.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/84.edn_genbits.1807353314 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 39947846 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 01:14:08 AM UTC 24 |
| Finished | Oct 03 01:14:11 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807353314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1807353314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/84.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/85.edn_alert.2592184641 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 23514762 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:14:11 AM UTC 24 |
| Finished | Oct 03 01:14:13 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592184641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 85.edn_alert.2592184641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/85.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/85.edn_err.2602129058 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 24050901 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 01:14:12 AM UTC 24 |
| Finished | Oct 03 01:14:15 AM UTC 24 |
| Peak memory | 247100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602129058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 85.edn_err.2602129058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/85.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/85.edn_genbits.3361656355 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 162814356 ps |
| CPU time | 3.44 seconds |
| Started | Oct 03 01:14:11 AM UTC 24 |
| Finished | Oct 03 01:14:15 AM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361656355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3361656355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/85.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/86.edn_alert.4224037132 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 27160209 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 01:14:12 AM UTC 24 |
| Finished | Oct 03 01:14:14 AM UTC 24 |
| Peak memory | 231076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224037132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 86.edn_alert.4224037132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/86.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/86.edn_err.2493238538 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 50652271 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 01:14:12 AM UTC 24 |
| Finished | Oct 03 01:14:14 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493238538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 86.edn_err.2493238538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/86.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/86.edn_genbits.424551855 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 47421014 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 01:14:12 AM UTC 24 |
| Finished | Oct 03 01:14:14 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424551855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 86.edn_genbits.424551855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/86.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/87.edn_alert.1660471680 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 34926930 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:14:13 AM UTC 24 |
| Finished | Oct 03 01:14:16 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660471680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 87.edn_alert.1660471680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/87.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/87.edn_genbits.3777923492 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 101447954 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 01:14:13 AM UTC 24 |
| Finished | Oct 03 01:14:17 AM UTC 24 |
| Peak memory | 230236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777923492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3777923492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/87.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/88.edn_alert.3840317279 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 78179347 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 01:14:15 AM UTC 24 |
| Finished | Oct 03 01:14:18 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840317279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 88.edn_alert.3840317279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/88.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/88.edn_err.2438296638 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 49978074 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 01:14:15 AM UTC 24 |
| Finished | Oct 03 01:14:18 AM UTC 24 |
| Peak memory | 246620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438296638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 88.edn_err.2438296638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/88.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/88.edn_genbits.3861089001 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31996255 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:14:14 AM UTC 24 |
| Finished | Oct 03 01:14:17 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861089001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3861089001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/88.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/89.edn_alert.1358229451 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 24939908 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:14:15 AM UTC 24 |
| Finished | Oct 03 01:14:18 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358229451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 89.edn_alert.1358229451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/89.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/89.edn_err.2645832132 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 17873844 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 01:14:17 AM UTC 24 |
| Finished | Oct 03 01:14:19 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645832132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 89.edn_err.2645832132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/89.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/89.edn_genbits.2251749856 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 51589426 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 01:14:15 AM UTC 24 |
| Finished | Oct 03 01:14:18 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251749856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2251749856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/89.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_alert_test.3869464 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 25284410 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 01:09:00 AM UTC 24 |
| Finished | Oct 03 01:09:02 AM UTC 24 |
| Peak memory | 216908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869464 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3869464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_disable.969695039 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 25144967 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 01:08:59 AM UTC 24 |
| Finished | Oct 03 01:09:01 AM UTC 24 |
| Peak memory | 227020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969695039 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.969695039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.2632268934 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 104708595 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 01:08:59 AM UTC 24 |
| Finished | Oct 03 01:09:02 AM UTC 24 |
| Peak memory | 226904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632268934 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.2632268934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_err.1077112954 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 26344860 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 01:08:59 AM UTC 24 |
| Finished | Oct 03 01:09:01 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077112954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 9.edn_err.1077112954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_genbits.3626465038 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 33296226 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 01:08:58 AM UTC 24 |
| Finished | Oct 03 01:09:01 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626465038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3626465038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_intr.3216873764 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 34294959 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:08:59 AM UTC 24 |
| Finished | Oct 03 01:09:01 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216873764 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3216873764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_regwen.483684828 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 35257722 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 01:08:56 AM UTC 24 |
| Finished | Oct 03 01:08:59 AM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483684828 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.edn_regwen.483684828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_smoke.2397507472 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 131332047 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 01:08:56 AM UTC 24 |
| Finished | Oct 03 01:08:59 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397507472 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.edn_smoke.2397507472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_stress_all.1407977905 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1009917446 ps |
| CPU time | 5.47 seconds |
| Started | Oct 03 01:08:58 AM UTC 24 |
| Finished | Oct 03 01:09:04 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407977905 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1407977905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.3125840771 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 11259250045 ps |
| CPU time | 96.49 seconds |
| Started | Oct 03 01:08:58 AM UTC 24 |
| Finished | Oct 03 01:10:36 AM UTC 24 |
| Peak memory | 230488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125840771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_ with_rand_reset.3125840771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/90.edn_alert.355309387 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 47136717 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 01:14:17 AM UTC 24 |
| Finished | Oct 03 01:14:19 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355309387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 90.edn_alert.355309387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/90.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/90.edn_err.4019965400 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 26822939 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 01:14:18 AM UTC 24 |
| Finished | Oct 03 01:14:20 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019965400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 90.edn_err.4019965400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/90.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/90.edn_genbits.389471222 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 68569974 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 01:14:17 AM UTC 24 |
| Finished | Oct 03 01:14:20 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389471222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 90.edn_genbits.389471222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/90.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/91.edn_alert.953726606 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 27638814 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:14:19 AM UTC 24 |
| Finished | Oct 03 01:14:22 AM UTC 24 |
| Peak memory | 226972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953726606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 91.edn_alert.953726606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/91.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/91.edn_err.2482139929 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 24345380 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 01:14:19 AM UTC 24 |
| Finished | Oct 03 01:14:22 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482139929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 91.edn_err.2482139929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/91.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/91.edn_genbits.668320813 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 36043907 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 01:14:18 AM UTC 24 |
| Finished | Oct 03 01:14:21 AM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668320813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 91.edn_genbits.668320813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/91.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/92.edn_alert.2505341891 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 244776367 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 01:14:19 AM UTC 24 |
| Finished | Oct 03 01:14:22 AM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505341891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 92.edn_alert.2505341891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/92.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/92.edn_err.2043668668 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 21118193 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 01:14:20 AM UTC 24 |
| Finished | Oct 03 01:14:22 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043668668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 92.edn_err.2043668668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/92.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/92.edn_genbits.1216833014 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 103531313 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 01:14:19 AM UTC 24 |
| Finished | Oct 03 01:14:22 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216833014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1216833014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/92.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/93.edn_alert.839536314 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 57414177 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 01:14:21 AM UTC 24 |
| Finished | Oct 03 01:14:24 AM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839536314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 93.edn_alert.839536314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/93.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/93.edn_err.1549931035 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 31755840 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 01:14:21 AM UTC 24 |
| Finished | Oct 03 01:14:24 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549931035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 93.edn_err.1549931035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/93.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/93.edn_genbits.1446856961 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 147537176 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 01:14:20 AM UTC 24 |
| Finished | Oct 03 01:14:23 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446856961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1446856961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/93.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/94.edn_alert.1775008458 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 27910380 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:14:22 AM UTC 24 |
| Finished | Oct 03 01:14:25 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775008458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 94.edn_alert.1775008458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/94.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/94.edn_err.3377955310 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 30091528 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 01:14:22 AM UTC 24 |
| Finished | Oct 03 01:14:25 AM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377955310 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 94.edn_err.3377955310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/94.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/95.edn_alert.1831335570 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 32098938 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 01:14:24 AM UTC 24 |
| Finished | Oct 03 01:14:26 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831335570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 95.edn_alert.1831335570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/95.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/95.edn_err.283901082 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 34498689 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 01:14:24 AM UTC 24 |
| Finished | Oct 03 01:14:26 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283901082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 95.edn_err.283901082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/95.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/95.edn_genbits.1619189748 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 80671293 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 01:14:24 AM UTC 24 |
| Finished | Oct 03 01:14:26 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619189748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1619189748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/95.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/96.edn_alert.2548081921 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 24667091 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 01:14:25 AM UTC 24 |
| Finished | Oct 03 01:14:28 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548081921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 96.edn_alert.2548081921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/96.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/96.edn_err.4100420431 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 18199077 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 01:14:25 AM UTC 24 |
| Finished | Oct 03 01:14:28 AM UTC 24 |
| Peak memory | 226968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100420431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 96.edn_err.4100420431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/96.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/96.edn_genbits.526011161 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 50562001 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 01:14:24 AM UTC 24 |
| Finished | Oct 03 01:14:27 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526011161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 96.edn_genbits.526011161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/96.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/97.edn_alert.249555055 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 51185061 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 01:14:26 AM UTC 24 |
| Finished | Oct 03 01:14:29 AM UTC 24 |
| Peak memory | 231068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249555055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 97.edn_alert.249555055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/97.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/97.edn_err.3031345601 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 27640932 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 01:14:27 AM UTC 24 |
| Finished | Oct 03 01:14:30 AM UTC 24 |
| Peak memory | 237352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031345601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 97.edn_err.3031345601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/97.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/97.edn_genbits.2829228841 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 136250178 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 01:14:26 AM UTC 24 |
| Finished | Oct 03 01:14:29 AM UTC 24 |
| Peak memory | 231060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829228841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2829228841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/97.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/98.edn_alert.2439664076 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 112013837 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 01:14:27 AM UTC 24 |
| Finished | Oct 03 01:14:30 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439664076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 98.edn_alert.2439664076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/98.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/98.edn_err.3234104939 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 21425582 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:14:27 AM UTC 24 |
| Finished | Oct 03 01:14:30 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234104939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 98.edn_err.3234104939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/98.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/98.edn_genbits.929753546 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 117665092 ps |
| CPU time | 3.63 seconds |
| Started | Oct 03 01:14:27 AM UTC 24 |
| Finished | Oct 03 01:14:32 AM UTC 24 |
| Peak memory | 230152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929753546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 98.edn_genbits.929753546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/98.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/99.edn_alert.3218742841 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 72636286 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 01:14:28 AM UTC 24 |
| Finished | Oct 03 01:14:31 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218742841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 99.edn_alert.3218742841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/99.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/99.edn_err.3773813560 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 30729944 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 01:14:29 AM UTC 24 |
| Finished | Oct 03 01:14:31 AM UTC 24 |
| Peak memory | 228956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773813560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 99.edn_err.3773813560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/99.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/default/99.edn_genbits.1161760647 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 40591316 ps |
| CPU time | 2.65 seconds |
| Started | Oct 03 01:14:28 AM UTC 24 |
| Finished | Oct 03 01:14:32 AM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161760647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1161760647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/99.edn_genbits/latest |
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