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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 98.23 93.97 97.07 93.02 96.33 99.77 93.18


Total test records in report: 1112
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1009 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3303288051 Oct 09 10:23:03 AM UTC 24 Oct 09 10:23:07 AM UTC 24 56915092 ps
T1010 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.556376038 Oct 09 10:23:01 AM UTC 24 Oct 09 10:23:08 AM UTC 24 247502682 ps
T1011 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.3720142937 Oct 09 10:23:03 AM UTC 24 Oct 09 10:23:08 AM UTC 24 361109138 ps
T1012 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.645280753 Oct 09 10:23:08 AM UTC 24 Oct 09 10:23:10 AM UTC 24 33870644 ps
T1013 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3201545124 Oct 09 10:23:08 AM UTC 24 Oct 09 10:23:10 AM UTC 24 46619471 ps
T1014 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.341459852 Oct 09 10:23:08 AM UTC 24 Oct 09 10:23:11 AM UTC 24 56022191 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3163175987 Oct 09 10:23:06 AM UTC 24 Oct 09 10:23:12 AM UTC 24 58579942 ps
T1015 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.4041309904 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:12 AM UTC 24 80189375 ps
T1016 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2911874325 Oct 09 10:23:13 AM UTC 24 Oct 09 10:23:16 AM UTC 24 28960053 ps
T1017 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.964844881 Oct 09 10:23:13 AM UTC 24 Oct 09 10:23:16 AM UTC 24 81802530 ps
T1018 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.827150696 Oct 09 10:23:14 AM UTC 24 Oct 09 10:23:16 AM UTC 24 61038188 ps
T1019 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.53396898 Oct 09 10:23:08 AM UTC 24 Oct 09 10:23:22 AM UTC 24 43480413 ps
T1020 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.391945307 Oct 09 10:23:07 AM UTC 24 Oct 09 10:23:16 AM UTC 24 21682625 ps
T1021 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2814592928 Oct 09 10:23:07 AM UTC 24 Oct 09 10:23:16 AM UTC 24 16231813 ps
T1022 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2355564180 Oct 09 10:23:07 AM UTC 24 Oct 09 10:23:16 AM UTC 24 67518165 ps
T1023 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2276045716 Oct 09 10:23:07 AM UTC 24 Oct 09 10:23:17 AM UTC 24 78568129 ps
T1024 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3738996776 Oct 09 10:23:11 AM UTC 24 Oct 09 10:23:18 AM UTC 24 47783229 ps
T1025 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2760020195 Oct 09 10:23:12 AM UTC 24 Oct 09 10:23:20 AM UTC 24 14698898 ps
T1026 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3948508527 Oct 09 10:23:05 AM UTC 24 Oct 09 10:23:20 AM UTC 24 31324506 ps
T1027 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3470327654 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:21 AM UTC 24 64535798 ps
T1028 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2301310186 Oct 09 10:23:05 AM UTC 24 Oct 09 10:23:21 AM UTC 24 198053590 ps
T1029 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.3389755000 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:22 AM UTC 24 28877019 ps
T1030 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2602406769 Oct 09 10:23:09 AM UTC 24 Oct 09 10:23:22 AM UTC 24 47306354 ps
T1031 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.952763370 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:22 AM UTC 24 10876128 ps
T1032 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.2381696523 Oct 09 10:23:17 AM UTC 24 Oct 09 10:23:23 AM UTC 24 13713673 ps
T1033 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.673411175 Oct 09 10:23:18 AM UTC 24 Oct 09 10:23:23 AM UTC 24 89311169 ps
T1034 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1523541926 Oct 09 10:23:17 AM UTC 24 Oct 09 10:23:23 AM UTC 24 59495608 ps
T1035 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.1374755816 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:22 AM UTC 24 24536252 ps
T1036 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.3390708097 Oct 09 10:23:18 AM UTC 24 Oct 09 10:23:22 AM UTC 24 29245043 ps
T1037 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.459887296 Oct 09 10:23:17 AM UTC 24 Oct 09 10:23:22 AM UTC 24 49173841 ps
T1038 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2740865374 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:22 AM UTC 24 21932026 ps
T1039 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1784583402 Oct 09 10:23:08 AM UTC 24 Oct 09 10:23:23 AM UTC 24 308490145 ps
T1040 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1495346908 Oct 09 10:23:17 AM UTC 24 Oct 09 10:23:23 AM UTC 24 55331711 ps
T1041 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.414501575 Oct 09 10:23:21 AM UTC 24 Oct 09 10:23:23 AM UTC 24 34839648 ps
T1042 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3192571621 Oct 09 10:23:17 AM UTC 24 Oct 09 10:23:24 AM UTC 24 100499867 ps
T1043 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.67201364 Oct 09 10:23:17 AM UTC 24 Oct 09 10:23:24 AM UTC 24 207607269 ps
T1044 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2972438943 Oct 09 10:23:02 AM UTC 24 Oct 09 10:23:24 AM UTC 24 73431240 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4128469054 Oct 09 10:23:09 AM UTC 24 Oct 09 10:23:24 AM UTC 24 899116847 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.281699254 Oct 09 10:23:22 AM UTC 24 Oct 09 10:23:25 AM UTC 24 76396528 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2614319916 Oct 09 10:23:22 AM UTC 24 Oct 09 10:23:25 AM UTC 24 25995959 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3361080271 Oct 09 10:23:22 AM UTC 24 Oct 09 10:23:25 AM UTC 24 35957446 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.508630059 Oct 09 10:23:23 AM UTC 24 Oct 09 10:23:25 AM UTC 24 33347224 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2220016041 Oct 09 10:23:23 AM UTC 24 Oct 09 10:23:25 AM UTC 24 155538175 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2156333700 Oct 09 10:23:23 AM UTC 24 Oct 09 10:23:25 AM UTC 24 48988127 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.4063983335 Oct 09 10:23:22 AM UTC 24 Oct 09 10:23:25 AM UTC 24 94762237 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3409338673 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:26 AM UTC 24 38481641 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.176615760 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:26 AM UTC 24 13979853 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3508850517 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:26 AM UTC 24 25284364 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1419061604 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:27 AM UTC 24 96761661 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.844771485 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:27 AM UTC 24 36089752 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.870568808 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:27 AM UTC 24 132075401 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2015441149 Oct 09 10:23:22 AM UTC 24 Oct 09 10:23:27 AM UTC 24 77582430 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3891552534 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:27 AM UTC 24 23254107 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.124685666 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:27 AM UTC 24 388718706 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.1165504616 Oct 09 10:23:25 AM UTC 24 Oct 09 10:23:28 AM UTC 24 46563912 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3363593659 Oct 09 10:23:25 AM UTC 24 Oct 09 10:23:28 AM UTC 24 130576013 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3121129314 Oct 09 10:23:26 AM UTC 24 Oct 09 10:23:28 AM UTC 24 31735375 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1169657548 Oct 09 10:23:26 AM UTC 24 Oct 09 10:23:28 AM UTC 24 30610359 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.4121052919 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:28 AM UTC 24 784952762 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3261049277 Oct 09 10:23:26 AM UTC 24 Oct 09 10:23:28 AM UTC 24 37774610 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1744742077 Oct 09 10:23:25 AM UTC 24 Oct 09 10:23:29 AM UTC 24 48788146 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.655702613 Oct 09 10:23:25 AM UTC 24 Oct 09 10:23:29 AM UTC 24 57674147 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.654644774 Oct 09 10:23:27 AM UTC 24 Oct 09 10:23:30 AM UTC 24 14744783 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.1261900839 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:30 AM UTC 24 20205445 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.929084372 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:30 AM UTC 24 63487626 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.282188477 Oct 09 10:23:27 AM UTC 24 Oct 09 10:23:31 AM UTC 24 48492687 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2174628237 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:31 AM UTC 24 44690866 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.738640711 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:31 AM UTC 24 99281729 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2712327818 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:31 AM UTC 24 88319097 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1770000199 Oct 09 10:23:24 AM UTC 24 Oct 09 10:23:31 AM UTC 24 442529097 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.4140070812 Oct 09 10:23:29 AM UTC 24 Oct 09 10:23:32 AM UTC 24 24128512 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3149415222 Oct 09 10:23:27 AM UTC 24 Oct 09 10:23:32 AM UTC 24 294797978 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.3159486885 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:32 AM UTC 24 499130885 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.2442966317 Oct 09 10:23:27 AM UTC 24 Oct 09 10:23:32 AM UTC 24 361281298 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3537983937 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:32 AM UTC 24 47504208 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1311288774 Oct 09 10:23:30 AM UTC 24 Oct 09 10:23:32 AM UTC 24 10754563 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.1775843700 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:34 AM UTC 24 133453233 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3678656646 Oct 09 10:23:28 AM UTC 24 Oct 09 10:23:34 AM UTC 24 691354906 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3562903038 Oct 09 10:23:30 AM UTC 24 Oct 09 10:23:35 AM UTC 24 15447328 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.4034827348 Oct 09 10:23:30 AM UTC 24 Oct 09 10:23:35 AM UTC 24 164591097 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.901352022 Oct 09 10:23:30 AM UTC 24 Oct 09 10:23:35 AM UTC 24 72132550 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2916661249 Oct 09 10:23:30 AM UTC 24 Oct 09 10:23:35 AM UTC 24 52550818 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1077511281 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 39534239 ps
T1084 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.3480181659 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 20622285 ps
T1085 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3929809829 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 38567132 ps
T1086 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.2694311330 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 11708279 ps
T1087 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.325045657 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 20224130 ps
T1088 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3158166517 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 15197908 ps
T1089 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.4025784968 Oct 09 10:23:33 AM UTC 24 Oct 09 10:23:35 AM UTC 24 61883501 ps
T1090 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2712450531 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:35 AM UTC 24 13897451 ps
T1091 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.609851341 Oct 09 10:23:33 AM UTC 24 Oct 09 10:23:36 AM UTC 24 24891812 ps
T1092 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3745723854 Oct 09 10:23:34 AM UTC 24 Oct 09 10:23:36 AM UTC 24 29334983 ps
T1093 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.1966891930 Oct 09 10:23:32 AM UTC 24 Oct 09 10:23:36 AM UTC 24 15029879 ps
T1094 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1738110559 Oct 09 10:23:27 AM UTC 24 Oct 09 10:23:36 AM UTC 24 71960871 ps
T1095 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.909309191 Oct 09 10:23:34 AM UTC 24 Oct 09 10:23:36 AM UTC 24 180918368 ps
T1096 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.484975436 Oct 09 10:23:31 AM UTC 24 Oct 09 10:23:36 AM UTC 24 15729382 ps
T1097 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.2439022112 Oct 09 10:23:31 AM UTC 24 Oct 09 10:23:40 AM UTC 24 25054410 ps
T1098 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.3379588861 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 32340023 ps
T1099 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.472327581 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 17131160 ps
T1100 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1629234688 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 12995431 ps
T1101 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.1326462293 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 16940001 ps
T1102 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3148761157 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 44075894 ps
T1103 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.3746496757 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 15212113 ps
T1104 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.239894261 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 15716666 ps
T1105 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3213203895 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 22811734 ps
T1106 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.4120583124 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 43922373 ps
T1107 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.1045128672 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:41 AM UTC 24 41146517 ps
T1108 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.4139665875 Oct 09 10:23:31 AM UTC 24 Oct 09 10:23:46 AM UTC 24 49713675 ps
T1109 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.799709086 Oct 09 10:23:27 AM UTC 24 Oct 09 10:23:46 AM UTC 24 26249881 ps
T1110 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.4046933144 Oct 09 10:23:35 AM UTC 24 Oct 09 10:23:47 AM UTC 24 12894537 ps
T1111 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2700300884 Oct 09 10:23:35 AM UTC 24 Oct 09 10:23:47 AM UTC 24 27135890 ps
T1112 /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.3408104772 Oct 09 10:23:36 AM UTC 24 Oct 09 10:23:51 AM UTC 24 31480818 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.3948149508
Short name T10
Test name
Test status
Simulation time 35693208 ps
CPU time 1.42 seconds
Started Oct 09 10:17:59 AM UTC 24
Finished Oct 09 10:18:01 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948149508 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.3948149508
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_sec_cm.1172958570
Short name T17
Test name
Test status
Simulation time 983657697 ps
CPU time 8.66 seconds
Started Oct 09 10:18:00 AM UTC 24
Finished Oct 09 10:18:10 AM UTC 24
Peak memory 260804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172958570 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1172958570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_genbits.1156952619
Short name T29
Test name
Test status
Simulation time 81124735 ps
CPU time 1.78 seconds
Started Oct 09 10:18:02 AM UTC 24
Finished Oct 09 10:18:05 AM UTC 24
Peak memory 228884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156952619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1156952619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_genbits.192507857
Short name T23
Test name
Test status
Simulation time 44014237 ps
CPU time 1.98 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:16 AM UTC 24
Peak memory 231272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192507857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_genbits.192507857
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_alert.3313507937
Short name T25
Test name
Test status
Simulation time 25520266 ps
CPU time 1.74 seconds
Started Oct 09 10:17:59 AM UTC 24
Finished Oct 09 10:18:01 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313507937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.3313507937
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_stress_all.3267917008
Short name T6
Test name
Test status
Simulation time 267090884 ps
CPU time 5.49 seconds
Started Oct 09 10:17:57 AM UTC 24
Finished Oct 09 10:18:04 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267917008 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3267917008
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.2751057513
Short name T38
Test name
Test status
Simulation time 5975545137 ps
CPU time 29.16 seconds
Started Oct 09 10:18:17 AM UTC 24
Finished Oct 09 10:18:47 AM UTC 24
Peak memory 230320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2751057513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_
with_rand_reset.2751057513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_genbits.643093488
Short name T46
Test name
Test status
Simulation time 62438078 ps
CPU time 1.96 seconds
Started Oct 09 10:18:17 AM UTC 24
Finished Oct 09 10:18:20 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643093488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_genbits.643093488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_stress_all.2795157213
Short name T118
Test name
Test status
Simulation time 597848285 ps
CPU time 7.42 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:35 AM UTC 24
Peak memory 232344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795157213 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2795157213
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_alert.66394205
Short name T129
Test name
Test status
Simulation time 32435076 ps
CPU time 1.75 seconds
Started Oct 09 10:18:51 AM UTC 24
Finished Oct 09 10:18:53 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66394205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_alert.66394205
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_intr.1449481824
Short name T4
Test name
Test status
Simulation time 35648710 ps
CPU time 1.41 seconds
Started Oct 09 10:17:58 AM UTC 24
Finished Oct 09 10:18:01 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449481824 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.1449481824
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_alert.1908970422
Short name T54
Test name
Test status
Simulation time 75351980 ps
CPU time 1.61 seconds
Started Oct 09 10:18:14 AM UTC 24
Finished Oct 09 10:18:17 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908970422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.1908970422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_alert.4137035332
Short name T201
Test name
Test status
Simulation time 32232556 ps
CPU time 1.9 seconds
Started Oct 09 10:19:18 AM UTC 24
Finished Oct 09 10:19:21 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137035332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_alert.4137035332
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.2863605082
Short name T220
Test name
Test status
Simulation time 48009909 ps
CPU time 1.63 seconds
Started Oct 09 10:18:56 AM UTC 24
Finished Oct 09 10:18:59 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863605082 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.2863605082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_alert.3550775214
Short name T130
Test name
Test status
Simulation time 106055857 ps
CPU time 1.52 seconds
Started Oct 09 10:18:27 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550775214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.3550775214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_regwen.57378453
Short name T263
Test name
Test status
Simulation time 24806842 ps
CPU time 1.3 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:13 AM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57378453 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_regwen.57378453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4098262631
Short name T321
Test name
Test status
Simulation time 60597152 ps
CPU time 1.75 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:07 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098262631 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4098262631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.3445951373
Short name T242
Test name
Test status
Simulation time 1117982393 ps
CPU time 30.37 seconds
Started Oct 09 10:19:40 AM UTC 24
Finished Oct 09 10:20:11 AM UTC 24
Peak memory 230296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3445951373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all
_with_rand_reset.3445951373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.3291180051
Short name T101
Test name
Test status
Simulation time 172238981 ps
CPU time 1.33 seconds
Started Oct 09 10:18:37 AM UTC 24
Finished Oct 09 10:18:40 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291180051 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.3291180051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.1382024443
Short name T283
Test name
Test status
Simulation time 116748082 ps
CPU time 0.95 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:00 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382024443 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1382024443
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_disable.3773714505
Short name T92
Test name
Test status
Simulation time 44590930 ps
CPU time 1.09 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:39 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773714505 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3773714505
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_disable.1251390981
Short name T227
Test name
Test status
Simulation time 19700169 ps
CPU time 1.4 seconds
Started Oct 09 10:18:58 AM UTC 24
Finished Oct 09 10:19:01 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251390981 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1251390981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_disable.4024427035
Short name T96
Test name
Test status
Simulation time 21747235 ps
CPU time 1.17 seconds
Started Oct 09 10:19:07 AM UTC 24
Finished Oct 09 10:19:09 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024427035 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4024427035
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_disable.1439440937
Short name T93
Test name
Test status
Simulation time 19734531 ps
CPU time 1.23 seconds
Started Oct 09 10:18:18 AM UTC 24
Finished Oct 09 10:18:21 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439440937 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1439440937
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/100.edn_alert.440188812
Short name T173
Test name
Test status
Simulation time 44236897 ps
CPU time 1.45 seconds
Started Oct 09 10:21:47 AM UTC 24
Finished Oct 09 10:21:50 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440188812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 100.edn_alert.440188812
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_alert.3795247546
Short name T273
Test name
Test status
Simulation time 27210677 ps
CPU time 1.83 seconds
Started Oct 09 10:20:39 AM UTC 24
Finished Oct 09 10:20:42 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795247546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.3795247546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.797023485
Short name T213
Test name
Test status
Simulation time 38547962 ps
CPU time 2.04 seconds
Started Oct 09 10:18:52 AM UTC 24
Finished Oct 09 10:18:55 AM UTC 24
Peak memory 228464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797023485 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.797023485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_stress_all.3095454725
Short name T114
Test name
Test status
Simulation time 475889106 ps
CPU time 4.98 seconds
Started Oct 09 10:18:08 AM UTC 24
Finished Oct 09 10:18:14 AM UTC 24
Peak memory 228048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095454725 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3095454725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_disable.1503663352
Short name T81
Test name
Test status
Simulation time 39215989 ps
CPU time 1.15 seconds
Started Oct 09 10:18:35 AM UTC 24
Finished Oct 09 10:18:38 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503663352 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1503663352
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_intr.1003099943
Short name T34
Test name
Test status
Simulation time 23520266 ps
CPU time 1.42 seconds
Started Oct 09 10:18:17 AM UTC 24
Finished Oct 09 10:18:19 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003099943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.1003099943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/114.edn_alert.821587654
Short name T717
Test name
Test status
Simulation time 76928407 ps
CPU time 1.28 seconds
Started Oct 09 10:21:55 AM UTC 24
Finished Oct 09 10:21:58 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821587654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 114.edn_alert.821587654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_alert.92691823
Short name T74
Test name
Test status
Simulation time 48777676 ps
CPU time 1.63 seconds
Started Oct 09 10:18:41 AM UTC 24
Finished Oct 09 10:18:44 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92691823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_alert.92691823
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_disable.3408057939
Short name T24
Test name
Test status
Simulation time 22632465 ps
CPU time 1.22 seconds
Started Oct 09 10:17:59 AM UTC 24
Finished Oct 09 10:18:01 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408057939 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3408057939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_genbits.3204422230
Short name T62
Test name
Test status
Simulation time 49820390 ps
CPU time 1.57 seconds
Started Oct 09 10:18:08 AM UTC 24
Finished Oct 09 10:18:11 AM UTC 24
Peak memory 231320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204422230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3204422230
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_alert_test.1749902964
Short name T26
Test name
Test status
Simulation time 73680470 ps
CPU time 1.41 seconds
Started Oct 09 10:18:00 AM UTC 24
Finished Oct 09 10:18:02 AM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749902964 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1749902964
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/130.edn_alert.2498136180
Short name T752
Test name
Test status
Simulation time 42713377 ps
CPU time 1.64 seconds
Started Oct 09 10:22:04 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498136180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.2498136180
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_alert.3051655472
Short name T133
Test name
Test status
Simulation time 42745837 ps
CPU time 1.84 seconds
Started Oct 09 10:20:06 AM UTC 24
Finished Oct 09 10:20:09 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051655472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.3051655472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_intr.1129301135
Short name T35
Test name
Test status
Simulation time 21414121 ps
CPU time 1.29 seconds
Started Oct 09 10:19:02 AM UTC 24
Finished Oct 09 10:19:04 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129301135 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.1129301135
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.1865194813
Short name T171
Test name
Test status
Simulation time 31659980 ps
CPU time 1.21 seconds
Started Oct 09 10:18:28 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865194813 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.1865194813
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/105.edn_alert.3717235343
Short name T699
Test name
Test status
Simulation time 39976365 ps
CPU time 1.44 seconds
Started Oct 09 10:21:50 AM UTC 24
Finished Oct 09 10:21:53 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717235343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 105.edn_alert.3717235343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/107.edn_alert.1241787158
Short name T701
Test name
Test status
Simulation time 35039955 ps
CPU time 1.3 seconds
Started Oct 09 10:21:51 AM UTC 24
Finished Oct 09 10:21:54 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241787158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.1241787158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3259771465
Short name T159
Test name
Test status
Simulation time 81783038 ps
CPU time 1.18 seconds
Started Oct 09 10:18:29 AM UTC 24
Finished Oct 09 10:18:32 AM UTC 24
Peak memory 228492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259771465 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3259771465
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_alert.1354835314
Short name T155
Test name
Test status
Simulation time 23913806 ps
CPU time 1.25 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:34 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354835314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.1354835314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.3970979520
Short name T147
Test name
Test status
Simulation time 26304597 ps
CPU time 1.34 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:35 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970979520 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.3970979520
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_err.3018936243
Short name T191
Test name
Test status
Simulation time 47172182 ps
CPU time 1.39 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:39 AM UTC 24
Peak memory 238156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018936243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.3018936243
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_alert.3203040448
Short name T197
Test name
Test status
Simulation time 76828813 ps
CPU time 1.62 seconds
Started Oct 09 10:18:44 AM UTC 24
Finished Oct 09 10:18:47 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203040448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.3203040448
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_alert.2152399794
Short name T85
Test name
Test status
Simulation time 119487302 ps
CPU time 1.74 seconds
Started Oct 09 10:18:48 AM UTC 24
Finished Oct 09 10:18:51 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152399794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.2152399794
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_err.2770637732
Short name T200
Test name
Test status
Simulation time 29111583 ps
CPU time 1.28 seconds
Started Oct 09 10:19:54 AM UTC 24
Finished Oct 09 10:19:56 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770637732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.edn_err.2770637732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_disable.524867067
Short name T207
Test name
Test status
Simulation time 38105343 ps
CPU time 1.29 seconds
Started Oct 09 10:20:16 AM UTC 24
Finished Oct 09 10:20:18 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524867067 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.524867067
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_disable.2721678545
Short name T208
Test name
Test status
Simulation time 13352962 ps
CPU time 1.33 seconds
Started Oct 09 10:20:41 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 216796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721678545 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2721678545
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_disable.546184338
Short name T219
Test name
Test status
Simulation time 22384192 ps
CPU time 1.05 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:20:47 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546184338 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.546184338
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/54.edn_err.260781317
Short name T204
Test name
Test status
Simulation time 27969310 ps
CPU time 1.58 seconds
Started Oct 09 10:21:00 AM UTC 24
Finished Oct 09 10:21:04 AM UTC 24
Peak memory 246688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260781317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 54.edn_err.260781317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/135.edn_genbits.3598362454
Short name T343
Test name
Test status
Simulation time 27152527 ps
CPU time 1.51 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:08 AM UTC 24
Peak memory 231268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598362454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3598362454
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/263.edn_genbits.978427672
Short name T940
Test name
Test status
Simulation time 84967291 ps
CPU time 1.57 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:47 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978427672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 263.edn_genbits.978427672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_genbits.227532113
Short name T344
Test name
Test status
Simulation time 83529846 ps
CPU time 1.67 seconds
Started Oct 09 10:20:09 AM UTC 24
Finished Oct 09 10:20:11 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227532113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.227532113
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_genbits.3668483346
Short name T75
Test name
Test status
Simulation time 46291121 ps
CPU time 2.18 seconds
Started Oct 09 10:18:44 AM UTC 24
Finished Oct 09 10:18:47 AM UTC 24
Peak memory 230240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668483346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3668483346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_stress_all.2736216519
Short name T330
Test name
Test status
Simulation time 346571859 ps
CPU time 8.44 seconds
Started Oct 09 10:19:20 AM UTC 24
Finished Oct 09 10:19:29 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736216519 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2736216519
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_intr.1200971424
Short name T104
Test name
Test status
Simulation time 39831557 ps
CPU time 1.19 seconds
Started Oct 09 10:18:48 AM UTC 24
Finished Oct 09 10:18:50 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200971424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.1200971424
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/111.edn_genbits.4258106810
Short name T712
Test name
Test status
Simulation time 341860633 ps
CPU time 1.36 seconds
Started Oct 09 10:21:54 AM UTC 24
Finished Oct 09 10:21:56 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258106810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4258106810
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.4063983335
Short name T319
Test name
Test status
Simulation time 94762237 ps
CPU time 1.76 seconds
Started Oct 09 10:23:22 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063983335 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4063983335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_genbits.3679269452
Short name T79
Test name
Test status
Simulation time 48255953 ps
CPU time 1.85 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679269452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3679269452
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/103.edn_genbits.2045891982
Short name T327
Test name
Test status
Simulation time 74429100 ps
CPU time 1.87 seconds
Started Oct 09 10:21:49 AM UTC 24
Finished Oct 09 10:21:52 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045891982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2045891982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/123.edn_genbits.3977668045
Short name T340
Test name
Test status
Simulation time 145315739 ps
CPU time 1.69 seconds
Started Oct 09 10:22:00 AM UTC 24
Finished Oct 09 10:22:02 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977668045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3977668045
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/161.edn_genbits.2377593235
Short name T350
Test name
Test status
Simulation time 45235894 ps
CPU time 2.17 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:20 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377593235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2377593235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/175.edn_genbits.3350457229
Short name T337
Test name
Test status
Simulation time 52211729 ps
CPU time 1.48 seconds
Started Oct 09 10:22:23 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350457229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3350457229
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/246.edn_genbits.1455343715
Short name T921
Test name
Test status
Simulation time 59030076 ps
CPU time 1.36 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:44 AM UTC 24
Peak memory 231320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455343715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1455343715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_genbits.1363473853
Short name T260
Test name
Test status
Simulation time 30167554 ps
CPU time 1.35 seconds
Started Oct 09 10:19:16 AM UTC 24
Finished Oct 09 10:19:18 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363473853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1363473853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.660971792
Short name T305
Test name
Test status
Simulation time 50905584 ps
CPU time 1.53 seconds
Started Oct 09 10:19:37 AM UTC 24
Finished Oct 09 10:19:40 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660971792 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.660971792
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.1264060629
Short name T241
Test name
Test status
Simulation time 9710249430 ps
CPU time 116.54 seconds
Started Oct 09 10:17:57 AM UTC 24
Finished Oct 09 10:19:56 AM UTC 24
Peak memory 234876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1264060629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_
with_rand_reset.1264060629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_intr.1765088588
Short name T36
Test name
Test status
Simulation time 26379946 ps
CPU time 1.31 seconds
Started Oct 09 10:19:58 AM UTC 24
Finished Oct 09 10:20:00 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765088588 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.1765088588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/129.edn_alert.633779106
Short name T140
Test name
Test status
Simulation time 81135629 ps
CPU time 1.38 seconds
Started Oct 09 10:22:03 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633779106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 129.edn_alert.633779106
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_intr.3340758750
Short name T105
Test name
Test status
Simulation time 22334946 ps
CPU time 1.65 seconds
Started Oct 09 10:18:53 AM UTC 24
Finished Oct 09 10:18:56 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340758750 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.3340758750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_err.3629805623
Short name T163
Test name
Test status
Simulation time 48501976 ps
CPU time 1.45 seconds
Started Oct 09 10:18:27 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629805623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.3629805623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/166.edn_genbits.295072353
Short name T820
Test name
Test status
Simulation time 48949044 ps
CPU time 2.43 seconds
Started Oct 09 10:22:19 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295072353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 166.edn_genbits.295072353
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.2779168760
Short name T279
Test name
Test status
Simulation time 104752966 ps
CPU time 1.8 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:56 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779168760 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2779168760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.3852156838
Short name T982
Test name
Test status
Simulation time 150035646 ps
CPU time 2.46 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 216800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852156838 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3852156838
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.202538437
Short name T978
Test name
Test status
Simulation time 14203993 ps
CPU time 1.01 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 216460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202538437 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.202538437
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2948077741
Short name T980
Test name
Test status
Simulation time 161042656 ps
CPU time 1.7 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:56 AM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2948077741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2948077741
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1344578194
Short name T292
Test name
Test status
Simulation time 19137738 ps
CPU time 1.09 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:55 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344578194 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1344578194
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.2689200259
Short name T979
Test name
Test status
Simulation time 13762401 ps
CPU time 1.14 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689200259 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2689200259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.2344828064
Short name T278
Test name
Test status
Simulation time 30955179 ps
CPU time 1.52 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:56 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344828064 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2344828064
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.2574252992
Short name T981
Test name
Test status
Simulation time 78254680 ps
CPU time 3.05 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:56 AM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574252992 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2574252992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.3414625008
Short name T310
Test name
Test status
Simulation time 148443438 ps
CPU time 2.41 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:55 AM UTC 24
Peak memory 227088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414625008 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3414625008
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.4127092633
Short name T986
Test name
Test status
Simulation time 23908776 ps
CPU time 1.28 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:22:58 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127092633 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4127092633
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.2711498239
Short name T989
Test name
Test status
Simulation time 511651744 ps
CPU time 3.45 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:23:00 AM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711498239 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2711498239
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.768461735
Short name T280
Test name
Test status
Simulation time 13325481 ps
CPU time 1.14 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768461735 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.768461735
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3728419943
Short name T987
Test name
Test status
Simulation time 74860875 ps
CPU time 2.1 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:22:58 AM UTC 24
Peak memory 227228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3728419943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3728419943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.3356909834
Short name T985
Test name
Test status
Simulation time 18285999 ps
CPU time 1.41 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356909834 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3356909834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1029394635
Short name T984
Test name
Test status
Simulation time 37309462 ps
CPU time 0.98 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029394635 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1029394635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.2917011533
Short name T293
Test name
Test status
Simulation time 19990500 ps
CPU time 1.17 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917011533 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.2917011533
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3554103919
Short name T983
Test name
Test status
Simulation time 235357373 ps
CPU time 2.18 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554103919 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3554103919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.3537799854
Short name T311
Test name
Test status
Simulation time 112599379 ps
CPU time 2.75 seconds
Started Oct 09 10:22:53 AM UTC 24
Finished Oct 09 10:22:57 AM UTC 24
Peak memory 216848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537799854 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3537799854
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.827150696
Short name T1018
Test name
Test status
Simulation time 61038188 ps
CPU time 1.01 seconds
Started Oct 09 10:23:14 AM UTC 24
Finished Oct 09 10:23:16 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=827150696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.827150696
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2911874325
Short name T1016
Test name
Test status
Simulation time 28960053 ps
CPU time 0.83 seconds
Started Oct 09 10:23:13 AM UTC 24
Finished Oct 09 10:23:16 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911874325 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2911874325
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2760020195
Short name T1025
Test name
Test status
Simulation time 14698898 ps
CPU time 0.92 seconds
Started Oct 09 10:23:12 AM UTC 24
Finished Oct 09 10:23:20 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760020195 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2760020195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.964844881
Short name T1017
Test name
Test status
Simulation time 81802530 ps
CPU time 1.04 seconds
Started Oct 09 10:23:13 AM UTC 24
Finished Oct 09 10:23:16 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964844881 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.964844881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4128469054
Short name T1045
Test name
Test status
Simulation time 899116847 ps
CPU time 3.41 seconds
Started Oct 09 10:23:09 AM UTC 24
Finished Oct 09 10:23:24 AM UTC 24
Peak memory 227100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128469054 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4128469054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3738996776
Short name T1024
Test name
Test status
Simulation time 47783229 ps
CPU time 1.8 seconds
Started Oct 09 10:23:11 AM UTC 24
Finished Oct 09 10:23:18 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738996776 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3738996776
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3192571621
Short name T1042
Test name
Test status
Simulation time 100499867 ps
CPU time 2.17 seconds
Started Oct 09 10:23:17 AM UTC 24
Finished Oct 09 10:23:24 AM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3192571621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3192571621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.2381696523
Short name T1032
Test name
Test status
Simulation time 13713673 ps
CPU time 1.18 seconds
Started Oct 09 10:23:17 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381696523 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2381696523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.459887296
Short name T1037
Test name
Test status
Simulation time 49173841 ps
CPU time 1.05 seconds
Started Oct 09 10:23:17 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459887296 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.459887296
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1495346908
Short name T1040
Test name
Test status
Simulation time 55331711 ps
CPU time 1.26 seconds
Started Oct 09 10:23:17 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495346908 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.1495346908
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.67201364
Short name T1043
Test name
Test status
Simulation time 207607269 ps
CPU time 2.44 seconds
Started Oct 09 10:23:17 AM UTC 24
Finished Oct 09 10:23:24 AM UTC 24
Peak memory 227160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67201364 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.67201364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1523541926
Short name T1034
Test name
Test status
Simulation time 59495608 ps
CPU time 1.92 seconds
Started Oct 09 10:23:17 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 224988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523541926 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1523541926
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3361080271
Short name T1048
Test name
Test status
Simulation time 35957446 ps
CPU time 1.23 seconds
Started Oct 09 10:23:22 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3361080271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3361080271
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.414501575
Short name T1041
Test name
Test status
Simulation time 34839648 ps
CPU time 0.91 seconds
Started Oct 09 10:23:21 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414501575 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.414501575
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.4136269739
Short name T995
Test name
Test status
Simulation time 35023369 ps
CPU time 0.88 seconds
Started Oct 09 10:23:21 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136269739 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4136269739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.281699254
Short name T1046
Test name
Test status
Simulation time 76396528 ps
CPU time 1.12 seconds
Started Oct 09 10:23:22 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281699254 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.281699254
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.3390708097
Short name T1036
Test name
Test status
Simulation time 29245043 ps
CPU time 1.74 seconds
Started Oct 09 10:23:18 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 224992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390708097 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3390708097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.673411175
Short name T1033
Test name
Test status
Simulation time 89311169 ps
CPU time 2.44 seconds
Started Oct 09 10:23:18 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 216840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673411175 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.673411175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2156333700
Short name T1050
Test name
Test status
Simulation time 48988127 ps
CPU time 1.19 seconds
Started Oct 09 10:23:23 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2156333700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2156333700
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.508630059
Short name T287
Test name
Test status
Simulation time 33347224 ps
CPU time 1.12 seconds
Started Oct 09 10:23:23 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508630059 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.508630059
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2614319916
Short name T1047
Test name
Test status
Simulation time 25995959 ps
CPU time 1.05 seconds
Started Oct 09 10:23:22 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614319916 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2614319916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2220016041
Short name T1049
Test name
Test status
Simulation time 155538175 ps
CPU time 1.1 seconds
Started Oct 09 10:23:23 AM UTC 24
Finished Oct 09 10:23:25 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220016041 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.2220016041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2015441149
Short name T1055
Test name
Test status
Simulation time 77582430 ps
CPU time 3.21 seconds
Started Oct 09 10:23:22 AM UTC 24
Finished Oct 09 10:23:27 AM UTC 24
Peak memory 227340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015441149 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2015441149
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.870568808
Short name T1054
Test name
Test status
Simulation time 132075401 ps
CPU time 1.4 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:27 AM UTC 24
Peak memory 224936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=870568808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.870568808
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3409338673
Short name T288
Test name
Test status
Simulation time 38481641 ps
CPU time 0.99 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:26 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409338673 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3409338673
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3508850517
Short name T1052
Test name
Test status
Simulation time 25284364 ps
CPU time 1.31 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:26 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508850517 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3508850517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.844771485
Short name T1053
Test name
Test status
Simulation time 36089752 ps
CPU time 1.58 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:27 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844771485 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.844771485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1770000199
Short name T1071
Test name
Test status
Simulation time 442529097 ps
CPU time 5.77 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:31 AM UTC 24
Peak memory 227212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770000199 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1770000199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.124685666
Short name T1057
Test name
Test status
Simulation time 388718706 ps
CPU time 2.17 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:27 AM UTC 24
Peak memory 216864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124685666 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.124685666
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3363593659
Short name T1059
Test name
Test status
Simulation time 130576013 ps
CPU time 1.03 seconds
Started Oct 09 10:23:25 AM UTC 24
Finished Oct 09 10:23:28 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3363593659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3363593659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1419061604
Short name T289
Test name
Test status
Simulation time 96761661 ps
CPU time 1.21 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:27 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419061604 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1419061604
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.176615760
Short name T1051
Test name
Test status
Simulation time 13979853 ps
CPU time 0.92 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:26 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176615760 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.176615760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.1165504616
Short name T1058
Test name
Test status
Simulation time 46563912 ps
CPU time 1 seconds
Started Oct 09 10:23:25 AM UTC 24
Finished Oct 09 10:23:28 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165504616 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.1165504616
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3891552534
Short name T1056
Test name
Test status
Simulation time 23254107 ps
CPU time 1.87 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:27 AM UTC 24
Peak memory 224992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891552534 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3891552534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.4121052919
Short name T1062
Test name
Test status
Simulation time 784952762 ps
CPU time 2.77 seconds
Started Oct 09 10:23:24 AM UTC 24
Finished Oct 09 10:23:28 AM UTC 24
Peak memory 227080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121052919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4121052919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.282188477
Short name T1067
Test name
Test status
Simulation time 48492687 ps
CPU time 1.62 seconds
Started Oct 09 10:23:27 AM UTC 24
Finished Oct 09 10:23:31 AM UTC 24
Peak memory 224936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=282188477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.282188477
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1169657548
Short name T1061
Test name
Test status
Simulation time 30610359 ps
CPU time 1.21 seconds
Started Oct 09 10:23:26 AM UTC 24
Finished Oct 09 10:23:28 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169657548 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1169657548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3121129314
Short name T1060
Test name
Test status
Simulation time 31735375 ps
CPU time 0.99 seconds
Started Oct 09 10:23:26 AM UTC 24
Finished Oct 09 10:23:28 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121129314 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3121129314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3261049277
Short name T1063
Test name
Test status
Simulation time 37774610 ps
CPU time 1.57 seconds
Started Oct 09 10:23:26 AM UTC 24
Finished Oct 09 10:23:28 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261049277 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.3261049277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.655702613
Short name T1064
Test name
Test status
Simulation time 57674147 ps
CPU time 2.36 seconds
Started Oct 09 10:23:25 AM UTC 24
Finished Oct 09 10:23:29 AM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655702613 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.655702613
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1744742077
Short name T320
Test name
Test status
Simulation time 48788146 ps
CPU time 1.97 seconds
Started Oct 09 10:23:25 AM UTC 24
Finished Oct 09 10:23:29 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744742077 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1744742077
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2174628237
Short name T1068
Test name
Test status
Simulation time 44690866 ps
CPU time 1.56 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:31 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2174628237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2174628237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.799709086
Short name T1109
Test name
Test status
Simulation time 26249881 ps
CPU time 1.06 seconds
Started Oct 09 10:23:27 AM UTC 24
Finished Oct 09 10:23:46 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799709086 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.799709086
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.654644774
Short name T1065
Test name
Test status
Simulation time 14744783 ps
CPU time 1.19 seconds
Started Oct 09 10:23:27 AM UTC 24
Finished Oct 09 10:23:30 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654644774 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.654644774
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1738110559
Short name T1094
Test name
Test status
Simulation time 71960871 ps
CPU time 1.51 seconds
Started Oct 09 10:23:27 AM UTC 24
Finished Oct 09 10:23:36 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738110559 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.1738110559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.2442966317
Short name T1075
Test name
Test status
Simulation time 361281298 ps
CPU time 2.66 seconds
Started Oct 09 10:23:27 AM UTC 24
Finished Oct 09 10:23:32 AM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442966317 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2442966317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3149415222
Short name T1073
Test name
Test status
Simulation time 294797978 ps
CPU time 2.57 seconds
Started Oct 09 10:23:27 AM UTC 24
Finished Oct 09 10:23:32 AM UTC 24
Peak memory 216848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149415222 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3149415222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2712327818
Short name T1070
Test name
Test status
Simulation time 88319097 ps
CPU time 1.59 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:31 AM UTC 24
Peak memory 224936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2712327818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2712327818
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.1261900839
Short name T290
Test name
Test status
Simulation time 20205445 ps
CPU time 0.97 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:30 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261900839 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1261900839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.929084372
Short name T1066
Test name
Test status
Simulation time 63487626 ps
CPU time 1.05 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:30 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929084372 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.929084372
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.738640711
Short name T1069
Test name
Test status
Simulation time 99281729 ps
CPU time 1.44 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:31 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738640711 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.738640711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.1775843700
Short name T1078
Test name
Test status
Simulation time 133453233 ps
CPU time 4.21 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:34 AM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775843700 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1775843700
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.3159486885
Short name T1074
Test name
Test status
Simulation time 499130885 ps
CPU time 2.31 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:32 AM UTC 24
Peak memory 217096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159486885 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3159486885
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.901352022
Short name T1081
Test name
Test status
Simulation time 72132550 ps
CPU time 1.23 seconds
Started Oct 09 10:23:30 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=901352022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.901352022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.4034827348
Short name T291
Test name
Test status
Simulation time 164591097 ps
CPU time 1.2 seconds
Started Oct 09 10:23:30 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034827348 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4034827348
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.4140070812
Short name T1072
Test name
Test status
Simulation time 24128512 ps
CPU time 1.14 seconds
Started Oct 09 10:23:29 AM UTC 24
Finished Oct 09 10:23:32 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140070812 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4140070812
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2916661249
Short name T1082
Test name
Test status
Simulation time 52550818 ps
CPU time 1.32 seconds
Started Oct 09 10:23:30 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916661249 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.2916661249
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3678656646
Short name T1079
Test name
Test status
Simulation time 691354906 ps
CPU time 3.95 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:34 AM UTC 24
Peak memory 227160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678656646 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3678656646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3537983937
Short name T1076
Test name
Test status
Simulation time 47504208 ps
CPU time 2.25 seconds
Started Oct 09 10:23:28 AM UTC 24
Finished Oct 09 10:23:32 AM UTC 24
Peak memory 216848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537983937 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3537983937
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.2008883383
Short name T282
Test name
Test status
Simulation time 86341735 ps
CPU time 1.79 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:22:59 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008883383 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2008883383
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.2590230131
Short name T994
Test name
Test status
Simulation time 113762745 ps
CPU time 3.39 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 216864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590230131 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2590230131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.1188826163
Short name T281
Test name
Test status
Simulation time 21215734 ps
CPU time 1.16 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:22:58 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188826163 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1188826163
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1264253551
Short name T993
Test name
Test status
Simulation time 35102210 ps
CPU time 1.77 seconds
Started Oct 09 10:22:57 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1264253551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1264253551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.1140718481
Short name T294
Test name
Test status
Simulation time 13875263 ps
CPU time 1.24 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:22:59 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140718481 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1140718481
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.476979450
Short name T988
Test name
Test status
Simulation time 16399923 ps
CPU time 1.36 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:22:59 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476979450 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.476979450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.2667623307
Short name T295
Test name
Test status
Simulation time 21133598 ps
CPU time 1.29 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:22:59 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667623307 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.2667623307
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.1540765156
Short name T992
Test name
Test status
Simulation time 183777531 ps
CPU time 4.2 seconds
Started Oct 09 10:22:55 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 227420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540765156 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1540765156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.1767695251
Short name T312
Test name
Test status
Simulation time 128645052 ps
CPU time 2.2 seconds
Started Oct 09 10:22:56 AM UTC 24
Finished Oct 09 10:22:59 AM UTC 24
Peak memory 216860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767695251 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1767695251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1311288774
Short name T1077
Test name
Test status
Simulation time 10754563 ps
CPU time 1.24 seconds
Started Oct 09 10:23:30 AM UTC 24
Finished Oct 09 10:23:32 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311288774 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1311288774
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3562903038
Short name T1080
Test name
Test status
Simulation time 15447328 ps
CPU time 0.94 seconds
Started Oct 09 10:23:30 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562903038 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3562903038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.4139665875
Short name T1108
Test name
Test status
Simulation time 49713675 ps
CPU time 1.02 seconds
Started Oct 09 10:23:31 AM UTC 24
Finished Oct 09 10:23:46 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139665875 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4139665875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.2439022112
Short name T1097
Test name
Test status
Simulation time 25054410 ps
CPU time 0.96 seconds
Started Oct 09 10:23:31 AM UTC 24
Finished Oct 09 10:23:40 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439022112 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2439022112
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.484975436
Short name T1096
Test name
Test status
Simulation time 15729382 ps
CPU time 1.05 seconds
Started Oct 09 10:23:31 AM UTC 24
Finished Oct 09 10:23:36 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484975436 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.484975436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1077511281
Short name T1083
Test name
Test status
Simulation time 39534239 ps
CPU time 0.98 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077511281 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1077511281
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.3480181659
Short name T1084
Test name
Test status
Simulation time 20622285 ps
CPU time 1.08 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480181659 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3480181659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3929809829
Short name T1085
Test name
Test status
Simulation time 38567132 ps
CPU time 0.98 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929809829 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3929809829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.2694311330
Short name T1086
Test name
Test status
Simulation time 11708279 ps
CPU time 1.05 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694311330 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2694311330
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.325045657
Short name T1087
Test name
Test status
Simulation time 20224130 ps
CPU time 1.16 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325045657 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.325045657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.2427615060
Short name T996
Test name
Test status
Simulation time 40135518 ps
CPU time 1.54 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427615060 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2427615060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.1157067886
Short name T1003
Test name
Test status
Simulation time 666376316 ps
CPU time 4.83 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:04 AM UTC 24
Peak memory 216792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157067886 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1157067886
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.1625705724
Short name T991
Test name
Test status
Simulation time 19895816 ps
CPU time 1.3 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625705724 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1625705724
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2736939074
Short name T1000
Test name
Test status
Simulation time 19146544 ps
CPU time 1.48 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:02 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2736939074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2736939074
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.3371497831
Short name T990
Test name
Test status
Simulation time 12146840 ps
CPU time 1.26 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:00 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371497831 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3371497831
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1766916781
Short name T296
Test name
Test status
Simulation time 45289917 ps
CPU time 1.23 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766916781 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1766916781
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.3926582019
Short name T1001
Test name
Test status
Simulation time 49418759 ps
CPU time 2.84 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:02 AM UTC 24
Peak memory 227208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926582019 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3926582019
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.1445545942
Short name T317
Test name
Test status
Simulation time 56447872 ps
CPU time 1.84 seconds
Started Oct 09 10:22:58 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445545942 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1445545942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2712450531
Short name T1090
Test name
Test status
Simulation time 13897451 ps
CPU time 1.04 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712450531 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2712450531
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.1966891930
Short name T1093
Test name
Test status
Simulation time 15029879 ps
CPU time 1.15 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:36 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966891930 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1966891930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3158166517
Short name T1088
Test name
Test status
Simulation time 15197908 ps
CPU time 0.98 seconds
Started Oct 09 10:23:32 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158166517 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3158166517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.4025784968
Short name T1089
Test name
Test status
Simulation time 61883501 ps
CPU time 0.99 seconds
Started Oct 09 10:23:33 AM UTC 24
Finished Oct 09 10:23:35 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025784968 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4025784968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.609851341
Short name T1091
Test name
Test status
Simulation time 24891812 ps
CPU time 0.96 seconds
Started Oct 09 10:23:33 AM UTC 24
Finished Oct 09 10:23:36 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609851341 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.609851341
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.909309191
Short name T1095
Test name
Test status
Simulation time 180918368 ps
CPU time 1.14 seconds
Started Oct 09 10:23:34 AM UTC 24
Finished Oct 09 10:23:36 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909309191 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.909309191
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3745723854
Short name T1092
Test name
Test status
Simulation time 29334983 ps
CPU time 0.88 seconds
Started Oct 09 10:23:34 AM UTC 24
Finished Oct 09 10:23:36 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745723854 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3745723854
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.4046933144
Short name T1110
Test name
Test status
Simulation time 12894537 ps
CPU time 0.8 seconds
Started Oct 09 10:23:35 AM UTC 24
Finished Oct 09 10:23:47 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046933144 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4046933144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2700300884
Short name T1111
Test name
Test status
Simulation time 27135890 ps
CPU time 0.99 seconds
Started Oct 09 10:23:35 AM UTC 24
Finished Oct 09 10:23:47 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700300884 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2700300884
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.472327581
Short name T1099
Test name
Test status
Simulation time 17131160 ps
CPU time 1.05 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472327581 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.472327581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.3923485339
Short name T1008
Test name
Test status
Simulation time 35720233 ps
CPU time 2.05 seconds
Started Oct 09 10:23:00 AM UTC 24
Finished Oct 09 10:23:07 AM UTC 24
Peak memory 216804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923485339 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3923485339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.19870084
Short name T285
Test name
Test status
Simulation time 223920118 ps
CPU time 3.24 seconds
Started Oct 09 10:23:00 AM UTC 24
Finished Oct 09 10:23:05 AM UTC 24
Peak memory 217052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19870084 -assert nopostproc +UVM_TESTNAME=edn_
base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ed
n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.19870084
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.3928132592
Short name T999
Test name
Test status
Simulation time 17235973 ps
CPU time 1.3 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928132592 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3928132592
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.136644272
Short name T1007
Test name
Test status
Simulation time 35083453 ps
CPU time 1.6 seconds
Started Oct 09 10:23:01 AM UTC 24
Finished Oct 09 10:23:07 AM UTC 24
Peak memory 224984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=136644272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.136644272
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2066810953
Short name T998
Test name
Test status
Simulation time 28239769 ps
CPU time 0.95 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066810953 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2066810953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.3215360582
Short name T997
Test name
Test status
Simulation time 13580132 ps
CPU time 1.06 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:01 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215360582 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3215360582
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.2736854568
Short name T297
Test name
Test status
Simulation time 26294283 ps
CPU time 1.26 seconds
Started Oct 09 10:23:00 AM UTC 24
Finished Oct 09 10:23:03 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736854568 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.2736854568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2331939201
Short name T1002
Test name
Test status
Simulation time 385725100 ps
CPU time 3.36 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:04 AM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331939201 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2331939201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.2364680892
Short name T318
Test name
Test status
Simulation time 79503946 ps
CPU time 1.66 seconds
Started Oct 09 10:22:59 AM UTC 24
Finished Oct 09 10:23:02 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364680892 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2364680892
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.3379588861
Short name T1098
Test name
Test status
Simulation time 32340023 ps
CPU time 0.83 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379588861 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3379588861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1629234688
Short name T1100
Test name
Test status
Simulation time 12995431 ps
CPU time 0.99 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629234688 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1629234688
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.3746496757
Short name T1103
Test name
Test status
Simulation time 15212113 ps
CPU time 1.16 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746496757 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3746496757
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.1326462293
Short name T1101
Test name
Test status
Simulation time 16940001 ps
CPU time 1.04 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326462293 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1326462293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.4120583124
Short name T1106
Test name
Test status
Simulation time 43922373 ps
CPU time 1.12 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120583124 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4120583124
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.1045128672
Short name T1107
Test name
Test status
Simulation time 41146517 ps
CPU time 1.1 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045128672 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1045128672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3213203895
Short name T1105
Test name
Test status
Simulation time 22811734 ps
CPU time 1.02 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213203895 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3213203895
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3148761157
Short name T1102
Test name
Test status
Simulation time 44075894 ps
CPU time 0.88 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148761157 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3148761157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.239894261
Short name T1104
Test name
Test status
Simulation time 15716666 ps
CPU time 1 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:41 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239894261 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.239894261
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.3408104772
Short name T1112
Test name
Test status
Simulation time 31480818 ps
CPU time 0.85 seconds
Started Oct 09 10:23:36 AM UTC 24
Finished Oct 09 10:23:51 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408104772 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3408104772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2740865374
Short name T1038
Test name
Test status
Simulation time 21932026 ps
CPU time 1.93 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 225000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2740865374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2740865374
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.3762982092
Short name T284
Test name
Test status
Simulation time 37954357 ps
CPU time 0.81 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:21 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762982092 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3762982092
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3470327654
Short name T1027
Test name
Test status
Simulation time 64535798 ps
CPU time 1.16 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:21 AM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470327654 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3470327654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.1374755816
Short name T1035
Test name
Test status
Simulation time 24536252 ps
CPU time 1.64 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374755816 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.1374755816
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.556376038
Short name T1010
Test name
Test status
Simulation time 247502682 ps
CPU time 2.58 seconds
Started Oct 09 10:23:01 AM UTC 24
Finished Oct 09 10:23:08 AM UTC 24
Peak memory 227188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556376038 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.556376038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.4041309904
Short name T1015
Test name
Test status
Simulation time 80189375 ps
CPU time 2.35 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:12 AM UTC 24
Peak memory 217040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041309904 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4041309904
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1863964297
Short name T1005
Test name
Test status
Simulation time 17413043 ps
CPU time 1.09 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:06 AM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1863964297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1863964297
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.3389755000
Short name T1029
Test name
Test status
Simulation time 28877019 ps
CPU time 1.05 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389755000 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3389755000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.952763370
Short name T1031
Test name
Test status
Simulation time 10876128 ps
CPU time 1.2 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952763370 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.952763370
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.2866127316
Short name T298
Test name
Test status
Simulation time 371502987 ps
CPU time 1.24 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:06 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866127316 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.2866127316
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2972438943
Short name T1044
Test name
Test status
Simulation time 73431240 ps
CPU time 3.44 seconds
Started Oct 09 10:23:02 AM UTC 24
Finished Oct 09 10:23:24 AM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972438943 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2972438943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3948508527
Short name T1026
Test name
Test status
Simulation time 31324506 ps
CPU time 1.25 seconds
Started Oct 09 10:23:05 AM UTC 24
Finished Oct 09 10:23:20 AM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3948508527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3948508527
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1201069909
Short name T286
Test name
Test status
Simulation time 38933237 ps
CPU time 0.96 seconds
Started Oct 09 10:23:04 AM UTC 24
Finished Oct 09 10:23:06 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201069909 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1201069909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.4042061611
Short name T1004
Test name
Test status
Simulation time 42869524 ps
CPU time 1 seconds
Started Oct 09 10:23:03 AM UTC 24
Finished Oct 09 10:23:06 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042061611 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4042061611
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1173931709
Short name T1006
Test name
Test status
Simulation time 22832038 ps
CPU time 1.31 seconds
Started Oct 09 10:23:04 AM UTC 24
Finished Oct 09 10:23:07 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173931709 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.1173931709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.3720142937
Short name T1011
Test name
Test status
Simulation time 361109138 ps
CPU time 3.15 seconds
Started Oct 09 10:23:03 AM UTC 24
Finished Oct 09 10:23:08 AM UTC 24
Peak memory 227148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720142937 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3720142937
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3303288051
Short name T1009
Test name
Test status
Simulation time 56915092 ps
CPU time 2.11 seconds
Started Oct 09 10:23:03 AM UTC 24
Finished Oct 09 10:23:07 AM UTC 24
Peak memory 216848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303288051 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3303288051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2276045716
Short name T1023
Test name
Test status
Simulation time 78568129 ps
CPU time 1.51 seconds
Started Oct 09 10:23:07 AM UTC 24
Finished Oct 09 10:23:17 AM UTC 24
Peak memory 224996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2276045716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2276045716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2814592928
Short name T1021
Test name
Test status
Simulation time 16231813 ps
CPU time 1.12 seconds
Started Oct 09 10:23:07 AM UTC 24
Finished Oct 09 10:23:16 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814592928 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2814592928
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.391945307
Short name T1020
Test name
Test status
Simulation time 21682625 ps
CPU time 1.09 seconds
Started Oct 09 10:23:07 AM UTC 24
Finished Oct 09 10:23:16 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391945307 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.391945307
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2355564180
Short name T1022
Test name
Test status
Simulation time 67518165 ps
CPU time 1.25 seconds
Started Oct 09 10:23:07 AM UTC 24
Finished Oct 09 10:23:16 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355564180 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.2355564180
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2301310186
Short name T1028
Test name
Test status
Simulation time 198053590 ps
CPU time 2.51 seconds
Started Oct 09 10:23:05 AM UTC 24
Finished Oct 09 10:23:21 AM UTC 24
Peak memory 227152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301310186 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2301310186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3163175987
Short name T322
Test name
Test status
Simulation time 58579942 ps
CPU time 1.78 seconds
Started Oct 09 10:23:06 AM UTC 24
Finished Oct 09 10:23:12 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163175987 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3163175987
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2602406769
Short name T1030
Test name
Test status
Simulation time 47306354 ps
CPU time 1.05 seconds
Started Oct 09 10:23:09 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 224916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2602406769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2602406769
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.645280753
Short name T1012
Test name
Test status
Simulation time 33870644 ps
CPU time 0.86 seconds
Started Oct 09 10:23:08 AM UTC 24
Finished Oct 09 10:23:10 AM UTC 24
Peak memory 214524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645280753 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.645280753
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.53396898
Short name T1019
Test name
Test status
Simulation time 43480413 ps
CPU time 0.98 seconds
Started Oct 09 10:23:08 AM UTC 24
Finished Oct 09 10:23:22 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53396898 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.53396898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3201545124
Short name T1013
Test name
Test status
Simulation time 46619471 ps
CPU time 1.04 seconds
Started Oct 09 10:23:08 AM UTC 24
Finished Oct 09 10:23:10 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201545124 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.3201545124
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.341459852
Short name T1014
Test name
Test status
Simulation time 56022191 ps
CPU time 2.29 seconds
Started Oct 09 10:23:08 AM UTC 24
Finished Oct 09 10:23:11 AM UTC 24
Peak memory 227060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341459852 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.341459852
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1784583402
Short name T1039
Test name
Test status
Simulation time 308490145 ps
CPU time 2.21 seconds
Started Oct 09 10:23:08 AM UTC 24
Finished Oct 09 10:23:23 AM UTC 24
Peak memory 227164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784583402 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1784583402
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_err.761966583
Short name T5
Test name
Test status
Simulation time 18606170 ps
CPU time 1.22 seconds
Started Oct 09 10:17:59 AM UTC 24
Finished Oct 09 10:18:01 AM UTC 24
Peak memory 238244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761966583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.edn_err.761966583
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_genbits.2165557019
Short name T3
Test name
Test status
Simulation time 54053242 ps
CPU time 1.74 seconds
Started Oct 09 10:17:56 AM UTC 24
Finished Oct 09 10:17:59 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165557019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2165557019
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_regwen.1018264696
Short name T2
Test name
Test status
Simulation time 39370128 ps
CPU time 1.23 seconds
Started Oct 09 10:17:56 AM UTC 24
Finished Oct 09 10:17:58 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018264696 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.1018264696
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/0.edn_smoke.3094942008
Short name T1
Test name
Test status
Simulation time 30213086 ps
CPU time 1.23 seconds
Started Oct 09 10:17:55 AM UTC 24
Finished Oct 09 10:17:57 AM UTC 24
Peak memory 217232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094942008 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_smoke.3094942008
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_alert.3414243959
Short name T19
Test name
Test status
Simulation time 57472693 ps
CPU time 1.44 seconds
Started Oct 09 10:18:02 AM UTC 24
Finished Oct 09 10:18:05 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414243959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.3414243959
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_alert_test.681792655
Short name T64
Test name
Test status
Simulation time 13515317 ps
CPU time 1.32 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:18:06 AM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681792655 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.681792655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_disable.2024715062
Short name T28
Test name
Test status
Simulation time 16220028 ps
CPU time 1.18 seconds
Started Oct 09 10:18:03 AM UTC 24
Finished Oct 09 10:18:05 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024715062 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2024715062
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.425838220
Short name T11
Test name
Test status
Simulation time 37188857 ps
CPU time 1.92 seconds
Started Oct 09 10:18:03 AM UTC 24
Finished Oct 09 10:18:06 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425838220 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.425838220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_err.544543059
Short name T32
Test name
Test status
Simulation time 18031528 ps
CPU time 1.42 seconds
Started Oct 09 10:18:03 AM UTC 24
Finished Oct 09 10:18:05 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544543059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.edn_err.544543059
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_intr.428081858
Short name T31
Test name
Test status
Simulation time 20257001 ps
CPU time 1.61 seconds
Started Oct 09 10:18:02 AM UTC 24
Finished Oct 09 10:18:05 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428081858 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.428081858
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_regwen.2711491226
Short name T27
Test name
Test status
Simulation time 28817360 ps
CPU time 1.19 seconds
Started Oct 09 10:18:01 AM UTC 24
Finished Oct 09 10:18:03 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711491226 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.2711491226
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_sec_cm.4175370502
Short name T18
Test name
Test status
Simulation time 1104191616 ps
CPU time 5.5 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:18:11 AM UTC 24
Peak memory 258748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175370502 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4175370502
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_smoke.1012649012
Short name T37
Test name
Test status
Simulation time 50757718 ps
CPU time 1.21 seconds
Started Oct 09 10:18:01 AM UTC 24
Finished Oct 09 10:18:03 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012649012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.1012649012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/1.edn_stress_all.319663630
Short name T56
Test name
Test status
Simulation time 277418195 ps
CPU time 5.89 seconds
Started Oct 09 10:18:02 AM UTC 24
Finished Oct 09 10:18:09 AM UTC 24
Peak memory 229948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319663630 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.319663630
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_alert_test.426680751
Short name T371
Test name
Test status
Simulation time 47192865 ps
CPU time 1.28 seconds
Started Oct 09 10:18:28 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 227196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426680751 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.426680751
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_disable.1119836742
Short name T71
Test name
Test status
Simulation time 21375427 ps
CPU time 1.13 seconds
Started Oct 09 10:18:27 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119836742 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1119836742
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_intr.377106596
Short name T370
Test name
Test status
Simulation time 40660108 ps
CPU time 1.5 seconds
Started Oct 09 10:18:27 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 236192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377106596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.377106596
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/10.edn_smoke.3605170338
Short name T369
Test name
Test status
Simulation time 16690240 ps
CPU time 1.16 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:28 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605170338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.3605170338
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/100.edn_genbits.3188442515
Short name T692
Test name
Test status
Simulation time 72987493 ps
CPU time 1.59 seconds
Started Oct 09 10:21:47 AM UTC 24
Finished Oct 09 10:21:50 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188442515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3188442515
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/101.edn_alert.2053997035
Short name T174
Test name
Test status
Simulation time 74372373 ps
CPU time 1.74 seconds
Started Oct 09 10:21:48 AM UTC 24
Finished Oct 09 10:21:51 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053997035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 101.edn_alert.2053997035
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/101.edn_genbits.568869903
Short name T697
Test name
Test status
Simulation time 146045535 ps
CPU time 2.89 seconds
Started Oct 09 10:21:48 AM UTC 24
Finished Oct 09 10:21:52 AM UTC 24
Peak memory 232308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568869903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 101.edn_genbits.568869903
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/102.edn_alert.3162878843
Short name T696
Test name
Test status
Simulation time 56617552 ps
CPU time 2.04 seconds
Started Oct 09 10:21:49 AM UTC 24
Finished Oct 09 10:21:52 AM UTC 24
Peak memory 232856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162878843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.3162878843
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/102.edn_genbits.2214211900
Short name T695
Test name
Test status
Simulation time 92819395 ps
CPU time 1.59 seconds
Started Oct 09 10:21:49 AM UTC 24
Finished Oct 09 10:21:51 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214211900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2214211900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/103.edn_alert.2550962758
Short name T698
Test name
Test status
Simulation time 93146045 ps
CPU time 1.47 seconds
Started Oct 09 10:21:50 AM UTC 24
Finished Oct 09 10:21:53 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550962758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.2550962758
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/104.edn_alert.685719062
Short name T276
Test name
Test status
Simulation time 87756754 ps
CPU time 1.77 seconds
Started Oct 09 10:21:50 AM UTC 24
Finished Oct 09 10:21:53 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685719062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 104.edn_alert.685719062
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/104.edn_genbits.4227379921
Short name T700
Test name
Test status
Simulation time 55048502 ps
CPU time 1.96 seconds
Started Oct 09 10:21:50 AM UTC 24
Finished Oct 09 10:21:53 AM UTC 24
Peak memory 229272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227379921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4227379921
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/105.edn_genbits.455067021
Short name T705
Test name
Test status
Simulation time 393809388 ps
CPU time 3.28 seconds
Started Oct 09 10:21:50 AM UTC 24
Finished Oct 09 10:21:55 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455067021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 105.edn_genbits.455067021
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/106.edn_alert.1555448834
Short name T703
Test name
Test status
Simulation time 45502053 ps
CPU time 1.64 seconds
Started Oct 09 10:21:51 AM UTC 24
Finished Oct 09 10:21:54 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555448834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.1555448834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/106.edn_genbits.330771899
Short name T704
Test name
Test status
Simulation time 67640722 ps
CPU time 1.71 seconds
Started Oct 09 10:21:51 AM UTC 24
Finished Oct 09 10:21:54 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330771899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 106.edn_genbits.330771899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/107.edn_genbits.255352201
Short name T702
Test name
Test status
Simulation time 70939271 ps
CPU time 1.61 seconds
Started Oct 09 10:21:51 AM UTC 24
Finished Oct 09 10:21:54 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255352201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 107.edn_genbits.255352201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/108.edn_alert.3318291902
Short name T709
Test name
Test status
Simulation time 50773146 ps
CPU time 1.87 seconds
Started Oct 09 10:21:52 AM UTC 24
Finished Oct 09 10:21:56 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318291902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.edn_alert.3318291902
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/108.edn_genbits.3417744325
Short name T706
Test name
Test status
Simulation time 47765393 ps
CPU time 2.19 seconds
Started Oct 09 10:21:51 AM UTC 24
Finished Oct 09 10:21:55 AM UTC 24
Peak memory 228180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417744325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3417744325
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/109.edn_alert.2299358106
Short name T707
Test name
Test status
Simulation time 69812161 ps
CPU time 1.59 seconds
Started Oct 09 10:21:53 AM UTC 24
Finished Oct 09 10:21:55 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299358106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.2299358106
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/109.edn_genbits.485795594
Short name T711
Test name
Test status
Simulation time 78666336 ps
CPU time 2.21 seconds
Started Oct 09 10:21:53 AM UTC 24
Finished Oct 09 10:21:56 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485795594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 109.edn_genbits.485795594
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_alert.601403562
Short name T51
Test name
Test status
Simulation time 31565729 ps
CPU time 1.55 seconds
Started Oct 09 10:18:29 AM UTC 24
Finished Oct 09 10:18:32 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601403562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.edn_alert.601403562
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_alert_test.459173339
Short name T375
Test name
Test status
Simulation time 22328585 ps
CPU time 1.15 seconds
Started Oct 09 10:18:29 AM UTC 24
Finished Oct 09 10:18:32 AM UTC 24
Peak memory 216916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459173339 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.459173339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_disable.3746603536
Short name T94
Test name
Test status
Simulation time 39904433 ps
CPU time 1.04 seconds
Started Oct 09 10:18:29 AM UTC 24
Finished Oct 09 10:18:32 AM UTC 24
Peak memory 226668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746603536 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3746603536
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_err.2337041897
Short name T373
Test name
Test status
Simulation time 20886930 ps
CPU time 1.27 seconds
Started Oct 09 10:18:29 AM UTC 24
Finished Oct 09 10:18:32 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337041897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.2337041897
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_genbits.2027479026
Short name T313
Test name
Test status
Simulation time 132766156 ps
CPU time 1.31 seconds
Started Oct 09 10:18:28 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027479026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2027479026
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_intr.3544626451
Short name T374
Test name
Test status
Simulation time 26972137 ps
CPU time 1.46 seconds
Started Oct 09 10:18:29 AM UTC 24
Finished Oct 09 10:18:32 AM UTC 24
Peak memory 237192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544626451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.3544626451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_smoke.2632983491
Short name T372
Test name
Test status
Simulation time 49378137 ps
CPU time 1.21 seconds
Started Oct 09 10:18:28 AM UTC 24
Finished Oct 09 10:18:30 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632983491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.2632983491
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_stress_all.183659293
Short name T112
Test name
Test status
Simulation time 313866030 ps
CPU time 4.33 seconds
Started Oct 09 10:18:28 AM UTC 24
Finished Oct 09 10:18:33 AM UTC 24
Peak memory 228068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183659293 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.183659293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.1259450934
Short name T40
Test name
Test status
Simulation time 10767932024 ps
CPU time 36.01 seconds
Started Oct 09 10:18:28 AM UTC 24
Finished Oct 09 10:19:06 AM UTC 24
Peak memory 228384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1259450934 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all
_with_rand_reset.1259450934
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/110.edn_alert.1201800591
Short name T716
Test name
Test status
Simulation time 396557815 ps
CPU time 2.6 seconds
Started Oct 09 10:21:54 AM UTC 24
Finished Oct 09 10:21:58 AM UTC 24
Peak memory 232660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201800591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.1201800591
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/110.edn_genbits.4138823440
Short name T708
Test name
Test status
Simulation time 66423267 ps
CPU time 1.54 seconds
Started Oct 09 10:21:53 AM UTC 24
Finished Oct 09 10:21:55 AM UTC 24
Peak memory 229200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138823440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4138823440
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/111.edn_alert.517885646
Short name T714
Test name
Test status
Simulation time 57066018 ps
CPU time 1.8 seconds
Started Oct 09 10:21:54 AM UTC 24
Finished Oct 09 10:21:57 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517885646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 111.edn_alert.517885646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/112.edn_alert.3403754542
Short name T713
Test name
Test status
Simulation time 26454746 ps
CPU time 1.29 seconds
Started Oct 09 10:21:54 AM UTC 24
Finished Oct 09 10:21:57 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403754542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.3403754542
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/112.edn_genbits.1853078794
Short name T715
Test name
Test status
Simulation time 61515265 ps
CPU time 1.99 seconds
Started Oct 09 10:21:54 AM UTC 24
Finished Oct 09 10:21:57 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853078794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1853078794
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/113.edn_alert.1862672741
Short name T720
Test name
Test status
Simulation time 21680815 ps
CPU time 1.71 seconds
Started Oct 09 10:21:55 AM UTC 24
Finished Oct 09 10:21:58 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862672741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.1862672741
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/113.edn_genbits.3532262615
Short name T718
Test name
Test status
Simulation time 67967303 ps
CPU time 1.48 seconds
Started Oct 09 10:21:55 AM UTC 24
Finished Oct 09 10:21:58 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532262615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3532262615
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/114.edn_genbits.2666982829
Short name T721
Test name
Test status
Simulation time 37327887 ps
CPU time 2.09 seconds
Started Oct 09 10:21:55 AM UTC 24
Finished Oct 09 10:21:58 AM UTC 24
Peak memory 230300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666982829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2666982829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/115.edn_alert.3434356064
Short name T722
Test name
Test status
Simulation time 61840398 ps
CPU time 1.64 seconds
Started Oct 09 10:21:56 AM UTC 24
Finished Oct 09 10:21:59 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434356064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.3434356064
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/115.edn_genbits.196902978
Short name T719
Test name
Test status
Simulation time 86491057 ps
CPU time 1.43 seconds
Started Oct 09 10:21:55 AM UTC 24
Finished Oct 09 10:21:58 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196902978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 115.edn_genbits.196902978
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/116.edn_alert.3530336538
Short name T723
Test name
Test status
Simulation time 67974205 ps
CPU time 1.59 seconds
Started Oct 09 10:21:57 AM UTC 24
Finished Oct 09 10:21:59 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530336538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.3530336538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/116.edn_genbits.3609427512
Short name T726
Test name
Test status
Simulation time 34792686 ps
CPU time 1.97 seconds
Started Oct 09 10:21:57 AM UTC 24
Finished Oct 09 10:22:00 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609427512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3609427512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/117.edn_alert.3011752479
Short name T724
Test name
Test status
Simulation time 47640027 ps
CPU time 1.71 seconds
Started Oct 09 10:21:57 AM UTC 24
Finished Oct 09 10:22:00 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011752479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.3011752479
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/117.edn_genbits.3733089620
Short name T332
Test name
Test status
Simulation time 108024724 ps
CPU time 3.35 seconds
Started Oct 09 10:21:57 AM UTC 24
Finished Oct 09 10:22:01 AM UTC 24
Peak memory 232100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733089620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3733089620
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/118.edn_alert.1767790116
Short name T730
Test name
Test status
Simulation time 54614339 ps
CPU time 1.71 seconds
Started Oct 09 10:21:58 AM UTC 24
Finished Oct 09 10:22:01 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767790116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.1767790116
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/118.edn_genbits.3336594766
Short name T727
Test name
Test status
Simulation time 85987258 ps
CPU time 2.03 seconds
Started Oct 09 10:21:57 AM UTC 24
Finished Oct 09 10:22:00 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336594766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3336594766
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/119.edn_alert.3279068288
Short name T729
Test name
Test status
Simulation time 26770226 ps
CPU time 1.46 seconds
Started Oct 09 10:21:58 AM UTC 24
Finished Oct 09 10:22:01 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279068288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.3279068288
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/119.edn_genbits.3694251744
Short name T731
Test name
Test status
Simulation time 82548899 ps
CPU time 2.04 seconds
Started Oct 09 10:21:58 AM UTC 24
Finished Oct 09 10:22:01 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694251744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3694251744
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_alert_test.1046019309
Short name T377
Test name
Test status
Simulation time 15752022 ps
CPU time 1.1 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:34 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046019309 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1046019309
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_disable.2385809127
Short name T99
Test name
Test status
Simulation time 41166100 ps
CPU time 1.18 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:34 AM UTC 24
Peak memory 216792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385809127 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2385809127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_err.2807417819
Short name T164
Test name
Test status
Simulation time 34878634 ps
CPU time 1.62 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:35 AM UTC 24
Peak memory 248512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807417819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.2807417819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_genbits.1998878576
Short name T316
Test name
Test status
Simulation time 327647473 ps
CPU time 1.15 seconds
Started Oct 09 10:18:30 AM UTC 24
Finished Oct 09 10:18:33 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998878576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1998878576
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_intr.3574996439
Short name T80
Test name
Test status
Simulation time 35905134 ps
CPU time 1.16 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:34 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574996439 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.3574996439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_smoke.4078149635
Short name T376
Test name
Test status
Simulation time 38642388 ps
CPU time 1.15 seconds
Started Oct 09 10:18:30 AM UTC 24
Finished Oct 09 10:18:33 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078149635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.4078149635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/12.edn_stress_all.3023252962
Short name T113
Test name
Test status
Simulation time 594460322 ps
CPU time 4.61 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:38 AM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023252962 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3023252962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/120.edn_alert.3295835396
Short name T736
Test name
Test status
Simulation time 28801138 ps
CPU time 1.9 seconds
Started Oct 09 10:21:59 AM UTC 24
Finished Oct 09 10:22:02 AM UTC 24
Peak memory 230984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295835396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.3295835396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/120.edn_genbits.3788396723
Short name T732
Test name
Test status
Simulation time 75378766 ps
CPU time 1.87 seconds
Started Oct 09 10:21:58 AM UTC 24
Finished Oct 09 10:22:01 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788396723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3788396723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/121.edn_alert.329758457
Short name T735
Test name
Test status
Simulation time 27680711 ps
CPU time 1.81 seconds
Started Oct 09 10:21:59 AM UTC 24
Finished Oct 09 10:22:02 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329758457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 121.edn_alert.329758457
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/121.edn_genbits.1896619018
Short name T733
Test name
Test status
Simulation time 136556925 ps
CPU time 1.6 seconds
Started Oct 09 10:21:59 AM UTC 24
Finished Oct 09 10:22:02 AM UTC 24
Peak memory 228976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896619018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1896619018
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/122.edn_alert.2945977379
Short name T734
Test name
Test status
Simulation time 23871164 ps
CPU time 1.43 seconds
Started Oct 09 10:21:59 AM UTC 24
Finished Oct 09 10:22:02 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945977379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 122.edn_alert.2945977379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/122.edn_genbits.2016860971
Short name T737
Test name
Test status
Simulation time 73070937 ps
CPU time 1.91 seconds
Started Oct 09 10:21:59 AM UTC 24
Finished Oct 09 10:22:02 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016860971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2016860971
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/123.edn_alert.1042359713
Short name T741
Test name
Test status
Simulation time 23983697 ps
CPU time 1.85 seconds
Started Oct 09 10:22:01 AM UTC 24
Finished Oct 09 10:22:04 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042359713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.1042359713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/124.edn_alert.2190937243
Short name T738
Test name
Test status
Simulation time 62874328 ps
CPU time 1.52 seconds
Started Oct 09 10:22:01 AM UTC 24
Finished Oct 09 10:22:03 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190937243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.2190937243
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/124.edn_genbits.3271100222
Short name T739
Test name
Test status
Simulation time 70994683 ps
CPU time 1.76 seconds
Started Oct 09 10:22:01 AM UTC 24
Finished Oct 09 10:22:03 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271100222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3271100222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/125.edn_alert.1357898812
Short name T740
Test name
Test status
Simulation time 43848549 ps
CPU time 1.59 seconds
Started Oct 09 10:22:01 AM UTC 24
Finished Oct 09 10:22:04 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357898812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.1357898812
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/125.edn_genbits.2123191833
Short name T742
Test name
Test status
Simulation time 48611158 ps
CPU time 1.91 seconds
Started Oct 09 10:22:01 AM UTC 24
Finished Oct 09 10:22:04 AM UTC 24
Peak memory 228932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123191833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2123191833
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/126.edn_alert.3936602461
Short name T744
Test name
Test status
Simulation time 85717018 ps
CPU time 1.33 seconds
Started Oct 09 10:22:02 AM UTC 24
Finished Oct 09 10:22:04 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936602461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.3936602461
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/126.edn_genbits.2210280834
Short name T743
Test name
Test status
Simulation time 147089503 ps
CPU time 2.18 seconds
Started Oct 09 10:22:01 AM UTC 24
Finished Oct 09 10:22:04 AM UTC 24
Peak memory 230316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210280834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2210280834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/127.edn_alert.950180994
Short name T745
Test name
Test status
Simulation time 23372533 ps
CPU time 1.5 seconds
Started Oct 09 10:22:02 AM UTC 24
Finished Oct 09 10:22:05 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950180994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 127.edn_alert.950180994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/127.edn_genbits.2904593307
Short name T747
Test name
Test status
Simulation time 73490076 ps
CPU time 1.77 seconds
Started Oct 09 10:22:02 AM UTC 24
Finished Oct 09 10:22:05 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904593307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2904593307
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/128.edn_alert.2652261221
Short name T746
Test name
Test status
Simulation time 86909427 ps
CPU time 1.43 seconds
Started Oct 09 10:22:02 AM UTC 24
Finished Oct 09 10:22:05 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652261221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.2652261221
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/128.edn_genbits.1259454705
Short name T749
Test name
Test status
Simulation time 74745630 ps
CPU time 2.41 seconds
Started Oct 09 10:22:02 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259454705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1259454705
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/129.edn_genbits.920989571
Short name T755
Test name
Test status
Simulation time 44976975 ps
CPU time 2.16 seconds
Started Oct 09 10:22:03 AM UTC 24
Finished Oct 09 10:22:07 AM UTC 24
Peak memory 230224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920989571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 129.edn_genbits.920989571
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_alert.589987598
Short name T100
Test name
Test status
Simulation time 127245744 ps
CPU time 1.52 seconds
Started Oct 09 10:18:33 AM UTC 24
Finished Oct 09 10:18:36 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589987598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_alert.589987598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_alert_test.1635485634
Short name T380
Test name
Test status
Simulation time 16795652 ps
CPU time 1.33 seconds
Started Oct 09 10:18:35 AM UTC 24
Finished Oct 09 10:18:38 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635485634 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1635485634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.1005813383
Short name T95
Test name
Test status
Simulation time 82744775 ps
CPU time 1.44 seconds
Started Oct 09 10:18:35 AM UTC 24
Finished Oct 09 10:18:38 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005813383 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.1005813383
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_err.2582872866
Short name T165
Test name
Test status
Simulation time 40513129 ps
CPU time 1.14 seconds
Started Oct 09 10:18:33 AM UTC 24
Finished Oct 09 10:18:36 AM UTC 24
Peak memory 238300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582872866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.2582872866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_genbits.1472080461
Short name T356
Test name
Test status
Simulation time 41989934 ps
CPU time 1.56 seconds
Started Oct 09 10:18:33 AM UTC 24
Finished Oct 09 10:18:36 AM UTC 24
Peak memory 229220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472080461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1472080461
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_intr.2661916615
Short name T44
Test name
Test status
Simulation time 29238221 ps
CPU time 1.16 seconds
Started Oct 09 10:18:33 AM UTC 24
Finished Oct 09 10:18:36 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661916615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.2661916615
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_smoke.4157611819
Short name T378
Test name
Test status
Simulation time 16208571 ps
CPU time 1.3 seconds
Started Oct 09 10:18:32 AM UTC 24
Finished Oct 09 10:18:35 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157611819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.4157611819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/13.edn_stress_all.1299373038
Short name T379
Test name
Test status
Simulation time 95958313 ps
CPU time 2.48 seconds
Started Oct 09 10:18:33 AM UTC 24
Finished Oct 09 10:18:37 AM UTC 24
Peak memory 228008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299373038 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1299373038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/130.edn_genbits.2886314695
Short name T750
Test name
Test status
Simulation time 174174288 ps
CPU time 1.39 seconds
Started Oct 09 10:22:03 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886314695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2886314695
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/131.edn_alert.109046322
Short name T753
Test name
Test status
Simulation time 36185680 ps
CPU time 1.54 seconds
Started Oct 09 10:22:04 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109046322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 131.edn_alert.109046322
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/131.edn_genbits.2087993994
Short name T754
Test name
Test status
Simulation time 34321967 ps
CPU time 1.85 seconds
Started Oct 09 10:22:04 AM UTC 24
Finished Oct 09 10:22:07 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087993994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2087993994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/132.edn_alert.3098350383
Short name T756
Test name
Test status
Simulation time 42129796 ps
CPU time 1.49 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:07 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098350383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.3098350383
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/132.edn_genbits.2463087836
Short name T764
Test name
Test status
Simulation time 127905267 ps
CPU time 3.27 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 232160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463087836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2463087836
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/133.edn_alert.2373498999
Short name T758
Test name
Test status
Simulation time 65679466 ps
CPU time 1.44 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:07 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373498999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 133.edn_alert.2373498999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/133.edn_genbits.1375257201
Short name T760
Test name
Test status
Simulation time 62001025 ps
CPU time 2.37 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:08 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375257201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1375257201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/134.edn_alert.697697744
Short name T759
Test name
Test status
Simulation time 48760114 ps
CPU time 1.31 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:08 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697697744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 134.edn_alert.697697744
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/134.edn_genbits.766155289
Short name T757
Test name
Test status
Simulation time 69390287 ps
CPU time 1.29 seconds
Started Oct 09 10:22:05 AM UTC 24
Finished Oct 09 10:22:07 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766155289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 134.edn_genbits.766155289
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/135.edn_alert.3677921524
Short name T761
Test name
Test status
Simulation time 44657495 ps
CPU time 1.13 seconds
Started Oct 09 10:22:06 AM UTC 24
Finished Oct 09 10:22:08 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677921524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.3677921524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/136.edn_alert.1448817632
Short name T762
Test name
Test status
Simulation time 121254785 ps
CPU time 1.43 seconds
Started Oct 09 10:22:06 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448817632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.1448817632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/136.edn_genbits.2161824077
Short name T763
Test name
Test status
Simulation time 28483387 ps
CPU time 1.64 seconds
Started Oct 09 10:22:06 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161824077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2161824077
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/137.edn_alert.3126950131
Short name T766
Test name
Test status
Simulation time 36248191 ps
CPU time 1.68 seconds
Started Oct 09 10:22:07 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126950131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.3126950131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/137.edn_genbits.817026475
Short name T765
Test name
Test status
Simulation time 41461872 ps
CPU time 1.61 seconds
Started Oct 09 10:22:06 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817026475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 137.edn_genbits.817026475
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/138.edn_alert.2930233174
Short name T767
Test name
Test status
Simulation time 164424298 ps
CPU time 1.71 seconds
Started Oct 09 10:22:07 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930233174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.2930233174
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/138.edn_genbits.243722367
Short name T768
Test name
Test status
Simulation time 63194012 ps
CPU time 1.81 seconds
Started Oct 09 10:22:07 AM UTC 24
Finished Oct 09 10:22:09 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243722367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 138.edn_genbits.243722367
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/139.edn_alert.2208119309
Short name T770
Test name
Test status
Simulation time 35628645 ps
CPU time 1.54 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:10 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208119309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.2208119309
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/139.edn_genbits.2931088099
Short name T769
Test name
Test status
Simulation time 85402458 ps
CPU time 1.13 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:10 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931088099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2931088099
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_alert.2133406218
Short name T229
Test name
Test status
Simulation time 70928092 ps
CPU time 1.55 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:39 AM UTC 24
Peak memory 229008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133406218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.2133406218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_alert_test.1677975923
Short name T382
Test name
Test status
Simulation time 130196115 ps
CPU time 1.12 seconds
Started Oct 09 10:18:37 AM UTC 24
Finished Oct 09 10:18:40 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677975923 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1677975923
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_genbits.1709615242
Short name T72
Test name
Test status
Simulation time 44161989 ps
CPU time 2.21 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:40 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709615242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1709615242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_intr.2976573130
Short name T109
Test name
Test status
Simulation time 19620605 ps
CPU time 1.5 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:39 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976573130 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.2976573130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_smoke.1093751807
Short name T381
Test name
Test status
Simulation time 44914679 ps
CPU time 1.11 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:39 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093751807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.1093751807
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_stress_all.3418292115
Short name T266
Test name
Test status
Simulation time 886902400 ps
CPU time 5.04 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:18:43 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418292115 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3418292115
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.48945983
Short name T512
Test name
Test status
Simulation time 15962988533 ps
CPU time 109.52 seconds
Started Oct 09 10:18:36 AM UTC 24
Finished Oct 09 10:20:28 AM UTC 24
Peak memory 232500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=48945983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_w
ith_rand_reset.48945983
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/140.edn_alert.3500502707
Short name T277
Test name
Test status
Simulation time 33998246 ps
CPU time 1.46 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:10 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500502707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.3500502707
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/140.edn_genbits.1111671649
Short name T772
Test name
Test status
Simulation time 50164829 ps
CPU time 2.1 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:11 AM UTC 24
Peak memory 230244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111671649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1111671649
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/141.edn_alert.1950887552
Short name T773
Test name
Test status
Simulation time 267671115 ps
CPU time 1.91 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:11 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950887552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 141.edn_alert.1950887552
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/141.edn_genbits.1180081112
Short name T774
Test name
Test status
Simulation time 51764328 ps
CPU time 2.03 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:11 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180081112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1180081112
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/142.edn_alert.4168929393
Short name T775
Test name
Test status
Simulation time 88198173 ps
CPU time 1.43 seconds
Started Oct 09 10:22:09 AM UTC 24
Finished Oct 09 10:22:12 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168929393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.4168929393
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/142.edn_genbits.52166984
Short name T771
Test name
Test status
Simulation time 51532597 ps
CPU time 1.55 seconds
Started Oct 09 10:22:08 AM UTC 24
Finished Oct 09 10:22:11 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52166984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 142.edn_genbits.52166984
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/143.edn_alert.153913344
Short name T776
Test name
Test status
Simulation time 25284262 ps
CPU time 1.81 seconds
Started Oct 09 10:22:09 AM UTC 24
Finished Oct 09 10:22:12 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153913344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 143.edn_alert.153913344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/143.edn_genbits.1202270884
Short name T777
Test name
Test status
Simulation time 122137791 ps
CPU time 1.95 seconds
Started Oct 09 10:22:09 AM UTC 24
Finished Oct 09 10:22:12 AM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202270884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1202270884
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/144.edn_alert.2306234715
Short name T156
Test name
Test status
Simulation time 99572190 ps
CPU time 1.62 seconds
Started Oct 09 10:22:09 AM UTC 24
Finished Oct 09 10:22:12 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306234715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.2306234715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/144.edn_genbits.4174597697
Short name T779
Test name
Test status
Simulation time 69915316 ps
CPU time 2.03 seconds
Started Oct 09 10:22:09 AM UTC 24
Finished Oct 09 10:22:12 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174597697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4174597697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/145.edn_alert.743132575
Short name T780
Test name
Test status
Simulation time 46753361 ps
CPU time 1.39 seconds
Started Oct 09 10:22:10 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743132575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 145.edn_alert.743132575
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/145.edn_genbits.1806621358
Short name T786
Test name
Test status
Simulation time 69388926 ps
CPU time 2.03 seconds
Started Oct 09 10:22:10 AM UTC 24
Finished Oct 09 10:22:14 AM UTC 24
Peak memory 230244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806621358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1806621358
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/146.edn_alert.3491114229
Short name T782
Test name
Test status
Simulation time 166798043 ps
CPU time 1.54 seconds
Started Oct 09 10:22:11 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491114229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.3491114229
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/146.edn_genbits.3635569491
Short name T781
Test name
Test status
Simulation time 84229389 ps
CPU time 1.52 seconds
Started Oct 09 10:22:11 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635569491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3635569491
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/147.edn_alert.1269277
Short name T784
Test name
Test status
Simulation time 42011006 ps
CPU time 1.64 seconds
Started Oct 09 10:22:11 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al
ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 147.edn_alert.1269277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/147.edn_genbits.199602623
Short name T341
Test name
Test status
Simulation time 84350212 ps
CPU time 1.74 seconds
Started Oct 09 10:22:11 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199602623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 147.edn_genbits.199602623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/148.edn_alert.1952665305
Short name T783
Test name
Test status
Simulation time 282255441 ps
CPU time 1.45 seconds
Started Oct 09 10:22:11 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952665305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.1952665305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/148.edn_genbits.1914358090
Short name T785
Test name
Test status
Simulation time 79701292 ps
CPU time 1.66 seconds
Started Oct 09 10:22:11 AM UTC 24
Finished Oct 09 10:22:13 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914358090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1914358090
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/149.edn_alert.1170845389
Short name T790
Test name
Test status
Simulation time 78637552 ps
CPU time 1.63 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:15 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170845389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.1170845389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/149.edn_genbits.633627232
Short name T787
Test name
Test status
Simulation time 75300257 ps
CPU time 1.5 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:14 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633627232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 149.edn_genbits.633627232
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_alert.3991692822
Short name T102
Test name
Test status
Simulation time 46179921 ps
CPU time 1.68 seconds
Started Oct 09 10:18:39 AM UTC 24
Finished Oct 09 10:18:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991692822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.3991692822
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_alert_test.4055327614
Short name T386
Test name
Test status
Simulation time 50755025 ps
CPU time 1.53 seconds
Started Oct 09 10:18:40 AM UTC 24
Finished Oct 09 10:18:43 AM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055327614 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4055327614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_disable.3513158265
Short name T90
Test name
Test status
Simulation time 20258100 ps
CPU time 1.2 seconds
Started Oct 09 10:18:40 AM UTC 24
Finished Oct 09 10:18:42 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513158265 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3513158265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.1568724951
Short name T160
Test name
Test status
Simulation time 82382737 ps
CPU time 1.46 seconds
Started Oct 09 10:18:40 AM UTC 24
Finished Oct 09 10:18:42 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568724951 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.1568724951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_err.1758446246
Short name T180
Test name
Test status
Simulation time 50265898 ps
CPU time 1.21 seconds
Started Oct 09 10:18:39 AM UTC 24
Finished Oct 09 10:18:41 AM UTC 24
Peak memory 238168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758446246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_err.1758446246
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_genbits.1943057652
Short name T73
Test name
Test status
Simulation time 107946580 ps
CPU time 1.79 seconds
Started Oct 09 10:18:37 AM UTC 24
Finished Oct 09 10:18:41 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943057652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1943057652
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_intr.862322082
Short name T384
Test name
Test status
Simulation time 22266225 ps
CPU time 1.65 seconds
Started Oct 09 10:18:39 AM UTC 24
Finished Oct 09 10:18:42 AM UTC 24
Peak memory 226976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862322082 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.862322082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_smoke.1227678245
Short name T383
Test name
Test status
Simulation time 16521392 ps
CPU time 1.17 seconds
Started Oct 09 10:18:37 AM UTC 24
Finished Oct 09 10:18:40 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227678245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.1227678245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_stress_all.845277682
Short name T329
Test name
Test status
Simulation time 273492055 ps
CPU time 5.78 seconds
Started Oct 09 10:18:38 AM UTC 24
Finished Oct 09 10:18:46 AM UTC 24
Peak memory 228056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845277682 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.845277682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.164035780
Short name T237
Test name
Test status
Simulation time 1894677446 ps
CPU time 51.66 seconds
Started Oct 09 10:18:39 AM UTC 24
Finished Oct 09 10:19:32 AM UTC 24
Peak memory 232240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=164035780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_
with_rand_reset.164035780
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/150.edn_alert.2203886578
Short name T792
Test name
Test status
Simulation time 117843848 ps
CPU time 1.65 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:15 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203886578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.2203886578
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/150.edn_genbits.425631100
Short name T788
Test name
Test status
Simulation time 93399870 ps
CPU time 1.36 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:14 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425631100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 150.edn_genbits.425631100
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/151.edn_alert.643440614
Short name T789
Test name
Test status
Simulation time 64088312 ps
CPU time 1.34 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:15 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643440614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 151.edn_alert.643440614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/151.edn_genbits.1812999994
Short name T791
Test name
Test status
Simulation time 88841253 ps
CPU time 1.58 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:15 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812999994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1812999994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/152.edn_alert.3855684017
Short name T796
Test name
Test status
Simulation time 119453408 ps
CPU time 1.67 seconds
Started Oct 09 10:22:13 AM UTC 24
Finished Oct 09 10:22:16 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855684017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.3855684017
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/152.edn_genbits.1888830376
Short name T793
Test name
Test status
Simulation time 21077153 ps
CPU time 1.47 seconds
Started Oct 09 10:22:12 AM UTC 24
Finished Oct 09 10:22:15 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888830376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1888830376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/153.edn_alert.4182547337
Short name T794
Test name
Test status
Simulation time 26124823 ps
CPU time 1.3 seconds
Started Oct 09 10:22:14 AM UTC 24
Finished Oct 09 10:22:16 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182547337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.4182547337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/153.edn_genbits.2121118368
Short name T798
Test name
Test status
Simulation time 43354788 ps
CPU time 1.81 seconds
Started Oct 09 10:22:13 AM UTC 24
Finished Oct 09 10:22:16 AM UTC 24
Peak memory 229200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121118368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2121118368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/154.edn_alert.2945014733
Short name T795
Test name
Test status
Simulation time 28316403 ps
CPU time 1.28 seconds
Started Oct 09 10:22:14 AM UTC 24
Finished Oct 09 10:22:16 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945014733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 154.edn_alert.2945014733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/154.edn_genbits.4002353929
Short name T799
Test name
Test status
Simulation time 38673861 ps
CPU time 1.79 seconds
Started Oct 09 10:22:14 AM UTC 24
Finished Oct 09 10:22:16 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002353929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4002353929
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/155.edn_alert.3517847900
Short name T801
Test name
Test status
Simulation time 47388627 ps
CPU time 1.61 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:17 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517847900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.3517847900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/155.edn_genbits.1624127814
Short name T797
Test name
Test status
Simulation time 21797771 ps
CPU time 1.45 seconds
Started Oct 09 10:22:14 AM UTC 24
Finished Oct 09 10:22:16 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624127814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1624127814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/156.edn_alert.852094687
Short name T175
Test name
Test status
Simulation time 99204304 ps
CPU time 1.61 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:17 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852094687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 156.edn_alert.852094687
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/156.edn_genbits.709689270
Short name T800
Test name
Test status
Simulation time 56852615 ps
CPU time 1.55 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:17 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709689270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 156.edn_genbits.709689270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/157.edn_alert.3110883231
Short name T804
Test name
Test status
Simulation time 28928608 ps
CPU time 1.65 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:18 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110883231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.3110883231
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/157.edn_genbits.762357769
Short name T828
Test name
Test status
Simulation time 725394479 ps
CPU time 7.39 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 230244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762357769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 157.edn_genbits.762357769
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/158.edn_alert.1789390635
Short name T802
Test name
Test status
Simulation time 72933105 ps
CPU time 1.33 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:18 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789390635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.1789390635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/158.edn_genbits.2945986851
Short name T803
Test name
Test status
Simulation time 51111322 ps
CPU time 1.53 seconds
Started Oct 09 10:22:15 AM UTC 24
Finished Oct 09 10:22:18 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945986851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2945986851
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/159.edn_alert.894015674
Short name T810
Test name
Test status
Simulation time 110913464 ps
CPU time 1.79 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894015674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 159.edn_alert.894015674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/159.edn_genbits.3844425570
Short name T805
Test name
Test status
Simulation time 61006594 ps
CPU time 1.48 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844425570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3844425570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_alert_test.3489162502
Short name T388
Test name
Test status
Simulation time 57412051 ps
CPU time 1.27 seconds
Started Oct 09 10:18:43 AM UTC 24
Finished Oct 09 10:18:45 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489162502 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3489162502
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_disable.3117593220
Short name T230
Test name
Test status
Simulation time 11798406 ps
CPU time 1.28 seconds
Started Oct 09 10:18:43 AM UTC 24
Finished Oct 09 10:18:45 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117593220 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3117593220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.1157040862
Short name T161
Test name
Test status
Simulation time 71073999 ps
CPU time 1.56 seconds
Started Oct 09 10:18:43 AM UTC 24
Finished Oct 09 10:18:45 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157040862 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.1157040862
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_err.4096946284
Short name T152
Test name
Test status
Simulation time 31479846 ps
CPU time 1.58 seconds
Started Oct 09 10:18:42 AM UTC 24
Finished Oct 09 10:18:44 AM UTC 24
Peak memory 246632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096946284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.4096946284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_genbits.1078435609
Short name T315
Test name
Test status
Simulation time 66771792 ps
CPU time 1.73 seconds
Started Oct 09 10:18:40 AM UTC 24
Finished Oct 09 10:18:43 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078435609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1078435609
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_intr.703735612
Short name T387
Test name
Test status
Simulation time 26859021 ps
CPU time 1.24 seconds
Started Oct 09 10:18:41 AM UTC 24
Finished Oct 09 10:18:44 AM UTC 24
Peak memory 238236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703735612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.703735612
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_smoke.379630311
Short name T385
Test name
Test status
Simulation time 16598217 ps
CPU time 1.35 seconds
Started Oct 09 10:18:40 AM UTC 24
Finished Oct 09 10:18:42 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379630311 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.edn_smoke.379630311
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/16.edn_stress_all.2921157863
Short name T244
Test name
Test status
Simulation time 194540490 ps
CPU time 5.96 seconds
Started Oct 09 10:18:41 AM UTC 24
Finished Oct 09 10:18:48 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921157863 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2921157863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/160.edn_alert.558104332
Short name T806
Test name
Test status
Simulation time 65325757 ps
CPU time 1.46 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558104332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 160.edn_alert.558104332
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/160.edn_genbits.219238720
Short name T807
Test name
Test status
Simulation time 28291765 ps
CPU time 1.53 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219238720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 160.edn_genbits.219238720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/161.edn_alert.867391490
Short name T808
Test name
Test status
Simulation time 23790931 ps
CPU time 1.43 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867391490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 161.edn_alert.867391490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/162.edn_alert.722462764
Short name T813
Test name
Test status
Simulation time 32871289 ps
CPU time 1.53 seconds
Started Oct 09 10:22:18 AM UTC 24
Finished Oct 09 10:22:20 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722462764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 162.edn_alert.722462764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/162.edn_genbits.413017708
Short name T809
Test name
Test status
Simulation time 76363230 ps
CPU time 1.37 seconds
Started Oct 09 10:22:16 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413017708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 162.edn_genbits.413017708
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/163.edn_alert.1965125510
Short name T812
Test name
Test status
Simulation time 30075680 ps
CPU time 1.23 seconds
Started Oct 09 10:22:18 AM UTC 24
Finished Oct 09 10:22:20 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965125510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.1965125510
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/163.edn_genbits.1016455392
Short name T815
Test name
Test status
Simulation time 182243362 ps
CPU time 3.03 seconds
Started Oct 09 10:22:18 AM UTC 24
Finished Oct 09 10:22:22 AM UTC 24
Peak memory 228128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016455392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1016455392
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/164.edn_alert.4217759046
Short name T725
Test name
Test status
Simulation time 27710524 ps
CPU time 1.59 seconds
Started Oct 09 10:22:18 AM UTC 24
Finished Oct 09 10:22:21 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217759046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.4217759046
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/164.edn_genbits.3992998451
Short name T814
Test name
Test status
Simulation time 37010561 ps
CPU time 1.4 seconds
Started Oct 09 10:22:18 AM UTC 24
Finished Oct 09 10:22:20 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992998451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3992998451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/165.edn_alert.2161708590
Short name T778
Test name
Test status
Simulation time 50368687 ps
CPU time 1.42 seconds
Started Oct 09 10:22:19 AM UTC 24
Finished Oct 09 10:22:22 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161708590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.2161708590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/165.edn_genbits.1470235034
Short name T827
Test name
Test status
Simulation time 141362053 ps
CPU time 3.28 seconds
Started Oct 09 10:22:19 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470235034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1470235034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/166.edn_alert.1631075658
Short name T817
Test name
Test status
Simulation time 92882047 ps
CPU time 1.58 seconds
Started Oct 09 10:22:19 AM UTC 24
Finished Oct 09 10:22:22 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631075658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.1631075658
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/167.edn_alert.2570175439
Short name T816
Test name
Test status
Simulation time 26240764 ps
CPU time 1.6 seconds
Started Oct 09 10:22:19 AM UTC 24
Finished Oct 09 10:22:22 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570175439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.2570175439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/167.edn_genbits.778999868
Short name T818
Test name
Test status
Simulation time 47721606 ps
CPU time 1.77 seconds
Started Oct 09 10:22:19 AM UTC 24
Finished Oct 09 10:22:22 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778999868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 167.edn_genbits.778999868
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/168.edn_alert.2649018741
Short name T822
Test name
Test status
Simulation time 56068794 ps
CPU time 1.33 seconds
Started Oct 09 10:22:20 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649018741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 168.edn_alert.2649018741
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/168.edn_genbits.1476320136
Short name T824
Test name
Test status
Simulation time 55062572 ps
CPU time 1.68 seconds
Started Oct 09 10:22:20 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476320136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1476320136
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/169.edn_alert.2473433983
Short name T823
Test name
Test status
Simulation time 90537798 ps
CPU time 1.34 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 228824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473433983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.2473433983
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/169.edn_genbits.863019626
Short name T825
Test name
Test status
Simulation time 77098658 ps
CPU time 1.5 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 226720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863019626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 169.edn_genbits.863019626
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_alert_test.3184961522
Short name T246
Test name
Test status
Simulation time 16628064 ps
CPU time 1.31 seconds
Started Oct 09 10:18:46 AM UTC 24
Finished Oct 09 10:18:49 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184961522 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3184961522
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_disable.3788720324
Short name T103
Test name
Test status
Simulation time 18251046 ps
CPU time 1.28 seconds
Started Oct 09 10:18:45 AM UTC 24
Finished Oct 09 10:18:48 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788720324 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3788720324
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.1351892521
Short name T243
Test name
Test status
Simulation time 123793654 ps
CPU time 1.89 seconds
Started Oct 09 10:18:45 AM UTC 24
Finished Oct 09 10:18:48 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351892521 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.1351892521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_err.4031352586
Short name T142
Test name
Test status
Simulation time 29405137 ps
CPU time 1.5 seconds
Started Oct 09 10:18:45 AM UTC 24
Finished Oct 09 10:18:48 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031352586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.4031352586
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_intr.280161839
Short name T390
Test name
Test status
Simulation time 35918518 ps
CPU time 1.22 seconds
Started Oct 09 10:18:44 AM UTC 24
Finished Oct 09 10:18:47 AM UTC 24
Peak memory 226976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280161839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.280161839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_smoke.1465004088
Short name T389
Test name
Test status
Simulation time 17263196 ps
CPU time 1.31 seconds
Started Oct 09 10:18:43 AM UTC 24
Finished Oct 09 10:18:45 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465004088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.1465004088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/17.edn_stress_all.2928402166
Short name T245
Test name
Test status
Simulation time 354522854 ps
CPU time 3.61 seconds
Started Oct 09 10:18:44 AM UTC 24
Finished Oct 09 10:18:49 AM UTC 24
Peak memory 228000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928402166 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2928402166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/170.edn_alert.2725229967
Short name T821
Test name
Test status
Simulation time 23332015 ps
CPU time 1.12 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725229967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.2725229967
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/170.edn_genbits.1732937134
Short name T826
Test name
Test status
Simulation time 39749052 ps
CPU time 1.64 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732937134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1732937134
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/171.edn_alert.841853897
Short name T829
Test name
Test status
Simulation time 47892913 ps
CPU time 1.57 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:23 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841853897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 171.edn_alert.841853897
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/171.edn_genbits.4059090277
Short name T832
Test name
Test status
Simulation time 41399430 ps
CPU time 2.31 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:24 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059090277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4059090277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/172.edn_alert.646329405
Short name T831
Test name
Test status
Simulation time 30100792 ps
CPU time 1.75 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:24 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646329405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 172.edn_alert.646329405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/172.edn_genbits.1807178039
Short name T830
Test name
Test status
Simulation time 64069307 ps
CPU time 1.57 seconds
Started Oct 09 10:22:21 AM UTC 24
Finished Oct 09 10:22:24 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807178039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1807178039
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/173.edn_alert.2048233067
Short name T833
Test name
Test status
Simulation time 157568224 ps
CPU time 1.51 seconds
Started Oct 09 10:22:22 AM UTC 24
Finished Oct 09 10:22:25 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048233067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.2048233067
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/173.edn_genbits.2970592931
Short name T834
Test name
Test status
Simulation time 54594204 ps
CPU time 1.5 seconds
Started Oct 09 10:22:22 AM UTC 24
Finished Oct 09 10:22:25 AM UTC 24
Peak memory 229220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970592931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2970592931
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/174.edn_alert.465165531
Short name T835
Test name
Test status
Simulation time 66699105 ps
CPU time 1.46 seconds
Started Oct 09 10:22:22 AM UTC 24
Finished Oct 09 10:22:25 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465165531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 174.edn_alert.465165531
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/174.edn_genbits.1723507948
Short name T842
Test name
Test status
Simulation time 189510657 ps
CPU time 3.23 seconds
Started Oct 09 10:22:22 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723507948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1723507948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/175.edn_alert.4058767563
Short name T841
Test name
Test status
Simulation time 33052562 ps
CPU time 1.87 seconds
Started Oct 09 10:22:23 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058767563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.4058767563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/176.edn_alert.3793262056
Short name T837
Test name
Test status
Simulation time 61022285 ps
CPU time 1.14 seconds
Started Oct 09 10:22:23 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793262056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.3793262056
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/176.edn_genbits.2299251949
Short name T836
Test name
Test status
Simulation time 29361158 ps
CPU time 1.23 seconds
Started Oct 09 10:22:23 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299251949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2299251949
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/177.edn_alert.4222710309
Short name T840
Test name
Test status
Simulation time 114580013 ps
CPU time 1.57 seconds
Started Oct 09 10:22:24 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222710309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 177.edn_alert.4222710309
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/177.edn_genbits.133880177
Short name T838
Test name
Test status
Simulation time 76555962 ps
CPU time 1.24 seconds
Started Oct 09 10:22:24 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133880177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 177.edn_genbits.133880177
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/178.edn_alert.3368013716
Short name T839
Test name
Test status
Simulation time 25199791 ps
CPU time 1.31 seconds
Started Oct 09 10:22:24 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368013716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.3368013716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/178.edn_genbits.3139559516
Short name T843
Test name
Test status
Simulation time 66439625 ps
CPU time 1.79 seconds
Started Oct 09 10:22:24 AM UTC 24
Finished Oct 09 10:22:26 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139559516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3139559516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/179.edn_alert.2408135874
Short name T844
Test name
Test status
Simulation time 36377622 ps
CPU time 1.24 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:27 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408135874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 179.edn_alert.2408135874
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/179.edn_genbits.2783593486
Short name T845
Test name
Test status
Simulation time 69324863 ps
CPU time 1.45 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:27 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783593486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2783593486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_alert_test.2756386369
Short name T392
Test name
Test status
Simulation time 22373143 ps
CPU time 1.29 seconds
Started Oct 09 10:18:49 AM UTC 24
Finished Oct 09 10:18:52 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756386369 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2756386369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_disable.1005275383
Short name T231
Test name
Test status
Simulation time 31208678 ps
CPU time 1.16 seconds
Started Oct 09 10:18:48 AM UTC 24
Finished Oct 09 10:18:50 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005275383 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1005275383
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.406634786
Short name T144
Test name
Test status
Simulation time 27316419 ps
CPU time 1.66 seconds
Started Oct 09 10:18:49 AM UTC 24
Finished Oct 09 10:18:52 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406634786 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.406634786
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_err.4232997237
Short name T391
Test name
Test status
Simulation time 24001157 ps
CPU time 1.43 seconds
Started Oct 09 10:18:48 AM UTC 24
Finished Oct 09 10:18:51 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232997237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.4232997237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_genbits.3253376354
Short name T76
Test name
Test status
Simulation time 59661735 ps
CPU time 1.98 seconds
Started Oct 09 10:18:47 AM UTC 24
Finished Oct 09 10:18:50 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253376354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3253376354
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_smoke.3190109467
Short name T247
Test name
Test status
Simulation time 16415230 ps
CPU time 1.51 seconds
Started Oct 09 10:18:47 AM UTC 24
Finished Oct 09 10:18:49 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190109467 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.3190109467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/18.edn_stress_all.1913255904
Short name T248
Test name
Test status
Simulation time 256790129 ps
CPU time 1.49 seconds
Started Oct 09 10:18:47 AM UTC 24
Finished Oct 09 10:18:49 AM UTC 24
Peak memory 217352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913255904 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1913255904
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/180.edn_alert.703026282
Short name T847
Test name
Test status
Simulation time 74919307 ps
CPU time 1.53 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:28 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703026282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 180.edn_alert.703026282
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/180.edn_genbits.1355717891
Short name T846
Test name
Test status
Simulation time 22750418 ps
CPU time 1.36 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:27 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355717891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1355717891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/181.edn_alert.2943335471
Short name T314
Test name
Test status
Simulation time 88120866 ps
CPU time 1.8 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:28 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943335471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 181.edn_alert.2943335471
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/181.edn_genbits.1624427484
Short name T849
Test name
Test status
Simulation time 66079665 ps
CPU time 1.62 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:28 AM UTC 24
Peak memory 229020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624427484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1624427484
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/182.edn_alert.1030829830
Short name T850
Test name
Test status
Simulation time 216455924 ps
CPU time 1.93 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:28 AM UTC 24
Peak memory 226976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030829830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.1030829830
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/182.edn_genbits.2814754394
Short name T848
Test name
Test status
Simulation time 50384790 ps
CPU time 1.61 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:28 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814754394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2814754394
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/183.edn_alert.359844156
Short name T856
Test name
Test status
Simulation time 44763458 ps
CPU time 1.76 seconds
Started Oct 09 10:22:26 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359844156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 183.edn_alert.359844156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/183.edn_genbits.928183265
Short name T342
Test name
Test status
Simulation time 55905003 ps
CPU time 1.41 seconds
Started Oct 09 10:22:25 AM UTC 24
Finished Oct 09 10:22:28 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928183265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 183.edn_genbits.928183265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/184.edn_alert.2060374286
Short name T852
Test name
Test status
Simulation time 83954808 ps
CPU time 1.39 seconds
Started Oct 09 10:22:26 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060374286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.2060374286
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/184.edn_genbits.2060049213
Short name T855
Test name
Test status
Simulation time 40778911 ps
CPU time 1.73 seconds
Started Oct 09 10:22:26 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060049213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2060049213
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/185.edn_alert.4119636814
Short name T851
Test name
Test status
Simulation time 71948530 ps
CPU time 1.28 seconds
Started Oct 09 10:22:26 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119636814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 185.edn_alert.4119636814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/185.edn_genbits.2074800490
Short name T853
Test name
Test status
Simulation time 32456188 ps
CPU time 1.42 seconds
Started Oct 09 10:22:26 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074800490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2074800490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/186.edn_alert.4275033422
Short name T857
Test name
Test status
Simulation time 41258503 ps
CPU time 1.6 seconds
Started Oct 09 10:22:27 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275033422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.4275033422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/186.edn_genbits.2538611408
Short name T854
Test name
Test status
Simulation time 70907316 ps
CPU time 1.37 seconds
Started Oct 09 10:22:27 AM UTC 24
Finished Oct 09 10:22:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538611408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2538611408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/187.edn_alert.976197604
Short name T858
Test name
Test status
Simulation time 48136612 ps
CPU time 1.34 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:30 AM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976197604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 187.edn_alert.976197604
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/187.edn_genbits.2172536456
Short name T863
Test name
Test status
Simulation time 55950242 ps
CPU time 1.92 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:31 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172536456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2172536456
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/188.edn_alert.4129785725
Short name T860
Test name
Test status
Simulation time 78443422 ps
CPU time 1.47 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:30 AM UTC 24
Peak memory 228868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129785725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.4129785725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/188.edn_genbits.3800706000
Short name T351
Test name
Test status
Simulation time 63000060 ps
CPU time 1.71 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:30 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800706000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3800706000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/189.edn_alert.3152593425
Short name T859
Test name
Test status
Simulation time 25891722 ps
CPU time 1.27 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:30 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152593425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.3152593425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/189.edn_genbits.539752732
Short name T864
Test name
Test status
Simulation time 37037410 ps
CPU time 2.23 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:31 AM UTC 24
Peak memory 229828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539752732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 189.edn_genbits.539752732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_alert_test.2444580276
Short name T395
Test name
Test status
Simulation time 10558004 ps
CPU time 1.23 seconds
Started Oct 09 10:18:52 AM UTC 24
Finished Oct 09 10:18:55 AM UTC 24
Peak memory 216916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444580276 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2444580276
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_disable.2346714274
Short name T394
Test name
Test status
Simulation time 19904864 ps
CPU time 1.23 seconds
Started Oct 09 10:18:52 AM UTC 24
Finished Oct 09 10:18:54 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346714274 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2346714274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_err.307410200
Short name T188
Test name
Test status
Simulation time 51285766 ps
CPU time 1.37 seconds
Started Oct 09 10:18:51 AM UTC 24
Finished Oct 09 10:18:53 AM UTC 24
Peak memory 238044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307410200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.edn_err.307410200
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_genbits.3077551227
Short name T353
Test name
Test status
Simulation time 120963232 ps
CPU time 2.04 seconds
Started Oct 09 10:18:49 AM UTC 24
Finished Oct 09 10:18:53 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077551227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3077551227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_intr.3110426001
Short name T139
Test name
Test status
Simulation time 32907231 ps
CPU time 1.31 seconds
Started Oct 09 10:18:51 AM UTC 24
Finished Oct 09 10:18:53 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110426001 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.3110426001
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_smoke.3008270558
Short name T393
Test name
Test status
Simulation time 22282813 ps
CPU time 1.52 seconds
Started Oct 09 10:18:49 AM UTC 24
Finished Oct 09 10:18:52 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008270558 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_smoke.3008270558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_stress_all.906033980
Short name T397
Test name
Test status
Simulation time 345180247 ps
CPU time 4.79 seconds
Started Oct 09 10:18:49 AM UTC 24
Finished Oct 09 10:18:55 AM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906033980 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.906033980
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.2402955806
Short name T240
Test name
Test status
Simulation time 2131261473 ps
CPU time 55.86 seconds
Started Oct 09 10:18:51 AM UTC 24
Finished Oct 09 10:19:48 AM UTC 24
Peak memory 230228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2402955806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all
_with_rand_reset.2402955806
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/190.edn_alert.2719659038
Short name T861
Test name
Test status
Simulation time 37805667 ps
CPU time 1.42 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:30 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719659038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.2719659038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/190.edn_genbits.475054997
Short name T862
Test name
Test status
Simulation time 65731198 ps
CPU time 1.6 seconds
Started Oct 09 10:22:28 AM UTC 24
Finished Oct 09 10:22:30 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475054997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 190.edn_genbits.475054997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/191.edn_alert.4182468979
Short name T865
Test name
Test status
Simulation time 83930689 ps
CPU time 1.26 seconds
Started Oct 09 10:22:29 AM UTC 24
Finished Oct 09 10:22:31 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182468979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.4182468979
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/191.edn_genbits.1416412623
Short name T867
Test name
Test status
Simulation time 48495667 ps
CPU time 1.89 seconds
Started Oct 09 10:22:29 AM UTC 24
Finished Oct 09 10:22:32 AM UTC 24
Peak memory 229220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416412623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1416412623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/192.edn_alert.3224834601
Short name T868
Test name
Test status
Simulation time 266217837 ps
CPU time 1.71 seconds
Started Oct 09 10:22:29 AM UTC 24
Finished Oct 09 10:22:32 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224834601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.3224834601
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/192.edn_genbits.3034457531
Short name T870
Test name
Test status
Simulation time 54972677 ps
CPU time 1.93 seconds
Started Oct 09 10:22:29 AM UTC 24
Finished Oct 09 10:22:32 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034457531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3034457531
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/193.edn_alert.2573713132
Short name T866
Test name
Test status
Simulation time 86469946 ps
CPU time 1.23 seconds
Started Oct 09 10:22:29 AM UTC 24
Finished Oct 09 10:22:32 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573713132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.2573713132
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/193.edn_genbits.1236005273
Short name T869
Test name
Test status
Simulation time 42564743 ps
CPU time 1.72 seconds
Started Oct 09 10:22:29 AM UTC 24
Finished Oct 09 10:22:32 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236005273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1236005273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/194.edn_alert.3736385730
Short name T874
Test name
Test status
Simulation time 66863498 ps
CPU time 1.51 seconds
Started Oct 09 10:22:30 AM UTC 24
Finished Oct 09 10:22:33 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736385730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.3736385730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/194.edn_genbits.3674470713
Short name T872
Test name
Test status
Simulation time 137157596 ps
CPU time 1.1 seconds
Started Oct 09 10:22:30 AM UTC 24
Finished Oct 09 10:22:32 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674470713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3674470713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/195.edn_alert.1272908313
Short name T875
Test name
Test status
Simulation time 86253131 ps
CPU time 1.39 seconds
Started Oct 09 10:22:30 AM UTC 24
Finished Oct 09 10:22:33 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272908313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 195.edn_alert.1272908313
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/195.edn_genbits.2189221725
Short name T873
Test name
Test status
Simulation time 257681718 ps
CPU time 1.29 seconds
Started Oct 09 10:22:30 AM UTC 24
Finished Oct 09 10:22:33 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189221725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2189221725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/196.edn_alert.2270631707
Short name T876
Test name
Test status
Simulation time 74927771 ps
CPU time 1.46 seconds
Started Oct 09 10:22:31 AM UTC 24
Finished Oct 09 10:22:33 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270631707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 196.edn_alert.2270631707
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/196.edn_genbits.1244492313
Short name T877
Test name
Test status
Simulation time 57623343 ps
CPU time 1.72 seconds
Started Oct 09 10:22:31 AM UTC 24
Finished Oct 09 10:22:33 AM UTC 24
Peak memory 229220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244492313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1244492313
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/197.edn_alert.78069632
Short name T882
Test name
Test status
Simulation time 306416024 ps
CPU time 1.49 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:34 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78069632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 197.edn_alert.78069632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/197.edn_genbits.780029535
Short name T880
Test name
Test status
Simulation time 97955654 ps
CPU time 1.91 seconds
Started Oct 09 10:22:31 AM UTC 24
Finished Oct 09 10:22:34 AM UTC 24
Peak memory 231272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780029535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 197.edn_genbits.780029535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/198.edn_alert.498282876
Short name T885
Test name
Test status
Simulation time 48896753 ps
CPU time 1.59 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:35 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498282876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 198.edn_alert.498282876
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/198.edn_genbits.796879641
Short name T881
Test name
Test status
Simulation time 45177427 ps
CPU time 1.34 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:34 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796879641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 198.edn_genbits.796879641
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/199.edn_alert.2270446880
Short name T883
Test name
Test status
Simulation time 24102801 ps
CPU time 1.35 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:34 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270446880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.2270446880
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/199.edn_genbits.1272086519
Short name T884
Test name
Test status
Simulation time 81978627 ps
CPU time 1.42 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:35 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272086519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1272086519
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_alert.89377152
Short name T12
Test name
Test status
Simulation time 75443780 ps
CPU time 1.5 seconds
Started Oct 09 10:18:05 AM UTC 24
Finished Oct 09 10:18:08 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89377152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_alert.89377152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_alert_test.1865355010
Short name T65
Test name
Test status
Simulation time 62612470 ps
CPU time 1.24 seconds
Started Oct 09 10:18:07 AM UTC 24
Finished Oct 09 10:18:09 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865355010 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1865355010
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_disable.1483833842
Short name T82
Test name
Test status
Simulation time 36649659 ps
CPU time 1.26 seconds
Started Oct 09 10:18:07 AM UTC 24
Finished Oct 09 10:18:09 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483833842 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1483833842
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.2965855970
Short name T16
Test name
Test status
Simulation time 49769070 ps
CPU time 2.17 seconds
Started Oct 09 10:18:07 AM UTC 24
Finished Oct 09 10:18:10 AM UTC 24
Peak memory 228656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965855970 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.2965855970
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_err.3783360329
Short name T70
Test name
Test status
Simulation time 26859340 ps
CPU time 1.5 seconds
Started Oct 09 10:18:06 AM UTC 24
Finished Oct 09 10:18:08 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783360329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.3783360329
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_genbits.547422075
Short name T41
Test name
Test status
Simulation time 72572786 ps
CPU time 1.63 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:18:07 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547422075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_genbits.547422075
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_intr.4100395026
Short name T69
Test name
Test status
Simulation time 21503732 ps
CPU time 1.43 seconds
Started Oct 09 10:18:05 AM UTC 24
Finished Oct 09 10:18:08 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100395026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.4100395026
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_regwen.3891858080
Short name T68
Test name
Test status
Simulation time 26281468 ps
CPU time 1.42 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:18:07 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891858080 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.3891858080
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_sec_cm.4268294127
Short name T20
Test name
Test status
Simulation time 804847165 ps
CPU time 11.57 seconds
Started Oct 09 10:18:07 AM UTC 24
Finished Oct 09 10:18:20 AM UTC 24
Peak memory 260848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268294127 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.4268294127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_smoke.3544342686
Short name T67
Test name
Test status
Simulation time 32079491 ps
CPU time 1.27 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:18:06 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544342686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.3544342686
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_stress_all.3509254220
Short name T42
Test name
Test status
Simulation time 119642613 ps
CPU time 2.66 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:18:08 AM UTC 24
Peak memory 227968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509254220 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3509254220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.1635253903
Short name T239
Test name
Test status
Simulation time 15728452109 ps
CPU time 92.48 seconds
Started Oct 09 10:18:04 AM UTC 24
Finished Oct 09 10:19:39 AM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1635253903 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_
with_rand_reset.1635253903
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_alert.378579715
Short name T127
Test name
Test status
Simulation time 49131503 ps
CPU time 1.69 seconds
Started Oct 09 10:18:54 AM UTC 24
Finished Oct 09 10:18:58 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378579715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_alert.378579715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_alert_test.1637993399
Short name T399
Test name
Test status
Simulation time 16711490 ps
CPU time 1.52 seconds
Started Oct 09 10:18:56 AM UTC 24
Finished Oct 09 10:18:58 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637993399 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1637993399
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_disable.4083086727
Short name T398
Test name
Test status
Simulation time 35982242 ps
CPU time 1.33 seconds
Started Oct 09 10:18:55 AM UTC 24
Finished Oct 09 10:18:57 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083086727 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4083086727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_err.2539699342
Short name T182
Test name
Test status
Simulation time 19522728 ps
CPU time 1.58 seconds
Started Oct 09 10:18:55 AM UTC 24
Finished Oct 09 10:18:57 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539699342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.2539699342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_genbits.1258681656
Short name T77
Test name
Test status
Simulation time 45506236 ps
CPU time 2.23 seconds
Started Oct 09 10:18:53 AM UTC 24
Finished Oct 09 10:18:57 AM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258681656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1258681656
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_smoke.3540339994
Short name T396
Test name
Test status
Simulation time 18842030 ps
CPU time 1.48 seconds
Started Oct 09 10:18:52 AM UTC 24
Finished Oct 09 10:18:55 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540339994 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_smoke.3540339994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_stress_all.1568102044
Short name T407
Test name
Test status
Simulation time 316719169 ps
CPU time 8.57 seconds
Started Oct 09 10:18:53 AM UTC 24
Finished Oct 09 10:19:03 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568102044 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1568102044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.2877026989
Short name T539
Test name
Test status
Simulation time 13560884357 ps
CPU time 104.23 seconds
Started Oct 09 10:18:53 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 228344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2877026989 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all
_with_rand_reset.2877026989
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/200.edn_genbits.4124419506
Short name T890
Test name
Test status
Simulation time 82258329 ps
CPU time 3.11 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:36 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124419506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4124419506
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/201.edn_genbits.407358225
Short name T886
Test name
Test status
Simulation time 40447324 ps
CPU time 1.37 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:35 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407358225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 201.edn_genbits.407358225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/202.edn_genbits.2034436420
Short name T888
Test name
Test status
Simulation time 65532092 ps
CPU time 2.07 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:35 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034436420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2034436420
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/203.edn_genbits.2129766259
Short name T887
Test name
Test status
Simulation time 76445059 ps
CPU time 1.8 seconds
Started Oct 09 10:22:32 AM UTC 24
Finished Oct 09 10:22:35 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129766259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2129766259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/204.edn_genbits.3414049722
Short name T819
Test name
Test status
Simulation time 710174157 ps
CPU time 6.07 seconds
Started Oct 09 10:22:33 AM UTC 24
Finished Oct 09 10:22:41 AM UTC 24
Peak memory 232096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414049722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3414049722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/205.edn_genbits.3192114501
Short name T889
Test name
Test status
Simulation time 44336683 ps
CPU time 1.4 seconds
Started Oct 09 10:22:33 AM UTC 24
Finished Oct 09 10:22:36 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192114501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3192114501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/206.edn_genbits.475230942
Short name T891
Test name
Test status
Simulation time 50460373 ps
CPU time 1.73 seconds
Started Oct 09 10:22:33 AM UTC 24
Finished Oct 09 10:22:36 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475230942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 206.edn_genbits.475230942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/207.edn_genbits.29934638
Short name T338
Test name
Test status
Simulation time 124616424 ps
CPU time 1.39 seconds
Started Oct 09 10:22:33 AM UTC 24
Finished Oct 09 10:22:36 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29934638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 207.edn_genbits.29934638
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/208.edn_genbits.1116998578
Short name T892
Test name
Test status
Simulation time 66282838 ps
CPU time 2.74 seconds
Started Oct 09 10:22:34 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116998578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1116998578
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/209.edn_genbits.635981554
Short name T333
Test name
Test status
Simulation time 56382386 ps
CPU time 1.45 seconds
Started Oct 09 10:22:34 AM UTC 24
Finished Oct 09 10:22:36 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635981554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 209.edn_genbits.635981554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_alert.1319814800
Short name T131
Test name
Test status
Simulation time 25120158 ps
CPU time 1.78 seconds
Started Oct 09 10:18:58 AM UTC 24
Finished Oct 09 10:19:01 AM UTC 24
Peak memory 228956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319814800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.1319814800
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_alert_test.2205229500
Short name T404
Test name
Test status
Simulation time 13979239 ps
CPU time 1.36 seconds
Started Oct 09 10:18:59 AM UTC 24
Finished Oct 09 10:19:02 AM UTC 24
Peak memory 217348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205229500 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2205229500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.3675529536
Short name T406
Test name
Test status
Simulation time 85835761 ps
CPU time 1.7 seconds
Started Oct 09 10:18:59 AM UTC 24
Finished Oct 09 10:19:02 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675529536 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.3675529536
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_err.2822165812
Short name T403
Test name
Test status
Simulation time 52100775 ps
CPU time 1.64 seconds
Started Oct 09 10:18:58 AM UTC 24
Finished Oct 09 10:19:01 AM UTC 24
Peak memory 238300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822165812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.2822165812
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_genbits.2988392358
Short name T401
Test name
Test status
Simulation time 53485987 ps
CPU time 1.44 seconds
Started Oct 09 10:18:57 AM UTC 24
Finished Oct 09 10:19:00 AM UTC 24
Peak memory 226556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988392358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2988392358
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_intr.2219624353
Short name T402
Test name
Test status
Simulation time 22295078 ps
CPU time 1.48 seconds
Started Oct 09 10:18:58 AM UTC 24
Finished Oct 09 10:19:01 AM UTC 24
Peak memory 228944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219624353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.2219624353
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_smoke.908469596
Short name T400
Test name
Test status
Simulation time 25472681 ps
CPU time 1.44 seconds
Started Oct 09 10:18:56 AM UTC 24
Finished Oct 09 10:18:59 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908469596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_smoke.908469596
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_stress_all.3460734818
Short name T267
Test name
Test status
Simulation time 91328624 ps
CPU time 3.29 seconds
Started Oct 09 10:18:57 AM UTC 24
Finished Oct 09 10:19:02 AM UTC 24
Peak memory 227732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460734818 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3460734818
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3374444367
Short name T251
Test name
Test status
Simulation time 9447944810 ps
CPU time 87.87 seconds
Started Oct 09 10:18:57 AM UTC 24
Finished Oct 09 10:20:27 AM UTC 24
Peak memory 230320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3374444367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.3374444367
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/210.edn_genbits.960357234
Short name T897
Test name
Test status
Simulation time 156082997 ps
CPU time 3.09 seconds
Started Oct 09 10:22:34 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 232416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960357234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.960357234
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/211.edn_genbits.1760756212
Short name T871
Test name
Test status
Simulation time 402767028 ps
CPU time 4.83 seconds
Started Oct 09 10:22:35 AM UTC 24
Finished Oct 09 10:22:41 AM UTC 24
Peak memory 232216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760756212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1760756212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/212.edn_genbits.1600584885
Short name T895
Test name
Test status
Simulation time 45829570 ps
CPU time 2.06 seconds
Started Oct 09 10:22:35 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600584885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1600584885
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/213.edn_genbits.1699969467
Short name T893
Test name
Test status
Simulation time 52417523 ps
CPU time 1.53 seconds
Started Oct 09 10:22:35 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699969467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1699969467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/214.edn_genbits.1535787421
Short name T900
Test name
Test status
Simulation time 37596876 ps
CPU time 1.89 seconds
Started Oct 09 10:22:35 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535787421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1535787421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/215.edn_genbits.2787048770
Short name T894
Test name
Test status
Simulation time 30861314 ps
CPU time 1.64 seconds
Started Oct 09 10:22:35 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787048770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2787048770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/216.edn_genbits.1484893573
Short name T901
Test name
Test status
Simulation time 112393717 ps
CPU time 2.21 seconds
Started Oct 09 10:22:35 AM UTC 24
Finished Oct 09 10:22:38 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484893573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1484893573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/217.edn_genbits.848311656
Short name T903
Test name
Test status
Simulation time 71304527 ps
CPU time 1.87 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:39 AM UTC 24
Peak memory 228940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848311656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 217.edn_genbits.848311656
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/218.edn_genbits.1707911128
Short name T905
Test name
Test status
Simulation time 472129241 ps
CPU time 3.52 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:41 AM UTC 24
Peak memory 232296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707911128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1707911128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/219.edn_genbits.1992881733
Short name T902
Test name
Test status
Simulation time 37624766 ps
CPU time 1.64 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:39 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992881733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1992881733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_alert.1749926837
Short name T137
Test name
Test status
Simulation time 33245909 ps
CPU time 1.88 seconds
Started Oct 09 10:19:02 AM UTC 24
Finished Oct 09 10:19:05 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749926837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.1749926837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_alert_test.205165853
Short name T409
Test name
Test status
Simulation time 15847679 ps
CPU time 1.21 seconds
Started Oct 09 10:19:03 AM UTC 24
Finished Oct 09 10:19:05 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205165853 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.205165853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_disable.2337045365
Short name T210
Test name
Test status
Simulation time 32981728 ps
CPU time 1.33 seconds
Started Oct 09 10:19:03 AM UTC 24
Finished Oct 09 10:19:05 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337045365 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2337045365
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.3281803770
Short name T216
Test name
Test status
Simulation time 319952860 ps
CPU time 1.4 seconds
Started Oct 09 10:19:03 AM UTC 24
Finished Oct 09 10:19:06 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281803770 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.3281803770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_err.1250763640
Short name T408
Test name
Test status
Simulation time 31535688 ps
CPU time 1.2 seconds
Started Oct 09 10:19:03 AM UTC 24
Finished Oct 09 10:19:05 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250763640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.edn_err.1250763640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_genbits.1029810812
Short name T357
Test name
Test status
Simulation time 65460678 ps
CPU time 3.4 seconds
Started Oct 09 10:19:01 AM UTC 24
Finished Oct 09 10:19:05 AM UTC 24
Peak memory 232308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029810812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1029810812
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_smoke.4137334274
Short name T405
Test name
Test status
Simulation time 15621639 ps
CPU time 1.49 seconds
Started Oct 09 10:19:00 AM UTC 24
Finished Oct 09 10:19:02 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137334274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_smoke.4137334274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_stress_all.4256804266
Short name T268
Test name
Test status
Simulation time 272564511 ps
CPU time 8 seconds
Started Oct 09 10:19:02 AM UTC 24
Finished Oct 09 10:19:11 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256804266 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4256804266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.1575372238
Short name T238
Test name
Test status
Simulation time 1490759884 ps
CPU time 35.27 seconds
Started Oct 09 10:19:02 AM UTC 24
Finished Oct 09 10:19:39 AM UTC 24
Peak memory 232368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1575372238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all
_with_rand_reset.1575372238
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/220.edn_genbits.948398072
Short name T878
Test name
Test status
Simulation time 44879626 ps
CPU time 2.37 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:40 AM UTC 24
Peak memory 230096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948398072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 220.edn_genbits.948398072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/221.edn_genbits.3312674000
Short name T334
Test name
Test status
Simulation time 29561960 ps
CPU time 1.57 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:39 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312674000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3312674000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/222.edn_genbits.4053077147
Short name T899
Test name
Test status
Simulation time 116800757 ps
CPU time 3.6 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:41 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053077147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.4053077147
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/223.edn_genbits.2224381467
Short name T906
Test name
Test status
Simulation time 67135756 ps
CPU time 2.11 seconds
Started Oct 09 10:22:36 AM UTC 24
Finished Oct 09 10:22:40 AM UTC 24
Peak memory 230216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224381467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2224381467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/224.edn_genbits.3875185056
Short name T907
Test name
Test status
Simulation time 109324919 ps
CPU time 1.82 seconds
Started Oct 09 10:22:37 AM UTC 24
Finished Oct 09 10:22:40 AM UTC 24
Peak memory 228952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875185056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3875185056
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/225.edn_genbits.1525873695
Short name T898
Test name
Test status
Simulation time 47172059 ps
CPU time 1.5 seconds
Started Oct 09 10:22:38 AM UTC 24
Finished Oct 09 10:22:40 AM UTC 24
Peak memory 231204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525873695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1525873695
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/226.edn_genbits.2628001942
Short name T904
Test name
Test status
Simulation time 88090861 ps
CPU time 1.65 seconds
Started Oct 09 10:22:38 AM UTC 24
Finished Oct 09 10:22:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628001942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2628001942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/227.edn_genbits.3262494551
Short name T896
Test name
Test status
Simulation time 55044532 ps
CPU time 1.86 seconds
Started Oct 09 10:22:38 AM UTC 24
Finished Oct 09 10:22:41 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262494551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3262494551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/228.edn_genbits.3571661080
Short name T879
Test name
Test status
Simulation time 66029095 ps
CPU time 1.81 seconds
Started Oct 09 10:22:38 AM UTC 24
Finished Oct 09 10:22:41 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571661080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3571661080
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/229.edn_genbits.2245232185
Short name T909
Test name
Test status
Simulation time 31807880 ps
CPU time 1.69 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245232185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2245232185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_alert.3775092230
Short name T190
Test name
Test status
Simulation time 78562005 ps
CPU time 1.67 seconds
Started Oct 09 10:19:07 AM UTC 24
Finished Oct 09 10:19:09 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775092230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.3775092230
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_alert_test.3613118308
Short name T413
Test name
Test status
Simulation time 26136208 ps
CPU time 1.35 seconds
Started Oct 09 10:19:07 AM UTC 24
Finished Oct 09 10:19:09 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613118308 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3613118308
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.4135630890
Short name T415
Test name
Test status
Simulation time 40214357 ps
CPU time 1.6 seconds
Started Oct 09 10:19:07 AM UTC 24
Finished Oct 09 10:19:09 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135630890 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.4135630890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_err.2563649930
Short name T412
Test name
Test status
Simulation time 23417496 ps
CPU time 1.18 seconds
Started Oct 09 10:19:07 AM UTC 24
Finished Oct 09 10:19:09 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563649930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.edn_err.2563649930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_genbits.3620794375
Short name T411
Test name
Test status
Simulation time 53722955 ps
CPU time 2.02 seconds
Started Oct 09 10:19:04 AM UTC 24
Finished Oct 09 10:19:07 AM UTC 24
Peak memory 230248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620794375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3620794375
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_intr.2574059996
Short name T106
Test name
Test status
Simulation time 25604478 ps
CPU time 1.3 seconds
Started Oct 09 10:19:06 AM UTC 24
Finished Oct 09 10:19:08 AM UTC 24
Peak memory 228584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574059996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.2574059996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_smoke.1146921385
Short name T410
Test name
Test status
Simulation time 15909674 ps
CPU time 1.44 seconds
Started Oct 09 10:19:04 AM UTC 24
Finished Oct 09 10:19:07 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146921385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.1146921385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/23.edn_stress_all.221068846
Short name T269
Test name
Test status
Simulation time 308284111 ps
CPU time 9.07 seconds
Started Oct 09 10:19:04 AM UTC 24
Finished Oct 09 10:19:15 AM UTC 24
Peak memory 228084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221068846 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.221068846
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/230.edn_genbits.2432994285
Short name T912
Test name
Test status
Simulation time 34721170 ps
CPU time 1.95 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 230900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432994285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2432994285
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/231.edn_genbits.3761797949
Short name T908
Test name
Test status
Simulation time 61991403 ps
CPU time 1.45 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761797949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3761797949
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/232.edn_genbits.316845422
Short name T910
Test name
Test status
Simulation time 39830614 ps
CPU time 1.57 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 231272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316845422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 232.edn_genbits.316845422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/233.edn_genbits.610441561
Short name T914
Test name
Test status
Simulation time 107767981 ps
CPU time 1.92 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610441561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 233.edn_genbits.610441561
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/234.edn_genbits.48320084
Short name T911
Test name
Test status
Simulation time 43796828 ps
CPU time 1.53 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48320084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 234.edn_genbits.48320084
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/235.edn_genbits.1200497139
Short name T913
Test name
Test status
Simulation time 70296843 ps
CPU time 1.72 seconds
Started Oct 09 10:22:39 AM UTC 24
Finished Oct 09 10:22:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200497139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1200497139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/236.edn_genbits.1960190477
Short name T925
Test name
Test status
Simulation time 140616061 ps
CPU time 3.22 seconds
Started Oct 09 10:22:40 AM UTC 24
Finished Oct 09 10:22:45 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960190477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1960190477
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/237.edn_genbits.967500295
Short name T915
Test name
Test status
Simulation time 25060940 ps
CPU time 1.41 seconds
Started Oct 09 10:22:40 AM UTC 24
Finished Oct 09 10:22:43 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967500295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 237.edn_genbits.967500295
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/238.edn_genbits.3847690086
Short name T352
Test name
Test status
Simulation time 77790727 ps
CPU time 1.45 seconds
Started Oct 09 10:22:40 AM UTC 24
Finished Oct 09 10:22:43 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847690086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3847690086
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/239.edn_genbits.2136672968
Short name T918
Test name
Test status
Simulation time 55760132 ps
CPU time 1.57 seconds
Started Oct 09 10:22:40 AM UTC 24
Finished Oct 09 10:22:43 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136672968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2136672968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_alert.1261144488
Short name T162
Test name
Test status
Simulation time 204811873 ps
CPU time 1.7 seconds
Started Oct 09 10:19:10 AM UTC 24
Finished Oct 09 10:19:13 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261144488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.1261144488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_alert_test.2941145378
Short name T418
Test name
Test status
Simulation time 15719890 ps
CPU time 1.29 seconds
Started Oct 09 10:19:11 AM UTC 24
Finished Oct 09 10:19:13 AM UTC 24
Peak memory 216544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941145378 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2941145378
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_disable.1470350139
Short name T417
Test name
Test status
Simulation time 62084809 ps
CPU time 1.29 seconds
Started Oct 09 10:19:11 AM UTC 24
Finished Oct 09 10:19:13 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470350139 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1470350139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2425553670
Short name T419
Test name
Test status
Simulation time 34778519 ps
CPU time 1.86 seconds
Started Oct 09 10:19:11 AM UTC 24
Finished Oct 09 10:19:14 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425553670 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.2425553670
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_err.2933327015
Short name T217
Test name
Test status
Simulation time 71488126 ps
CPU time 1.58 seconds
Started Oct 09 10:19:11 AM UTC 24
Finished Oct 09 10:19:13 AM UTC 24
Peak memory 242904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933327015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.2933327015
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_genbits.3832328042
Short name T86
Test name
Test status
Simulation time 54697316 ps
CPU time 2.15 seconds
Started Oct 09 10:19:08 AM UTC 24
Finished Oct 09 10:19:11 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832328042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3832328042
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_intr.3844638103
Short name T416
Test name
Test status
Simulation time 21216777 ps
CPU time 1.6 seconds
Started Oct 09 10:19:09 AM UTC 24
Finished Oct 09 10:19:12 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844638103 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.3844638103
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_smoke.9306856
Short name T414
Test name
Test status
Simulation time 22962913 ps
CPU time 1.32 seconds
Started Oct 09 10:19:07 AM UTC 24
Finished Oct 09 10:19:09 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9306856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_smoke.9306856
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_stress_all.3580818329
Short name T264
Test name
Test status
Simulation time 936631572 ps
CPU time 6.98 seconds
Started Oct 09 10:19:08 AM UTC 24
Finished Oct 09 10:19:16 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580818329 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3580818329
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.3017907603
Short name T495
Test name
Test status
Simulation time 17302491226 ps
CPU time 63.64 seconds
Started Oct 09 10:19:09 AM UTC 24
Finished Oct 09 10:20:15 AM UTC 24
Peak memory 228316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3017907603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.3017907603
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/240.edn_genbits.3427818003
Short name T917
Test name
Test status
Simulation time 38728531 ps
CPU time 1.54 seconds
Started Oct 09 10:22:41 AM UTC 24
Finished Oct 09 10:22:43 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427818003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3427818003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/241.edn_genbits.1398649597
Short name T916
Test name
Test status
Simulation time 100020053 ps
CPU time 1.35 seconds
Started Oct 09 10:22:41 AM UTC 24
Finished Oct 09 10:22:43 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398649597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1398649597
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/242.edn_genbits.2374718496
Short name T920
Test name
Test status
Simulation time 40553118 ps
CPU time 1.56 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:44 AM UTC 24
Peak memory 228984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374718496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2374718496
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/243.edn_genbits.831498208
Short name T919
Test name
Test status
Simulation time 118387402 ps
CPU time 1.31 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:44 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831498208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.edn_genbits.831498208
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/244.edn_genbits.3924747165
Short name T922
Test name
Test status
Simulation time 64302123 ps
CPU time 1.63 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:44 AM UTC 24
Peak memory 231124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924747165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3924747165
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/245.edn_genbits.61904852
Short name T927
Test name
Test status
Simulation time 69433200 ps
CPU time 2.04 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:45 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61904852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 245.edn_genbits.61904852
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/247.edn_genbits.2497303737
Short name T926
Test name
Test status
Simulation time 44635006 ps
CPU time 1.9 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:45 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497303737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2497303737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/248.edn_genbits.23810403
Short name T924
Test name
Test status
Simulation time 87485318 ps
CPU time 1.52 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:45 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23810403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 248.edn_genbits.23810403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/249.edn_genbits.3182471435
Short name T928
Test name
Test status
Simulation time 107915788 ps
CPU time 2.28 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:45 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182471435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3182471435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_alert.2546036278
Short name T178
Test name
Test status
Simulation time 44885628 ps
CPU time 1.8 seconds
Started Oct 09 10:19:14 AM UTC 24
Finished Oct 09 10:19:17 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546036278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.2546036278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_alert_test.2178707307
Short name T259
Test name
Test status
Simulation time 29168756 ps
CPU time 1.4 seconds
Started Oct 09 10:19:16 AM UTC 24
Finished Oct 09 10:19:18 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178707307 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2178707307
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_disable.1734798772
Short name T423
Test name
Test status
Simulation time 11918936 ps
CPU time 1.42 seconds
Started Oct 09 10:19:14 AM UTC 24
Finished Oct 09 10:19:17 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734798772 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1734798772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.2858900232
Short name T257
Test name
Test status
Simulation time 72778849 ps
CPU time 1.78 seconds
Started Oct 09 10:19:14 AM UTC 24
Finished Oct 09 10:19:17 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858900232 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2858900232
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_err.3209369698
Short name T256
Test name
Test status
Simulation time 18223926 ps
CPU time 1.61 seconds
Started Oct 09 10:19:14 AM UTC 24
Finished Oct 09 10:19:17 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209369698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.3209369698
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_genbits.1206394558
Short name T421
Test name
Test status
Simulation time 20875184 ps
CPU time 1.64 seconds
Started Oct 09 10:19:12 AM UTC 24
Finished Oct 09 10:19:15 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206394558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1206394558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_intr.1478699710
Short name T422
Test name
Test status
Simulation time 33359066 ps
CPU time 1.27 seconds
Started Oct 09 10:19:14 AM UTC 24
Finished Oct 09 10:19:16 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478699710 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.1478699710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_smoke.3299140829
Short name T420
Test name
Test status
Simulation time 75715012 ps
CPU time 1.31 seconds
Started Oct 09 10:19:12 AM UTC 24
Finished Oct 09 10:19:14 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299140829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.3299140829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_stress_all.2467261893
Short name T261
Test name
Test status
Simulation time 139178580 ps
CPU time 4.72 seconds
Started Oct 09 10:19:13 AM UTC 24
Finished Oct 09 10:19:19 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467261893 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2467261893
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.357640255
Short name T249
Test name
Test status
Simulation time 2355421464 ps
CPU time 66.64 seconds
Started Oct 09 10:19:14 AM UTC 24
Finished Oct 09 10:20:23 AM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=357640255 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_
with_rand_reset.357640255
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/250.edn_genbits.1463998504
Short name T923
Test name
Test status
Simulation time 90479472 ps
CPU time 1.27 seconds
Started Oct 09 10:22:42 AM UTC 24
Finished Oct 09 10:22:44 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463998504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1463998504
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/251.edn_genbits.1958281081
Short name T945
Test name
Test status
Simulation time 289279171 ps
CPU time 4.42 seconds
Started Oct 09 10:22:43 AM UTC 24
Finished Oct 09 10:22:49 AM UTC 24
Peak memory 232056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958281081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1958281081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/252.edn_genbits.789737726
Short name T934
Test name
Test status
Simulation time 82383103 ps
CPU time 2.23 seconds
Started Oct 09 10:22:43 AM UTC 24
Finished Oct 09 10:22:46 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789737726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 252.edn_genbits.789737726
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/253.edn_genbits.3491322816
Short name T933
Test name
Test status
Simulation time 350578656 ps
CPU time 1.95 seconds
Started Oct 09 10:22:43 AM UTC 24
Finished Oct 09 10:22:46 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491322816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3491322816
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/254.edn_genbits.1865293063
Short name T929
Test name
Test status
Simulation time 233540664 ps
CPU time 1.62 seconds
Started Oct 09 10:22:43 AM UTC 24
Finished Oct 09 10:22:46 AM UTC 24
Peak memory 231052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865293063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1865293063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/255.edn_genbits.3211996805
Short name T930
Test name
Test status
Simulation time 89809263 ps
CPU time 1.55 seconds
Started Oct 09 10:22:43 AM UTC 24
Finished Oct 09 10:22:46 AM UTC 24
Peak memory 228984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211996805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3211996805
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/256.edn_genbits.1146651171
Short name T932
Test name
Test status
Simulation time 47538288 ps
CPU time 1.73 seconds
Started Oct 09 10:22:43 AM UTC 24
Finished Oct 09 10:22:46 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146651171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1146651171
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/257.edn_genbits.3222523130
Short name T931
Test name
Test status
Simulation time 34034292 ps
CPU time 1.49 seconds
Started Oct 09 10:22:44 AM UTC 24
Finished Oct 09 10:22:46 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222523130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3222523130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/258.edn_genbits.2558061165
Short name T935
Test name
Test status
Simulation time 49961649 ps
CPU time 1.48 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:47 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558061165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2558061165
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/259.edn_genbits.4287128650
Short name T936
Test name
Test status
Simulation time 41078764 ps
CPU time 1.47 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:47 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287128650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4287128650
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_alert_test.2715010011
Short name T427
Test name
Test status
Simulation time 28746103 ps
CPU time 1.31 seconds
Started Oct 09 10:19:19 AM UTC 24
Finished Oct 09 10:19:22 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715010011 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2715010011
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_disable.3507375010
Short name T196
Test name
Test status
Simulation time 12510446 ps
CPU time 1.36 seconds
Started Oct 09 10:19:18 AM UTC 24
Finished Oct 09 10:19:21 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507375010 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3507375010
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.4019472959
Short name T424
Test name
Test status
Simulation time 22868739 ps
CPU time 1.46 seconds
Started Oct 09 10:19:18 AM UTC 24
Finished Oct 09 10:19:21 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019472959 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.4019472959
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_err.2794071468
Short name T425
Test name
Test status
Simulation time 28883298 ps
CPU time 2.05 seconds
Started Oct 09 10:19:18 AM UTC 24
Finished Oct 09 10:19:21 AM UTC 24
Peak memory 244124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794071468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.2794071468
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_intr.1943831849
Short name T262
Test name
Test status
Simulation time 36222951 ps
CPU time 1.21 seconds
Started Oct 09 10:19:18 AM UTC 24
Finished Oct 09 10:19:20 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943831849 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.1943831849
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_smoke.3206453380
Short name T258
Test name
Test status
Simulation time 47567643 ps
CPU time 1.29 seconds
Started Oct 09 10:19:16 AM UTC 24
Finished Oct 09 10:19:18 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206453380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.3206453380
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_stress_all.710660200
Short name T426
Test name
Test status
Simulation time 967932519 ps
CPU time 3.5 seconds
Started Oct 09 10:19:17 AM UTC 24
Finished Oct 09 10:19:21 AM UTC 24
Peak memory 230184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710660200 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.710660200
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.3205837985
Short name T250
Test name
Test status
Simulation time 18566111841 ps
CPU time 66.15 seconds
Started Oct 09 10:19:18 AM UTC 24
Finished Oct 09 10:20:26 AM UTC 24
Peak memory 232608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3205837985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all
_with_rand_reset.3205837985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/260.edn_genbits.305294339
Short name T939
Test name
Test status
Simulation time 54270828 ps
CPU time 1.68 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:47 AM UTC 24
Peak memory 231272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305294339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.edn_genbits.305294339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/261.edn_genbits.2301435764
Short name T937
Test name
Test status
Simulation time 62386565 ps
CPU time 1.53 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:47 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301435764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2301435764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/262.edn_genbits.633387202
Short name T938
Test name
Test status
Simulation time 46045423 ps
CPU time 1.43 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:47 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633387202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 262.edn_genbits.633387202
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/264.edn_genbits.825857001
Short name T941
Test name
Test status
Simulation time 109847942 ps
CPU time 1.84 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:48 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825857001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 264.edn_genbits.825857001
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/265.edn_genbits.104383585
Short name T942
Test name
Test status
Simulation time 50026140 ps
CPU time 2.01 seconds
Started Oct 09 10:22:45 AM UTC 24
Finished Oct 09 10:22:48 AM UTC 24
Peak memory 232176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104383585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 265.edn_genbits.104383585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/266.edn_genbits.282549573
Short name T943
Test name
Test status
Simulation time 72057242 ps
CPU time 1.18 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:48 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282549573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 266.edn_genbits.282549573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/267.edn_genbits.531936015
Short name T954
Test name
Test status
Simulation time 367259063 ps
CPU time 3.82 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 232204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531936015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 267.edn_genbits.531936015
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/268.edn_genbits.679252558
Short name T944
Test name
Test status
Simulation time 58005560 ps
CPU time 1.48 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:49 AM UTC 24
Peak memory 231272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679252558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 268.edn_genbits.679252558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/269.edn_genbits.3705723586
Short name T947
Test name
Test status
Simulation time 39105022 ps
CPU time 1.65 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:49 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705723586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3705723586
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_alert.68863875
Short name T235
Test name
Test status
Simulation time 53799961 ps
CPU time 1.95 seconds
Started Oct 09 10:19:22 AM UTC 24
Finished Oct 09 10:19:25 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68863875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_alert.68863875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_alert_test.900706284
Short name T431
Test name
Test status
Simulation time 36318071 ps
CPU time 1.12 seconds
Started Oct 09 10:19:23 AM UTC 24
Finished Oct 09 10:19:25 AM UTC 24
Peak memory 216916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900706284 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.900706284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_disable.3736620715
Short name T234
Test name
Test status
Simulation time 12431377 ps
CPU time 1.15 seconds
Started Oct 09 10:19:22 AM UTC 24
Finished Oct 09 10:19:24 AM UTC 24
Peak memory 227036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736620715 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3736620715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.42862480
Short name T172
Test name
Test status
Simulation time 32434270 ps
CPU time 1.74 seconds
Started Oct 09 10:19:22 AM UTC 24
Finished Oct 09 10:19:25 AM UTC 24
Peak memory 231012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42862480 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.42862480
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_err.3206326922
Short name T215
Test name
Test status
Simulation time 49704066 ps
CPU time 1.73 seconds
Started Oct 09 10:19:22 AM UTC 24
Finished Oct 09 10:19:25 AM UTC 24
Peak memory 248460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206326922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.3206326922
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_genbits.941819140
Short name T429
Test name
Test status
Simulation time 38757898 ps
CPU time 2 seconds
Started Oct 09 10:19:19 AM UTC 24
Finished Oct 09 10:19:22 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941819140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_genbits.941819140
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_intr.3943707994
Short name T430
Test name
Test status
Simulation time 41250935 ps
CPU time 1.39 seconds
Started Oct 09 10:19:22 AM UTC 24
Finished Oct 09 10:19:24 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943707994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.3943707994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_smoke.3112136043
Short name T428
Test name
Test status
Simulation time 51892750 ps
CPU time 1.4 seconds
Started Oct 09 10:19:19 AM UTC 24
Finished Oct 09 10:19:22 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112136043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.3112136043
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.1235344131
Short name T252
Test name
Test status
Simulation time 5527058589 ps
CPU time 73.75 seconds
Started Oct 09 10:19:21 AM UTC 24
Finished Oct 09 10:20:36 AM UTC 24
Peak memory 230452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1235344131 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all
_with_rand_reset.1235344131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/270.edn_genbits.907368014
Short name T948
Test name
Test status
Simulation time 41515782 ps
CPU time 1.8 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:49 AM UTC 24
Peak memory 231260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907368014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 270.edn_genbits.907368014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/271.edn_genbits.4108568108
Short name T946
Test name
Test status
Simulation time 25842674 ps
CPU time 1.36 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:49 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108568108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4108568108
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/272.edn_genbits.4143469894
Short name T335
Test name
Test status
Simulation time 22165216 ps
CPU time 1.41 seconds
Started Oct 09 10:22:46 AM UTC 24
Finished Oct 09 10:22:49 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143469894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.4143469894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/273.edn_genbits.914279777
Short name T949
Test name
Test status
Simulation time 34253103 ps
CPU time 1.5 seconds
Started Oct 09 10:22:47 AM UTC 24
Finished Oct 09 10:22:50 AM UTC 24
Peak memory 228916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914279777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 273.edn_genbits.914279777
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/274.edn_genbits.2795898726
Short name T953
Test name
Test status
Simulation time 65647488 ps
CPU time 2.37 seconds
Started Oct 09 10:22:48 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795898726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2795898726
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/275.edn_genbits.2544610582
Short name T952
Test name
Test status
Simulation time 36936300 ps
CPU time 2.03 seconds
Started Oct 09 10:22:48 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 230244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544610582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2544610582
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/276.edn_genbits.710186926
Short name T960
Test name
Test status
Simulation time 94865693 ps
CPU time 2.84 seconds
Started Oct 09 10:22:48 AM UTC 24
Finished Oct 09 10:22:52 AM UTC 24
Peak memory 232184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710186926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 276.edn_genbits.710186926
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/277.edn_genbits.2941178060
Short name T955
Test name
Test status
Simulation time 50225934 ps
CPU time 2.37 seconds
Started Oct 09 10:22:48 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941178060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2941178060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/278.edn_genbits.3482106498
Short name T951
Test name
Test status
Simulation time 53571361 ps
CPU time 1.38 seconds
Started Oct 09 10:22:48 AM UTC 24
Finished Oct 09 10:22:50 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482106498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3482106498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/279.edn_genbits.3898272687
Short name T950
Test name
Test status
Simulation time 66102960 ps
CPU time 1.33 seconds
Started Oct 09 10:22:48 AM UTC 24
Finished Oct 09 10:22:50 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898272687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3898272687
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_alert.410122014
Short name T436
Test name
Test status
Simulation time 48167841 ps
CPU time 1.58 seconds
Started Oct 09 10:19:26 AM UTC 24
Finished Oct 09 10:19:29 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410122014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.edn_alert.410122014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_alert_test.435375823
Short name T438
Test name
Test status
Simulation time 14734466 ps
CPU time 1.33 seconds
Started Oct 09 10:19:28 AM UTC 24
Finished Oct 09 10:19:30 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435375823 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.435375823
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_disable.1806054107
Short name T435
Test name
Test status
Simulation time 10630106 ps
CPU time 1.3 seconds
Started Oct 09 10:19:27 AM UTC 24
Finished Oct 09 10:19:29 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806054107 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1806054107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.1795957799
Short name T437
Test name
Test status
Simulation time 205311055 ps
CPU time 1.54 seconds
Started Oct 09 10:19:27 AM UTC 24
Finished Oct 09 10:19:29 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795957799 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.1795957799
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_err.4170801030
Short name T157
Test name
Test status
Simulation time 68782450 ps
CPU time 1.55 seconds
Started Oct 09 10:19:27 AM UTC 24
Finished Oct 09 10:19:29 AM UTC 24
Peak memory 226960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170801030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.4170801030
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_genbits.3799291898
Short name T433
Test name
Test status
Simulation time 78890499 ps
CPU time 2.22 seconds
Started Oct 09 10:19:23 AM UTC 24
Finished Oct 09 10:19:27 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799291898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3799291898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_intr.1510881506
Short name T434
Test name
Test status
Simulation time 22097400 ps
CPU time 1.86 seconds
Started Oct 09 10:19:25 AM UTC 24
Finished Oct 09 10:19:29 AM UTC 24
Peak memory 238480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510881506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.1510881506
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_smoke.3704579763
Short name T432
Test name
Test status
Simulation time 39255819 ps
CPU time 1.4 seconds
Started Oct 09 10:19:23 AM UTC 24
Finished Oct 09 10:19:26 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704579763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.3704579763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_stress_all.1978981253
Short name T439
Test name
Test status
Simulation time 534720771 ps
CPU time 5.57 seconds
Started Oct 09 10:19:25 AM UTC 24
Finished Oct 09 10:19:32 AM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978981253 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1978981253
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.2861142888
Short name T254
Test name
Test status
Simulation time 21662261047 ps
CPU time 99.56 seconds
Started Oct 09 10:19:25 AM UTC 24
Finished Oct 09 10:21:07 AM UTC 24
Peak memory 230324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2861142888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all
_with_rand_reset.2861142888
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/280.edn_genbits.1127342392
Short name T956
Test name
Test status
Simulation time 66163474 ps
CPU time 1.24 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127342392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1127342392
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/281.edn_genbits.4145693922
Short name T957
Test name
Test status
Simulation time 45566199 ps
CPU time 1.28 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145693922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4145693922
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/282.edn_genbits.829655886
Short name T958
Test name
Test status
Simulation time 90625122 ps
CPU time 1.28 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:51 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829655886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 282.edn_genbits.829655886
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/283.edn_genbits.1512726054
Short name T959
Test name
Test status
Simulation time 97154168 ps
CPU time 1.41 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:52 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512726054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1512726054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/284.edn_genbits.2686597615
Short name T964
Test name
Test status
Simulation time 83478188 ps
CPU time 2.33 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:52 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686597615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2686597615
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/285.edn_genbits.1107998444
Short name T961
Test name
Test status
Simulation time 227839518 ps
CPU time 1.48 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:52 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107998444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1107998444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/286.edn_genbits.3902465265
Short name T962
Test name
Test status
Simulation time 77722828 ps
CPU time 1.53 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:52 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902465265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3902465265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/287.edn_genbits.2034814990
Short name T963
Test name
Test status
Simulation time 37479649 ps
CPU time 2.07 seconds
Started Oct 09 10:22:49 AM UTC 24
Finished Oct 09 10:22:52 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034814990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2034814990
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/288.edn_genbits.1953159538
Short name T965
Test name
Test status
Simulation time 41072750 ps
CPU time 1.47 seconds
Started Oct 09 10:22:50 AM UTC 24
Finished Oct 09 10:22:53 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953159538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1953159538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/289.edn_genbits.2264192750
Short name T967
Test name
Test status
Simulation time 76212033 ps
CPU time 1.62 seconds
Started Oct 09 10:22:50 AM UTC 24
Finished Oct 09 10:22:53 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264192750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2264192750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_alert.3310680106
Short name T138
Test name
Test status
Simulation time 29436999 ps
CPU time 1.95 seconds
Started Oct 09 10:19:30 AM UTC 24
Finished Oct 09 10:19:33 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310680106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.3310680106
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_alert_test.915230142
Short name T300
Test name
Test status
Simulation time 37687520 ps
CPU time 1.27 seconds
Started Oct 09 10:19:34 AM UTC 24
Finished Oct 09 10:19:36 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915230142 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.915230142
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_disable.3969756403
Short name T214
Test name
Test status
Simulation time 10561643 ps
CPU time 1.39 seconds
Started Oct 09 10:19:32 AM UTC 24
Finished Oct 09 10:19:35 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969756403 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3969756403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1484241037
Short name T148
Test name
Test status
Simulation time 108294280 ps
CPU time 1.73 seconds
Started Oct 09 10:19:33 AM UTC 24
Finished Oct 09 10:19:36 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484241037 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1484241037
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_err.2744218031
Short name T212
Test name
Test status
Simulation time 129051506 ps
CPU time 1.66 seconds
Started Oct 09 10:19:31 AM UTC 24
Finished Oct 09 10:19:34 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744218031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.2744218031
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_genbits.2722405780
Short name T13
Test name
Test status
Simulation time 57181488 ps
CPU time 1.84 seconds
Started Oct 09 10:19:30 AM UTC 24
Finished Oct 09 10:19:33 AM UTC 24
Peak memory 231268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722405780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2722405780
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_intr.3155513291
Short name T440
Test name
Test status
Simulation time 22208026 ps
CPU time 1.28 seconds
Started Oct 09 10:19:30 AM UTC 24
Finished Oct 09 10:19:32 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155513291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.3155513291
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_smoke.3013695766
Short name T441
Test name
Test status
Simulation time 49460370 ps
CPU time 1.45 seconds
Started Oct 09 10:19:30 AM UTC 24
Finished Oct 09 10:19:33 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013695766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.3013695766
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/29.edn_stress_all.1619179203
Short name T299
Test name
Test status
Simulation time 280792909 ps
CPU time 3.15 seconds
Started Oct 09 10:19:30 AM UTC 24
Finished Oct 09 10:19:34 AM UTC 24
Peak memory 228132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619179203 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1619179203
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/290.edn_genbits.1146209331
Short name T968
Test name
Test status
Simulation time 102276414 ps
CPU time 1.63 seconds
Started Oct 09 10:22:50 AM UTC 24
Finished Oct 09 10:22:53 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146209331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1146209331
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/291.edn_genbits.1430049659
Short name T966
Test name
Test status
Simulation time 58018672 ps
CPU time 1.38 seconds
Started Oct 09 10:22:50 AM UTC 24
Finished Oct 09 10:22:53 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430049659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1430049659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/292.edn_genbits.3055884459
Short name T969
Test name
Test status
Simulation time 30309364 ps
CPU time 1.99 seconds
Started Oct 09 10:22:51 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055884459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3055884459
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/293.edn_genbits.2649184950
Short name T971
Test name
Test status
Simulation time 57109142 ps
CPU time 2.39 seconds
Started Oct 09 10:22:51 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649184950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2649184950
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/294.edn_genbits.1530015868
Short name T970
Test name
Test status
Simulation time 84433463 ps
CPU time 1.29 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530015868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1530015868
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/295.edn_genbits.400666162
Short name T973
Test name
Test status
Simulation time 165767717 ps
CPU time 1.33 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400666162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 295.edn_genbits.400666162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/296.edn_genbits.4222960394
Short name T972
Test name
Test status
Simulation time 68334654 ps
CPU time 1.27 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:54 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222960394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4222960394
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/297.edn_genbits.4110528744
Short name T976
Test name
Test status
Simulation time 67866617 ps
CPU time 2.03 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:55 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110528744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.4110528744
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/298.edn_genbits.4271503096
Short name T974
Test name
Test status
Simulation time 58901103 ps
CPU time 1.65 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:55 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271503096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4271503096
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/299.edn_genbits.1993126366
Short name T975
Test name
Test status
Simulation time 82621713 ps
CPU time 1.64 seconds
Started Oct 09 10:22:52 AM UTC 24
Finished Oct 09 10:22:55 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993126366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1993126366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_alert.141104225
Short name T52
Test name
Test status
Simulation time 29785045 ps
CPU time 1.54 seconds
Started Oct 09 10:18:08 AM UTC 24
Finished Oct 09 10:18:11 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141104225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.edn_alert.141104225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_alert_test.3394131608
Short name T66
Test name
Test status
Simulation time 13809508 ps
CPU time 1.36 seconds
Started Oct 09 10:18:10 AM UTC 24
Finished Oct 09 10:18:12 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394131608 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3394131608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_disable.2620906066
Short name T53
Test name
Test status
Simulation time 12063162 ps
CPU time 1.14 seconds
Started Oct 09 10:18:10 AM UTC 24
Finished Oct 09 10:18:12 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620906066 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2620906066
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.1488062735
Short name T45
Test name
Test status
Simulation time 34971288 ps
CPU time 1.28 seconds
Started Oct 09 10:18:10 AM UTC 24
Finished Oct 09 10:18:12 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488062735 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.1488062735
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_err.3773714719
Short name T63
Test name
Test status
Simulation time 26343713 ps
CPU time 1.21 seconds
Started Oct 09 10:18:09 AM UTC 24
Finished Oct 09 10:18:12 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773714719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.3773714719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_intr.1384090281
Short name T43
Test name
Test status
Simulation time 21985555 ps
CPU time 1.35 seconds
Started Oct 09 10:18:08 AM UTC 24
Finished Oct 09 10:18:11 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384090281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.1384090281
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_regwen.1530901642
Short name T83
Test name
Test status
Simulation time 116745166 ps
CPU time 1.33 seconds
Started Oct 09 10:18:07 AM UTC 24
Finished Oct 09 10:18:09 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530901642 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.1530901642
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_sec_cm.4182435458
Short name T58
Test name
Test status
Simulation time 1926178313 ps
CPU time 10.18 seconds
Started Oct 09 10:18:10 AM UTC 24
Finished Oct 09 10:18:21 AM UTC 24
Peak memory 262780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182435458 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4182435458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/3.edn_smoke.1158835444
Short name T84
Test name
Test status
Simulation time 50689250 ps
CPU time 1.44 seconds
Started Oct 09 10:18:07 AM UTC 24
Finished Oct 09 10:18:09 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158835444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.1158835444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_alert.3970133956
Short name T304
Test name
Test status
Simulation time 72462990 ps
CPU time 1.48 seconds
Started Oct 09 10:19:36 AM UTC 24
Finished Oct 09 10:19:38 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970133956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.3970133956
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_alert_test.2489178342
Short name T443
Test name
Test status
Simulation time 20696619 ps
CPU time 1.22 seconds
Started Oct 09 10:19:38 AM UTC 24
Finished Oct 09 10:19:41 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489178342 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2489178342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_disable.1857550453
Short name T442
Test name
Test status
Simulation time 13834612 ps
CPU time 1.2 seconds
Started Oct 09 10:19:37 AM UTC 24
Finished Oct 09 10:19:39 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857550453 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1857550453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_err.2903062625
Short name T158
Test name
Test status
Simulation time 28043603 ps
CPU time 1.71 seconds
Started Oct 09 10:19:37 AM UTC 24
Finished Oct 09 10:19:40 AM UTC 24
Peak memory 246980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903062625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.2903062625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_genbits.4141652596
Short name T302
Test name
Test status
Simulation time 77714687 ps
CPU time 2.35 seconds
Started Oct 09 10:19:34 AM UTC 24
Finished Oct 09 10:19:37 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141652596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4141652596
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_intr.405866114
Short name T303
Test name
Test status
Simulation time 22860676 ps
CPU time 1.7 seconds
Started Oct 09 10:19:35 AM UTC 24
Finished Oct 09 10:19:38 AM UTC 24
Peak memory 226976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405866114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.405866114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_smoke.45543639
Short name T301
Test name
Test status
Simulation time 94344370 ps
CPU time 1.24 seconds
Started Oct 09 10:19:34 AM UTC 24
Finished Oct 09 10:19:36 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45543639 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_smoke.45543639
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_stress_all.773425493
Short name T328
Test name
Test status
Simulation time 227423697 ps
CPU time 6.66 seconds
Started Oct 09 10:19:35 AM UTC 24
Finished Oct 09 10:19:43 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773425493 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.773425493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.1236711769
Short name T524
Test name
Test status
Simulation time 3417967113 ps
CPU time 56.09 seconds
Started Oct 09 10:19:35 AM UTC 24
Finished Oct 09 10:20:33 AM UTC 24
Peak memory 230252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1236711769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all
_with_rand_reset.1236711769
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_alert.427928097
Short name T446
Test name
Test status
Simulation time 92432329 ps
CPU time 1.45 seconds
Started Oct 09 10:19:41 AM UTC 24
Finished Oct 09 10:19:43 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427928097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_alert.427928097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_alert_test.2198103840
Short name T447
Test name
Test status
Simulation time 136913154 ps
CPU time 1.07 seconds
Started Oct 09 10:19:42 AM UTC 24
Finished Oct 09 10:19:44 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198103840 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2198103840
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_disable.1521968679
Short name T448
Test name
Test status
Simulation time 10972680 ps
CPU time 1.35 seconds
Started Oct 09 10:19:42 AM UTC 24
Finished Oct 09 10:19:44 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521968679 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1521968679
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.18005154
Short name T449
Test name
Test status
Simulation time 30927964 ps
CPU time 1.75 seconds
Started Oct 09 10:19:42 AM UTC 24
Finished Oct 09 10:19:45 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18005154 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.18005154
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_err.875740334
Short name T181
Test name
Test status
Simulation time 22736890 ps
CPU time 1.47 seconds
Started Oct 09 10:19:41 AM UTC 24
Finished Oct 09 10:19:43 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875740334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.edn_err.875740334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_genbits.2237806013
Short name T360
Test name
Test status
Simulation time 98336342 ps
CPU time 2.56 seconds
Started Oct 09 10:19:39 AM UTC 24
Finished Oct 09 10:19:43 AM UTC 24
Peak memory 232184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237806013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2237806013
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_intr.3095214318
Short name T445
Test name
Test status
Simulation time 26835794 ps
CPU time 1.29 seconds
Started Oct 09 10:19:41 AM UTC 24
Finished Oct 09 10:19:43 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095214318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.3095214318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_smoke.1779023857
Short name T444
Test name
Test status
Simulation time 16727407 ps
CPU time 1.5 seconds
Started Oct 09 10:19:38 AM UTC 24
Finished Oct 09 10:19:41 AM UTC 24
Peak memory 226836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779023857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.1779023857
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/31.edn_stress_all.1676451296
Short name T331
Test name
Test status
Simulation time 215772593 ps
CPU time 4.64 seconds
Started Oct 09 10:19:39 AM UTC 24
Finished Oct 09 10:19:45 AM UTC 24
Peak memory 230256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676451296 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1676451296
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_alert.3466356173
Short name T145
Test name
Test status
Simulation time 26541269 ps
CPU time 1.61 seconds
Started Oct 09 10:19:46 AM UTC 24
Finished Oct 09 10:19:48 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466356173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.3466356173
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_alert_test.3500325973
Short name T455
Test name
Test status
Simulation time 95865707 ps
CPU time 1.11 seconds
Started Oct 09 10:19:47 AM UTC 24
Finished Oct 09 10:19:49 AM UTC 24
Peak memory 216916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500325973 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3500325973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_disable.2836744493
Short name T453
Test name
Test status
Simulation time 40386477 ps
CPU time 1.23 seconds
Started Oct 09 10:19:46 AM UTC 24
Finished Oct 09 10:19:48 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836744493 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2836744493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1059729875
Short name T211
Test name
Test status
Simulation time 236513693 ps
CPU time 1.5 seconds
Started Oct 09 10:19:46 AM UTC 24
Finished Oct 09 10:19:48 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059729875 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1059729875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_err.3847178344
Short name T454
Test name
Test status
Simulation time 25763061 ps
CPU time 1.5 seconds
Started Oct 09 10:19:46 AM UTC 24
Finished Oct 09 10:19:48 AM UTC 24
Peak memory 238048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847178344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.3847178344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_genbits.4282300661
Short name T452
Test name
Test status
Simulation time 35023089 ps
CPU time 2.05 seconds
Started Oct 09 10:19:44 AM UTC 24
Finished Oct 09 10:19:47 AM UTC 24
Peak memory 230300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282300661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4282300661
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_intr.3230451439
Short name T451
Test name
Test status
Simulation time 22911502 ps
CPU time 1.31 seconds
Started Oct 09 10:19:44 AM UTC 24
Finished Oct 09 10:19:47 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230451439 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.3230451439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_smoke.1267516529
Short name T450
Test name
Test status
Simulation time 50963341 ps
CPU time 1.36 seconds
Started Oct 09 10:19:43 AM UTC 24
Finished Oct 09 10:19:46 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267516529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.1267516529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/32.edn_stress_all.1120923868
Short name T456
Test name
Test status
Simulation time 780730111 ps
CPU time 4.54 seconds
Started Oct 09 10:19:44 AM UTC 24
Finished Oct 09 10:19:50 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120923868 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1120923868
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_alert.1406834502
Short name T169
Test name
Test status
Simulation time 118685374 ps
CPU time 1.74 seconds
Started Oct 09 10:19:49 AM UTC 24
Finished Oct 09 10:19:52 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406834502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_alert.1406834502
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_alert_test.2598462343
Short name T461
Test name
Test status
Simulation time 25585103 ps
CPU time 1.34 seconds
Started Oct 09 10:19:52 AM UTC 24
Finished Oct 09 10:19:54 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598462343 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2598462343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_disable.2035714502
Short name T459
Test name
Test status
Simulation time 41667022 ps
CPU time 1.33 seconds
Started Oct 09 10:19:50 AM UTC 24
Finished Oct 09 10:19:53 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035714502 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2035714502
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.1744209357
Short name T460
Test name
Test status
Simulation time 222709282 ps
CPU time 1.63 seconds
Started Oct 09 10:19:51 AM UTC 24
Finished Oct 09 10:19:53 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744209357 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.1744209357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_err.1812164072
Short name T226
Test name
Test status
Simulation time 44333420 ps
CPU time 1.62 seconds
Started Oct 09 10:19:49 AM UTC 24
Finished Oct 09 10:19:52 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812164072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.1812164072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_genbits.23921129
Short name T14
Test name
Test status
Simulation time 46939030 ps
CPU time 2.48 seconds
Started Oct 09 10:19:48 AM UTC 24
Finished Oct 09 10:19:51 AM UTC 24
Peak memory 232292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23921129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.edn_genbits.23921129
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_intr.3527383928
Short name T458
Test name
Test status
Simulation time 32103396 ps
CPU time 1.22 seconds
Started Oct 09 10:19:49 AM UTC 24
Finished Oct 09 10:19:51 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527383928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.3527383928
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_smoke.1582395973
Short name T457
Test name
Test status
Simulation time 40260601 ps
CPU time 1.31 seconds
Started Oct 09 10:19:48 AM UTC 24
Finished Oct 09 10:19:50 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582395973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.1582395973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_stress_all.2848551604
Short name T464
Test name
Test status
Simulation time 493199217 ps
CPU time 5.62 seconds
Started Oct 09 10:19:49 AM UTC 24
Finished Oct 09 10:19:56 AM UTC 24
Peak memory 232088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848551604 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2848551604
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.112041568
Short name T253
Test name
Test status
Simulation time 9871881072 ps
CPU time 53.83 seconds
Started Oct 09 10:19:49 AM UTC 24
Finished Oct 09 10:20:45 AM UTC 24
Peak memory 230332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=112041568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_
with_rand_reset.112041568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_alert.437886618
Short name T467
Test name
Test status
Simulation time 31220085 ps
CPU time 1.79 seconds
Started Oct 09 10:19:54 AM UTC 24
Finished Oct 09 10:19:57 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437886618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_alert.437886618
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_alert_test.1378349049
Short name T468
Test name
Test status
Simulation time 40871480 ps
CPU time 1.3 seconds
Started Oct 09 10:19:56 AM UTC 24
Finished Oct 09 10:19:59 AM UTC 24
Peak memory 216752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378349049 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1378349049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_disable.3226122913
Short name T232
Test name
Test status
Simulation time 167939892 ps
CPU time 1.24 seconds
Started Oct 09 10:19:55 AM UTC 24
Finished Oct 09 10:19:58 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226122913 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3226122913
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.1130610243
Short name T224
Test name
Test status
Simulation time 41136945 ps
CPU time 1.39 seconds
Started Oct 09 10:19:56 AM UTC 24
Finished Oct 09 10:19:59 AM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130610243 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.1130610243
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_genbits.3381159403
Short name T462
Test name
Test status
Simulation time 60426969 ps
CPU time 1.39 seconds
Started Oct 09 10:19:53 AM UTC 24
Finished Oct 09 10:19:55 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381159403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3381159403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_intr.4158819484
Short name T465
Test name
Test status
Simulation time 38417182 ps
CPU time 1.31 seconds
Started Oct 09 10:19:54 AM UTC 24
Finished Oct 09 10:19:56 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158819484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.4158819484
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_smoke.1032674697
Short name T463
Test name
Test status
Simulation time 44400299 ps
CPU time 1.46 seconds
Started Oct 09 10:19:53 AM UTC 24
Finished Oct 09 10:19:55 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032674697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.1032674697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/34.edn_stress_all.1051508982
Short name T466
Test name
Test status
Simulation time 88045494 ps
CPU time 2.89 seconds
Started Oct 09 10:19:53 AM UTC 24
Finished Oct 09 10:19:57 AM UTC 24
Peak memory 227992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051508982 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1051508982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_alert.3431339764
Short name T471
Test name
Test status
Simulation time 82069657 ps
CPU time 1.78 seconds
Started Oct 09 10:19:58 AM UTC 24
Finished Oct 09 10:20:01 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431339764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.3431339764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_alert_test.2989229912
Short name T476
Test name
Test status
Simulation time 16403612 ps
CPU time 1.32 seconds
Started Oct 09 10:20:00 AM UTC 24
Finished Oct 09 10:20:02 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989229912 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2989229912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_disable.3320349648
Short name T472
Test name
Test status
Simulation time 41262120 ps
CPU time 1.2 seconds
Started Oct 09 10:19:59 AM UTC 24
Finished Oct 09 10:20:01 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320349648 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3320349648
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.2975992322
Short name T473
Test name
Test status
Simulation time 35291641 ps
CPU time 1.59 seconds
Started Oct 09 10:19:59 AM UTC 24
Finished Oct 09 10:20:02 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975992322 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.2975992322
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_err.1983852150
Short name T195
Test name
Test status
Simulation time 25657336 ps
CPU time 1.4 seconds
Started Oct 09 10:19:58 AM UTC 24
Finished Oct 09 10:20:00 AM UTC 24
Peak memory 238048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983852150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.1983852150
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_genbits.3883324559
Short name T470
Test name
Test status
Simulation time 52049076 ps
CPU time 2.18 seconds
Started Oct 09 10:19:57 AM UTC 24
Finished Oct 09 10:20:00 AM UTC 24
Peak memory 230188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883324559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3883324559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_smoke.1958879476
Short name T469
Test name
Test status
Simulation time 27180520 ps
CPU time 1.4 seconds
Started Oct 09 10:19:56 AM UTC 24
Finished Oct 09 10:19:59 AM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958879476 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_smoke.1958879476
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_stress_all.3978623533
Short name T474
Test name
Test status
Simulation time 187869371 ps
CPU time 3.12 seconds
Started Oct 09 10:19:58 AM UTC 24
Finished Oct 09 10:20:02 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978623533 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3978623533
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.4173845825
Short name T710
Test name
Test status
Simulation time 4682214530 ps
CPU time 115.7 seconds
Started Oct 09 10:19:58 AM UTC 24
Finished Oct 09 10:21:56 AM UTC 24
Peak memory 234940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4173845825 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.4173845825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_alert.369400891
Short name T198
Test name
Test status
Simulation time 295207735 ps
CPU time 2.22 seconds
Started Oct 09 10:20:02 AM UTC 24
Finished Oct 09 10:20:05 AM UTC 24
Peak memory 230680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369400891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.edn_alert.369400891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_alert_test.2717628298
Short name T483
Test name
Test status
Simulation time 15679802 ps
CPU time 1.34 seconds
Started Oct 09 10:20:04 AM UTC 24
Finished Oct 09 10:20:06 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717628298 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2717628298
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_disable.1274753943
Short name T479
Test name
Test status
Simulation time 14151050 ps
CPU time 1.34 seconds
Started Oct 09 10:20:03 AM UTC 24
Finished Oct 09 10:20:05 AM UTC 24
Peak memory 216792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274753943 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1274753943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.539942232
Short name T481
Test name
Test status
Simulation time 93056757 ps
CPU time 1.59 seconds
Started Oct 09 10:20:03 AM UTC 24
Finished Oct 09 10:20:05 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539942232 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.539942232
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_err.1531270797
Short name T480
Test name
Test status
Simulation time 19134827 ps
CPU time 1.52 seconds
Started Oct 09 10:20:03 AM UTC 24
Finished Oct 09 10:20:05 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531270797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.1531270797
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_genbits.285332513
Short name T477
Test name
Test status
Simulation time 43410724 ps
CPU time 1.29 seconds
Started Oct 09 10:20:00 AM UTC 24
Finished Oct 09 10:20:03 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285332513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_genbits.285332513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_intr.4109816551
Short name T478
Test name
Test status
Simulation time 29299166 ps
CPU time 1.44 seconds
Started Oct 09 10:20:01 AM UTC 24
Finished Oct 09 10:20:04 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109816551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.4109816551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_smoke.2059626101
Short name T475
Test name
Test status
Simulation time 17838150 ps
CPU time 1.32 seconds
Started Oct 09 10:20:00 AM UTC 24
Finished Oct 09 10:20:02 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059626101 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.2059626101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_stress_all.4165531013
Short name T485
Test name
Test status
Simulation time 830557939 ps
CPU time 6.47 seconds
Started Oct 09 10:20:00 AM UTC 24
Finished Oct 09 10:20:08 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165531013 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4165531013
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.3343118124
Short name T811
Test name
Test status
Simulation time 37399429582 ps
CPU time 135.31 seconds
Started Oct 09 10:20:01 AM UTC 24
Finished Oct 09 10:22:19 AM UTC 24
Peak memory 230308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3343118124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all
_with_rand_reset.3343118124
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_alert_test.4162499318
Short name T491
Test name
Test status
Simulation time 17507468 ps
CPU time 1.27 seconds
Started Oct 09 10:20:09 AM UTC 24
Finished Oct 09 10:20:11 AM UTC 24
Peak memory 216908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162499318 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4162499318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_disable.1934187962
Short name T489
Test name
Test status
Simulation time 12663490 ps
CPU time 1.39 seconds
Started Oct 09 10:20:07 AM UTC 24
Finished Oct 09 10:20:10 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934187962 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1934187962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.260353364
Short name T490
Test name
Test status
Simulation time 48831642 ps
CPU time 1.47 seconds
Started Oct 09 10:20:08 AM UTC 24
Finished Oct 09 10:20:10 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260353364 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.260353364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_err.2189120600
Short name T488
Test name
Test status
Simulation time 44579934 ps
CPU time 1.65 seconds
Started Oct 09 10:20:06 AM UTC 24
Finished Oct 09 10:20:09 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189120600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.2189120600
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_genbits.105059951
Short name T486
Test name
Test status
Simulation time 48748699 ps
CPU time 3.01 seconds
Started Oct 09 10:20:04 AM UTC 24
Finished Oct 09 10:20:08 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105059951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_genbits.105059951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_intr.3473282025
Short name T487
Test name
Test status
Simulation time 24810367 ps
CPU time 1.43 seconds
Started Oct 09 10:20:06 AM UTC 24
Finished Oct 09 10:20:09 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473282025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.3473282025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_smoke.1729462319
Short name T482
Test name
Test status
Simulation time 16899294 ps
CPU time 1.28 seconds
Started Oct 09 10:20:04 AM UTC 24
Finished Oct 09 10:20:06 AM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729462319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.1729462319
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_stress_all.1396175342
Short name T484
Test name
Test status
Simulation time 22749295 ps
CPU time 1.62 seconds
Started Oct 09 10:20:05 AM UTC 24
Finished Oct 09 10:20:08 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396175342 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1396175342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.4291503764
Short name T625
Test name
Test status
Simulation time 2787216849 ps
CPU time 76.9 seconds
Started Oct 09 10:20:06 AM UTC 24
Finished Oct 09 10:21:25 AM UTC 24
Peak memory 230496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4291503764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all
_with_rand_reset.4291503764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_alert.813007302
Short name T136
Test name
Test status
Simulation time 23144017 ps
CPU time 1.78 seconds
Started Oct 09 10:20:11 AM UTC 24
Finished Oct 09 10:20:14 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813007302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_alert.813007302
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_alert_test.648777955
Short name T498
Test name
Test status
Simulation time 28166568 ps
CPU time 1.63 seconds
Started Oct 09 10:20:12 AM UTC 24
Finished Oct 09 10:20:15 AM UTC 24
Peak memory 216956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648777955 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.648777955
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_disable.3936252890
Short name T494
Test name
Test status
Simulation time 40267284 ps
CPU time 1.29 seconds
Started Oct 09 10:20:12 AM UTC 24
Finished Oct 09 10:20:15 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936252890 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3936252890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.2531991036
Short name T497
Test name
Test status
Simulation time 47854711 ps
CPU time 1.65 seconds
Started Oct 09 10:20:12 AM UTC 24
Finished Oct 09 10:20:15 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531991036 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.2531991036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_err.1719264299
Short name T153
Test name
Test status
Simulation time 54575240 ps
CPU time 1.58 seconds
Started Oct 09 10:20:11 AM UTC 24
Finished Oct 09 10:20:14 AM UTC 24
Peak memory 246752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719264299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.edn_err.1719264299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_intr.2035167031
Short name T493
Test name
Test status
Simulation time 42437021 ps
CPU time 1.31 seconds
Started Oct 09 10:20:10 AM UTC 24
Finished Oct 09 10:20:12 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035167031 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.2035167031
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_smoke.600687279
Short name T492
Test name
Test status
Simulation time 36520549 ps
CPU time 1.42 seconds
Started Oct 09 10:20:09 AM UTC 24
Finished Oct 09 10:20:11 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600687279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_smoke.600687279
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_stress_all.3574723883
Short name T499
Test name
Test status
Simulation time 211609030 ps
CPU time 4.4 seconds
Started Oct 09 10:20:10 AM UTC 24
Finished Oct 09 10:20:15 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574723883 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3574723883
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.1276329344
Short name T748
Test name
Test status
Simulation time 18934986698 ps
CPU time 113.44 seconds
Started Oct 09 10:20:10 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 230364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1276329344 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all
_with_rand_reset.1276329344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_alert.440506492
Short name T272
Test name
Test status
Simulation time 49811987 ps
CPU time 1.87 seconds
Started Oct 09 10:20:16 AM UTC 24
Finished Oct 09 10:20:19 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440506492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.edn_alert.440506492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_alert_test.1132538653
Short name T501
Test name
Test status
Simulation time 21802683 ps
CPU time 1.43 seconds
Started Oct 09 10:20:16 AM UTC 24
Finished Oct 09 10:20:18 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132538653 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1132538653
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.2596230048
Short name T502
Test name
Test status
Simulation time 28047421 ps
CPU time 1.65 seconds
Started Oct 09 10:20:16 AM UTC 24
Finished Oct 09 10:20:19 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596230048 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.2596230048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_err.4005565249
Short name T154
Test name
Test status
Simulation time 50582723 ps
CPU time 1.41 seconds
Started Oct 09 10:20:16 AM UTC 24
Finished Oct 09 10:20:18 AM UTC 24
Peak memory 231056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005565249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.4005565249
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_genbits.4061993825
Short name T500
Test name
Test status
Simulation time 96943353 ps
CPU time 1.69 seconds
Started Oct 09 10:20:13 AM UTC 24
Finished Oct 09 10:20:16 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061993825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4061993825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_intr.156273907
Short name T108
Test name
Test status
Simulation time 24263438 ps
CPU time 1.43 seconds
Started Oct 09 10:20:16 AM UTC 24
Finished Oct 09 10:20:18 AM UTC 24
Peak memory 228972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156273907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.156273907
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_smoke.2003201695
Short name T496
Test name
Test status
Simulation time 25623760 ps
CPU time 1.28 seconds
Started Oct 09 10:20:12 AM UTC 24
Finished Oct 09 10:20:15 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003201695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.2003201695
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/39.edn_stress_all.1666264182
Short name T504
Test name
Test status
Simulation time 3455798848 ps
CPU time 6.19 seconds
Started Oct 09 10:20:15 AM UTC 24
Finished Oct 09 10:20:22 AM UTC 24
Peak memory 230376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666264182 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1666264182
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_alert.3104325875
Short name T126
Test name
Test status
Simulation time 86494497 ps
CPU time 1.75 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:14 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104325875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.3104325875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_alert_test.2567765630
Short name T270
Test name
Test status
Simulation time 116408620 ps
CPU time 1.33 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:15 AM UTC 24
Peak memory 227356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567765630 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2567765630
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_disable.903210614
Short name T184
Test name
Test status
Simulation time 103091789 ps
CPU time 1.17 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:15 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903210614 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.903210614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.2237358595
Short name T21
Test name
Test status
Simulation time 94263399 ps
CPU time 1.43 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:15 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237358595 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.2237358595
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_err.21944101
Short name T122
Test name
Test status
Simulation time 26729500 ps
CPU time 1.22 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:14 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21944101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.edn_err.21944101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_genbits.3675379212
Short name T49
Test name
Test status
Simulation time 33706453 ps
CPU time 1.45 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:14 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675379212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3675379212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_intr.1681094781
Short name T33
Test name
Test status
Simulation time 23604504 ps
CPU time 1.27 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:14 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681094781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.1681094781
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_sec_cm.1241067801
Short name T60
Test name
Test status
Simulation time 4228253151 ps
CPU time 11.04 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:25 AM UTC 24
Peak memory 260912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241067801 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1241067801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_smoke.3097240591
Short name T362
Test name
Test status
Simulation time 44584559 ps
CPU time 1.25 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:13 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097240591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.3097240591
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/4.edn_stress_all.3049645692
Short name T110
Test name
Test status
Simulation time 717965113 ps
CPU time 5.28 seconds
Started Oct 09 10:18:11 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 228192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049645692 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3049645692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_alert.4137970614
Short name T170
Test name
Test status
Simulation time 27142283 ps
CPU time 1.94 seconds
Started Oct 09 10:20:19 AM UTC 24
Finished Oct 09 10:20:22 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137970614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.4137970614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_alert_test.1719821610
Short name T508
Test name
Test status
Simulation time 69707054 ps
CPU time 1.28 seconds
Started Oct 09 10:20:23 AM UTC 24
Finished Oct 09 10:20:25 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719821610 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1719821610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_disable.2875877290
Short name T225
Test name
Test status
Simulation time 16922114 ps
CPU time 1.35 seconds
Started Oct 09 10:20:21 AM UTC 24
Finished Oct 09 10:20:23 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875877290 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2875877290
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.2696042794
Short name T306
Test name
Test status
Simulation time 107765183 ps
CPU time 1.71 seconds
Started Oct 09 10:20:23 AM UTC 24
Finished Oct 09 10:20:25 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696042794 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.2696042794
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_err.3733862716
Short name T506
Test name
Test status
Simulation time 76413044 ps
CPU time 1.47 seconds
Started Oct 09 10:20:20 AM UTC 24
Finished Oct 09 10:20:22 AM UTC 24
Peak memory 237364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733862716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.3733862716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_genbits.1421065579
Short name T505
Test name
Test status
Simulation time 61441668 ps
CPU time 1.69 seconds
Started Oct 09 10:20:19 AM UTC 24
Finished Oct 09 10:20:22 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421065579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1421065579
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_intr.2188457818
Short name T507
Test name
Test status
Simulation time 23175226 ps
CPU time 1.69 seconds
Started Oct 09 10:20:19 AM UTC 24
Finished Oct 09 10:20:22 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188457818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.2188457818
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_smoke.1774120460
Short name T503
Test name
Test status
Simulation time 21633537 ps
CPU time 1.47 seconds
Started Oct 09 10:20:17 AM UTC 24
Finished Oct 09 10:20:20 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774120460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.1774120460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/40.edn_stress_all.773130531
Short name T511
Test name
Test status
Simulation time 212967428 ps
CPU time 6.18 seconds
Started Oct 09 10:20:19 AM UTC 24
Finished Oct 09 10:20:27 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773130531 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.773130531
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_alert.533658860
Short name T185
Test name
Test status
Simulation time 24991175 ps
CPU time 1.25 seconds
Started Oct 09 10:20:25 AM UTC 24
Finished Oct 09 10:20:28 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533658860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.edn_alert.533658860
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_alert_test.3428293772
Short name T516
Test name
Test status
Simulation time 24402493 ps
CPU time 1.28 seconds
Started Oct 09 10:20:27 AM UTC 24
Finished Oct 09 10:20:29 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428293772 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3428293772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_disable.1985925452
Short name T515
Test name
Test status
Simulation time 57308559 ps
CPU time 1.31 seconds
Started Oct 09 10:20:26 AM UTC 24
Finished Oct 09 10:20:29 AM UTC 24
Peak memory 216792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985925452 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1985925452
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.3474343266
Short name T517
Test name
Test status
Simulation time 63628214 ps
CPU time 1.67 seconds
Started Oct 09 10:20:27 AM UTC 24
Finished Oct 09 10:20:29 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474343266 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.3474343266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_err.3453835529
Short name T513
Test name
Test status
Simulation time 20778022 ps
CPU time 1.32 seconds
Started Oct 09 10:20:26 AM UTC 24
Finished Oct 09 10:20:29 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453835529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.3453835529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_genbits.2152018438
Short name T358
Test name
Test status
Simulation time 99290625 ps
CPU time 2.3 seconds
Started Oct 09 10:20:23 AM UTC 24
Finished Oct 09 10:20:26 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152018438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2152018438
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_intr.3989476185
Short name T510
Test name
Test status
Simulation time 33402018 ps
CPU time 1.18 seconds
Started Oct 09 10:20:24 AM UTC 24
Finished Oct 09 10:20:26 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989476185 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.3989476185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_smoke.1548515172
Short name T509
Test name
Test status
Simulation time 81698974 ps
CPU time 1.4 seconds
Started Oct 09 10:20:23 AM UTC 24
Finished Oct 09 10:20:25 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548515172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.1548515172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_stress_all.4075900886
Short name T514
Test name
Test status
Simulation time 545975242 ps
CPU time 3.64 seconds
Started Oct 09 10:20:24 AM UTC 24
Finished Oct 09 10:20:29 AM UTC 24
Peak memory 228000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075900886 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4075900886
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.155159408
Short name T659
Test name
Test status
Simulation time 6090091801 ps
CPU time 72.43 seconds
Started Oct 09 10:20:24 AM UTC 24
Finished Oct 09 10:21:38 AM UTC 24
Peak memory 230392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=155159408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_
with_rand_reset.155159408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_alert.82619054
Short name T179
Test name
Test status
Simulation time 25062140 ps
CPU time 1.72 seconds
Started Oct 09 10:20:29 AM UTC 24
Finished Oct 09 10:20:32 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82619054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_alert.82619054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_alert_test.1641470802
Short name T522
Test name
Test status
Simulation time 24774305 ps
CPU time 1.25 seconds
Started Oct 09 10:20:30 AM UTC 24
Finished Oct 09 10:20:33 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641470802 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1641470802
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_disable.1709848373
Short name T521
Test name
Test status
Simulation time 12052897 ps
CPU time 1.14 seconds
Started Oct 09 10:20:30 AM UTC 24
Finished Oct 09 10:20:32 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709848373 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1709848373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.2412725325
Short name T526
Test name
Test status
Simulation time 128090805 ps
CPU time 1.87 seconds
Started Oct 09 10:20:30 AM UTC 24
Finished Oct 09 10:20:33 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412725325 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2412725325
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_err.769375421
Short name T523
Test name
Test status
Simulation time 18008753 ps
CPU time 1.45 seconds
Started Oct 09 10:20:30 AM UTC 24
Finished Oct 09 10:20:33 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769375421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.edn_err.769375421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_genbits.4175163527
Short name T519
Test name
Test status
Simulation time 59071221 ps
CPU time 1.58 seconds
Started Oct 09 10:20:28 AM UTC 24
Finished Oct 09 10:20:30 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175163527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4175163527
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_intr.4183864930
Short name T520
Test name
Test status
Simulation time 37705676 ps
CPU time 1.22 seconds
Started Oct 09 10:20:29 AM UTC 24
Finished Oct 09 10:20:31 AM UTC 24
Peak memory 226852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183864930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.4183864930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_smoke.323598584
Short name T518
Test name
Test status
Simulation time 33043619 ps
CPU time 1.35 seconds
Started Oct 09 10:20:28 AM UTC 24
Finished Oct 09 10:20:30 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323598584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_smoke.323598584
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/42.edn_stress_all.4219091671
Short name T326
Test name
Test status
Simulation time 1469099537 ps
CPU time 5.26 seconds
Started Oct 09 10:20:28 AM UTC 24
Finished Oct 09 10:20:34 AM UTC 24
Peak memory 228188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219091671 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4219091671
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_alert.2529298596
Short name T533
Test name
Test status
Simulation time 43572066 ps
CPU time 1.66 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:37 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529298596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.2529298596
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_alert_test.3849991795
Short name T530
Test name
Test status
Simulation time 14026215 ps
CPU time 1.11 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:36 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849991795 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3849991795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_disable.2184699916
Short name T531
Test name
Test status
Simulation time 70318225 ps
CPU time 1.3 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:36 AM UTC 24
Peak memory 227028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184699916 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2184699916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.49381532
Short name T307
Test name
Test status
Simulation time 177065412 ps
CPU time 1.49 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:37 AM UTC 24
Peak memory 226916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49381532 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.49381532
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_err.941281396
Short name T534
Test name
Test status
Simulation time 24735028 ps
CPU time 1.67 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:37 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941281396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.edn_err.941281396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_genbits.216096437
Short name T528
Test name
Test status
Simulation time 36742883 ps
CPU time 2.28 seconds
Started Oct 09 10:20:31 AM UTC 24
Finished Oct 09 10:20:35 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216096437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_genbits.216096437
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_intr.2677270718
Short name T529
Test name
Test status
Simulation time 37076402 ps
CPU time 1.23 seconds
Started Oct 09 10:20:33 AM UTC 24
Finished Oct 09 10:20:35 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677270718 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.2677270718
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_smoke.2925209889
Short name T525
Test name
Test status
Simulation time 16560765 ps
CPU time 1.46 seconds
Started Oct 09 10:20:30 AM UTC 24
Finished Oct 09 10:20:33 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925209889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.2925209889
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_stress_all.1738127003
Short name T536
Test name
Test status
Simulation time 2139050654 ps
CPU time 4.37 seconds
Started Oct 09 10:20:32 AM UTC 24
Finished Oct 09 10:20:37 AM UTC 24
Peak memory 227992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738127003 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1738127003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.1362667370
Short name T642
Test name
Test status
Simulation time 7902490763 ps
CPU time 56.55 seconds
Started Oct 09 10:20:33 AM UTC 24
Finished Oct 09 10:21:31 AM UTC 24
Peak memory 230452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1362667370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all
_with_rand_reset.1362667370
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_alert.4150419046
Short name T186
Test name
Test status
Simulation time 75324452 ps
CPU time 1.66 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150419046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.4150419046
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_alert_test.2907963530
Short name T541
Test name
Test status
Simulation time 52242686 ps
CPU time 1.3 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907963530 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2907963530
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_disable.954455708
Short name T543
Test name
Test status
Simulation time 23204726 ps
CPU time 1.37 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954455708 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.954455708
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.3444399921
Short name T542
Test name
Test status
Simulation time 97762048 ps
CPU time 1.4 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444399921 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.3444399921
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_err.2215633051
Short name T189
Test name
Test status
Simulation time 27414542 ps
CPU time 1.53 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 238228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215633051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.2215633051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_genbits.2287737632
Short name T535
Test name
Test status
Simulation time 61071191 ps
CPU time 1.66 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:37 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287737632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2287737632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_intr.1090567426
Short name T538
Test name
Test status
Simulation time 20755578 ps
CPU time 1.5 seconds
Started Oct 09 10:20:35 AM UTC 24
Finished Oct 09 10:20:38 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090567426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.1090567426
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_smoke.3830091607
Short name T532
Test name
Test status
Simulation time 167001960 ps
CPU time 1.28 seconds
Started Oct 09 10:20:34 AM UTC 24
Finished Oct 09 10:20:36 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830091607 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.3830091607
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/44.edn_stress_all.1815605916
Short name T547
Test name
Test status
Simulation time 392363380 ps
CPU time 7.3 seconds
Started Oct 09 10:20:35 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815605916 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1815605916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_alert_test.581956476
Short name T546
Test name
Test status
Simulation time 54291593 ps
CPU time 1.07 seconds
Started Oct 09 10:20:41 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581956476 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.581956476
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3292333358
Short name T308
Test name
Test status
Simulation time 59426028 ps
CPU time 1.39 seconds
Started Oct 09 10:20:41 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292333358 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3292333358
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_err.2622888558
Short name T221
Test name
Test status
Simulation time 52088573 ps
CPU time 1.8 seconds
Started Oct 09 10:20:41 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 243272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622888558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.2622888558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_genbits.1139851635
Short name T544
Test name
Test status
Simulation time 55800566 ps
CPU time 1.56 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139851635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1139851635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_intr.624181576
Short name T545
Test name
Test status
Simulation time 45105893 ps
CPU time 1.37 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:41 AM UTC 24
Peak memory 226976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624181576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.624181576
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_smoke.1106362252
Short name T540
Test name
Test status
Simulation time 45866558 ps
CPU time 1.18 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:40 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106362252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.1106362252
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_stress_all.2678328934
Short name T549
Test name
Test status
Simulation time 152717541 ps
CPU time 4.71 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678328934 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2678328934
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.163140713
Short name T255
Test name
Test status
Simulation time 14038278455 ps
CPU time 39.57 seconds
Started Oct 09 10:20:38 AM UTC 24
Finished Oct 09 10:21:19 AM UTC 24
Peak memory 230300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=163140713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_
with_rand_reset.163140713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_alert.13507010
Short name T552
Test name
Test status
Simulation time 27872423 ps
CPU time 1.44 seconds
Started Oct 09 10:20:43 AM UTC 24
Finished Oct 09 10:20:45 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13507010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_alert.13507010
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_alert_test.3806197504
Short name T553
Test name
Test status
Simulation time 33922527 ps
CPU time 1.07 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:20:47 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806197504 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3806197504
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.348922000
Short name T555
Test name
Test status
Simulation time 206946119 ps
CPU time 1.6 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348922000 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.348922000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_err.3233856045
Short name T218
Test name
Test status
Simulation time 256370481 ps
CPU time 1.55 seconds
Started Oct 09 10:20:44 AM UTC 24
Finished Oct 09 10:20:47 AM UTC 24
Peak memory 242928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233856045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.3233856045
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_genbits.2370469405
Short name T347
Test name
Test status
Simulation time 63440627 ps
CPU time 1.76 seconds
Started Oct 09 10:20:42 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 231268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370469405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2370469405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_intr.2533563756
Short name T550
Test name
Test status
Simulation time 106952131 ps
CPU time 1.54 seconds
Started Oct 09 10:20:42 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 237372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533563756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.2533563756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_smoke.1155862242
Short name T548
Test name
Test status
Simulation time 24329385 ps
CPU time 1.18 seconds
Started Oct 09 10:20:42 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155862242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.1155862242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_stress_all.1671964335
Short name T551
Test name
Test status
Simulation time 88331978 ps
CPU time 1.64 seconds
Started Oct 09 10:20:42 AM UTC 24
Finished Oct 09 10:20:44 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671964335 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1671964335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.327158347
Short name T647
Test name
Test status
Simulation time 1997802641 ps
CPU time 50.34 seconds
Started Oct 09 10:20:42 AM UTC 24
Finished Oct 09 10:21:34 AM UTC 24
Peak memory 230268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=327158347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_
with_rand_reset.327158347
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_alert.3185556555
Short name T559
Test name
Test status
Simulation time 350650064 ps
CPU time 1.58 seconds
Started Oct 09 10:20:46 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185556555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.3185556555
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_alert_test.3246313482
Short name T562
Test name
Test status
Simulation time 26549481 ps
CPU time 1.42 seconds
Started Oct 09 10:20:48 AM UTC 24
Finished Oct 09 10:20:50 AM UTC 24
Peak memory 216908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246313482 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3246313482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_disable.1217010401
Short name T554
Test name
Test status
Simulation time 26478055 ps
CPU time 1.07 seconds
Started Oct 09 10:20:46 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217010401 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1217010401
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.2044668299
Short name T561
Test name
Test status
Simulation time 81444014 ps
CPU time 1.22 seconds
Started Oct 09 10:20:47 AM UTC 24
Finished Oct 09 10:20:49 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044668299 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.2044668299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_err.450751917
Short name T560
Test name
Test status
Simulation time 19940035 ps
CPU time 1.58 seconds
Started Oct 09 10:20:46 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450751917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.edn_err.450751917
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_genbits.2355824518
Short name T361
Test name
Test status
Simulation time 35909563 ps
CPU time 1.74 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355824518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2355824518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_intr.87012
Short name T557
Test name
Test status
Simulation time 24176145 ps
CPU time 1.5 seconds
Started Oct 09 10:20:46 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 47.edn_intr.87012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_smoke.357026037
Short name T556
Test name
Test status
Simulation time 19739581 ps
CPU time 1.42 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357026037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.edn_smoke.357026037
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_stress_all.1437506771
Short name T558
Test name
Test status
Simulation time 43375622 ps
CPU time 1.65 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:20:48 AM UTC 24
Peak memory 229160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437506771 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1437506771
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.3869229489
Short name T728
Test name
Test status
Simulation time 5311439172 ps
CPU time 72.76 seconds
Started Oct 09 10:20:45 AM UTC 24
Finished Oct 09 10:22:00 AM UTC 24
Peak memory 230380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3869229489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all
_with_rand_reset.3869229489
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_alert.2503226257
Short name T193
Test name
Test status
Simulation time 81075191 ps
CPU time 1.56 seconds
Started Oct 09 10:20:49 AM UTC 24
Finished Oct 09 10:20:52 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503226257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.2503226257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_alert_test.3853934020
Short name T566
Test name
Test status
Simulation time 17559481 ps
CPU time 1.45 seconds
Started Oct 09 10:20:50 AM UTC 24
Finished Oct 09 10:20:52 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853934020 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3853934020
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_disable.3158976912
Short name T564
Test name
Test status
Simulation time 32163122 ps
CPU time 1.28 seconds
Started Oct 09 10:20:49 AM UTC 24
Finished Oct 09 10:20:52 AM UTC 24
Peak memory 227032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158976912 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3158976912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.1414947426
Short name T567
Test name
Test status
Simulation time 55559287 ps
CPU time 1.69 seconds
Started Oct 09 10:20:50 AM UTC 24
Finished Oct 09 10:20:52 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414947426 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.1414947426
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_err.3142587917
Short name T565
Test name
Test status
Simulation time 78220890 ps
CPU time 1.61 seconds
Started Oct 09 10:20:49 AM UTC 24
Finished Oct 09 10:20:52 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142587917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.3142587917
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_genbits.4055663936
Short name T977
Test name
Test status
Simulation time 13747695875 ps
CPU time 162.22 seconds
Started Oct 09 10:20:48 AM UTC 24
Finished Oct 09 10:23:33 AM UTC 24
Peak memory 230392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055663936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4055663936
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_intr.238982238
Short name T107
Test name
Test status
Simulation time 25281284 ps
CPU time 1.28 seconds
Started Oct 09 10:20:49 AM UTC 24
Finished Oct 09 10:20:52 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238982238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.238982238
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_smoke.2772076320
Short name T563
Test name
Test status
Simulation time 18173030 ps
CPU time 1.45 seconds
Started Oct 09 10:20:48 AM UTC 24
Finished Oct 09 10:20:50 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772076320 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.2772076320
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_stress_all.1929706117
Short name T574
Test name
Test status
Simulation time 624577955 ps
CPU time 5.71 seconds
Started Oct 09 10:20:49 AM UTC 24
Finished Oct 09 10:20:56 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929706117 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1929706117
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.2304919023
Short name T751
Test name
Test status
Simulation time 2790281735 ps
CPU time 75.11 seconds
Started Oct 09 10:20:49 AM UTC 24
Finished Oct 09 10:22:06 AM UTC 24
Peak memory 230492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2304919023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all
_with_rand_reset.2304919023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_alert.1672193175
Short name T570
Test name
Test status
Simulation time 32739915 ps
CPU time 1.53 seconds
Started Oct 09 10:20:53 AM UTC 24
Finished Oct 09 10:20:56 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672193175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.1672193175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_alert_test.921690052
Short name T577
Test name
Test status
Simulation time 16595553 ps
CPU time 1.46 seconds
Started Oct 09 10:20:54 AM UTC 24
Finished Oct 09 10:20:57 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921690052 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.921690052
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_disable.824918560
Short name T571
Test name
Test status
Simulation time 12145213 ps
CPU time 1.34 seconds
Started Oct 09 10:20:53 AM UTC 24
Finished Oct 09 10:20:56 AM UTC 24
Peak memory 216800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824918560 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.824918560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.3481738264
Short name T575
Test name
Test status
Simulation time 22550713 ps
CPU time 1.62 seconds
Started Oct 09 10:20:53 AM UTC 24
Finished Oct 09 10:20:56 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481738264 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.3481738264
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_err.1225074785
Short name T573
Test name
Test status
Simulation time 19726301 ps
CPU time 1.5 seconds
Started Oct 09 10:20:53 AM UTC 24
Finished Oct 09 10:20:56 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225074785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.1225074785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_genbits.3967503201
Short name T569
Test name
Test status
Simulation time 79222191 ps
CPU time 2.79 seconds
Started Oct 09 10:20:51 AM UTC 24
Finished Oct 09 10:20:55 AM UTC 24
Peak memory 230248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967503201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3967503201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_intr.2269787999
Short name T572
Test name
Test status
Simulation time 23118883 ps
CPU time 1.63 seconds
Started Oct 09 10:20:53 AM UTC 24
Finished Oct 09 10:20:56 AM UTC 24
Peak memory 226988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269787999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.2269787999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_smoke.3975638524
Short name T568
Test name
Test status
Simulation time 20603296 ps
CPU time 1.49 seconds
Started Oct 09 10:20:51 AM UTC 24
Finished Oct 09 10:20:53 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975638524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.3975638524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/49.edn_stress_all.2408153370
Short name T576
Test name
Test status
Simulation time 482447758 ps
CPU time 4 seconds
Started Oct 09 10:20:52 AM UTC 24
Finished Oct 09 10:20:57 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408153370 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2408153370
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_alert_test.411779366
Short name T363
Test name
Test status
Simulation time 30123063 ps
CPU time 1.38 seconds
Started Oct 09 10:18:16 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411779366 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.411779366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_disable.3271835809
Short name T177
Test name
Test status
Simulation time 19127045 ps
CPU time 1.3 seconds
Started Oct 09 10:18:15 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271835809 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3271835809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.2091967029
Short name T22
Test name
Test status
Simulation time 68953394 ps
CPU time 1.52 seconds
Started Oct 09 10:18:15 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 226916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091967029 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.2091967029
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_err.2369509042
Short name T7
Test name
Test status
Simulation time 140687215 ps
CPU time 1.59 seconds
Started Oct 09 10:18:15 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 246872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369509042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.2369509042
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_intr.3233241160
Short name T57
Test name
Test status
Simulation time 22449203 ps
CPU time 1.72 seconds
Started Oct 09 10:18:14 AM UTC 24
Finished Oct 09 10:18:17 AM UTC 24
Peak memory 238360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233241160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.3233241160
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_regwen.2184049763
Short name T121
Test name
Test status
Simulation time 41399747 ps
CPU time 1.43 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:15 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184049763 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2184049763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_smoke.1725925442
Short name T123
Test name
Test status
Simulation time 69659432 ps
CPU time 1.22 seconds
Started Oct 09 10:18:13 AM UTC 24
Finished Oct 09 10:18:15 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725925442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.1725925442
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_stress_all.991644521
Short name T111
Test name
Test status
Simulation time 137814331 ps
CPU time 3.65 seconds
Started Oct 09 10:18:14 AM UTC 24
Finished Oct 09 10:18:19 AM UTC 24
Peak memory 228068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991644521 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.991644521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.3254825395
Short name T39
Test name
Test status
Simulation time 3143020153 ps
CPU time 48 seconds
Started Oct 09 10:18:14 AM UTC 24
Finished Oct 09 10:19:04 AM UTC 24
Peak memory 230368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3254825395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.3254825395
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/50.edn_alert.248018333
Short name T166
Test name
Test status
Simulation time 112488752 ps
CPU time 1.49 seconds
Started Oct 09 10:20:57 AM UTC 24
Finished Oct 09 10:20:59 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248018333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 50.edn_alert.248018333
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/50.edn_err.2159070500
Short name T134
Test name
Test status
Simulation time 28732075 ps
CPU time 1.59 seconds
Started Oct 09 10:20:57 AM UTC 24
Finished Oct 09 10:20:59 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159070500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.2159070500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/50.edn_genbits.2419683143
Short name T578
Test name
Test status
Simulation time 81390746 ps
CPU time 1.46 seconds
Started Oct 09 10:20:55 AM UTC 24
Finished Oct 09 10:20:58 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419683143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2419683143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/51.edn_alert.3491270330
Short name T149
Test name
Test status
Simulation time 315796841 ps
CPU time 1.97 seconds
Started Oct 09 10:20:57 AM UTC 24
Finished Oct 09 10:21:00 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491270330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.3491270330
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/51.edn_err.1973910476
Short name T183
Test name
Test status
Simulation time 18360415 ps
CPU time 1.64 seconds
Started Oct 09 10:20:57 AM UTC 24
Finished Oct 09 10:20:59 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973910476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.1973910476
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/51.edn_genbits.889878563
Short name T579
Test name
Test status
Simulation time 64570961 ps
CPU time 1.59 seconds
Started Oct 09 10:20:57 AM UTC 24
Finished Oct 09 10:20:59 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889878563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 51.edn_genbits.889878563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/52.edn_alert.2434829494
Short name T194
Test name
Test status
Simulation time 78905480 ps
CPU time 1.63 seconds
Started Oct 09 10:20:58 AM UTC 24
Finished Oct 09 10:21:01 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434829494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 52.edn_alert.2434829494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/52.edn_err.2784166542
Short name T580
Test name
Test status
Simulation time 64322132 ps
CPU time 1.27 seconds
Started Oct 09 10:20:58 AM UTC 24
Finished Oct 09 10:21:00 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784166542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.2784166542
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/52.edn_genbits.3125508260
Short name T581
Test name
Test status
Simulation time 120663715 ps
CPU time 2.47 seconds
Started Oct 09 10:20:57 AM UTC 24
Finished Oct 09 10:21:00 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125508260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3125508260
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/53.edn_alert.3864714642
Short name T584
Test name
Test status
Simulation time 60981982 ps
CPU time 1.77 seconds
Started Oct 09 10:21:00 AM UTC 24
Finished Oct 09 10:21:03 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864714642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.3864714642
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/53.edn_err.2491046433
Short name T583
Test name
Test status
Simulation time 31389031 ps
CPU time 1.38 seconds
Started Oct 09 10:21:00 AM UTC 24
Finished Oct 09 10:21:03 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491046433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.2491046433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/53.edn_genbits.3775119086
Short name T582
Test name
Test status
Simulation time 59326510 ps
CPU time 1.48 seconds
Started Oct 09 10:20:59 AM UTC 24
Finished Oct 09 10:21:02 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775119086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3775119086
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/54.edn_alert.1312049533
Short name T585
Test name
Test status
Simulation time 81058007 ps
CPU time 1.95 seconds
Started Oct 09 10:21:00 AM UTC 24
Finished Oct 09 10:21:04 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312049533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 54.edn_alert.1312049533
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/54.edn_genbits.797490365
Short name T586
Test name
Test status
Simulation time 47524870 ps
CPU time 2.02 seconds
Started Oct 09 10:21:00 AM UTC 24
Finished Oct 09 10:21:05 AM UTC 24
Peak memory 230248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797490365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.edn_genbits.797490365
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/55.edn_alert.4240816498
Short name T150
Test name
Test status
Simulation time 34661811 ps
CPU time 2.01 seconds
Started Oct 09 10:21:02 AM UTC 24
Finished Oct 09 10:21:05 AM UTC 24
Peak memory 228692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240816498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.4240816498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/55.edn_err.456622813
Short name T205
Test name
Test status
Simulation time 21106837 ps
CPU time 1.59 seconds
Started Oct 09 10:21:02 AM UTC 24
Finished Oct 09 10:21:05 AM UTC 24
Peak memory 244400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456622813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 55.edn_err.456622813
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/55.edn_genbits.985253667
Short name T587
Test name
Test status
Simulation time 93556868 ps
CPU time 2 seconds
Started Oct 09 10:21:02 AM UTC 24
Finished Oct 09 10:21:05 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985253667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 55.edn_genbits.985253667
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/56.edn_alert.341628168
Short name T309
Test name
Test status
Simulation time 27936545 ps
CPU time 1.72 seconds
Started Oct 09 10:21:04 AM UTC 24
Finished Oct 09 10:21:07 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341628168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 56.edn_alert.341628168
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/56.edn_err.3407156535
Short name T588
Test name
Test status
Simulation time 21993851 ps
CPU time 1.39 seconds
Started Oct 09 10:21:04 AM UTC 24
Finished Oct 09 10:21:06 AM UTC 24
Peak memory 237184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407156535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.3407156535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/56.edn_genbits.1900362235
Short name T354
Test name
Test status
Simulation time 450253084 ps
CPU time 3 seconds
Started Oct 09 10:21:03 AM UTC 24
Finished Oct 09 10:21:07 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900362235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1900362235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/57.edn_alert.2826023098
Short name T589
Test name
Test status
Simulation time 20610830 ps
CPU time 1.46 seconds
Started Oct 09 10:21:05 AM UTC 24
Finished Oct 09 10:21:08 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826023098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.2826023098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/57.edn_err.3901319453
Short name T590
Test name
Test status
Simulation time 33128023 ps
CPU time 1.56 seconds
Started Oct 09 10:21:05 AM UTC 24
Finished Oct 09 10:21:08 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901319453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.3901319453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/57.edn_genbits.2601957807
Short name T15
Test name
Test status
Simulation time 46360140 ps
CPU time 1.72 seconds
Started Oct 09 10:21:05 AM UTC 24
Finished Oct 09 10:21:08 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601957807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2601957807
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/58.edn_alert.3041920081
Short name T592
Test name
Test status
Simulation time 28282478 ps
CPU time 1.8 seconds
Started Oct 09 10:21:06 AM UTC 24
Finished Oct 09 10:21:09 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041920081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.3041920081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/58.edn_err.3802223801
Short name T591
Test name
Test status
Simulation time 19670682 ps
CPU time 1.63 seconds
Started Oct 09 10:21:06 AM UTC 24
Finished Oct 09 10:21:09 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802223801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.3802223801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/58.edn_genbits.78418891
Short name T348
Test name
Test status
Simulation time 29688033 ps
CPU time 1.62 seconds
Started Oct 09 10:21:06 AM UTC 24
Finished Oct 09 10:21:09 AM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78418891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 58.edn_genbits.78418891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/59.edn_alert.2657620369
Short name T594
Test name
Test status
Simulation time 86494623 ps
CPU time 1.71 seconds
Started Oct 09 10:21:07 AM UTC 24
Finished Oct 09 10:21:10 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657620369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.2657620369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/59.edn_err.1409300629
Short name T593
Test name
Test status
Simulation time 23436820 ps
CPU time 1.44 seconds
Started Oct 09 10:21:08 AM UTC 24
Finished Oct 09 10:21:10 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409300629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.1409300629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/59.edn_genbits.3420883209
Short name T349
Test name
Test status
Simulation time 80486428 ps
CPU time 1.57 seconds
Started Oct 09 10:21:07 AM UTC 24
Finished Oct 09 10:21:10 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420883209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3420883209
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_alert.161950924
Short name T128
Test name
Test status
Simulation time 25237789 ps
CPU time 1.75 seconds
Started Oct 09 10:18:17 AM UTC 24
Finished Oct 09 10:18:20 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161950924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.edn_alert.161950924
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_alert_test.662680452
Short name T364
Test name
Test status
Simulation time 12966856 ps
CPU time 1.1 seconds
Started Oct 09 10:18:18 AM UTC 24
Finished Oct 09 10:18:21 AM UTC 24
Peak memory 216604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662680452 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.662680452
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.4045075586
Short name T97
Test name
Test status
Simulation time 45366163 ps
CPU time 1.44 seconds
Started Oct 09 10:18:18 AM UTC 24
Finished Oct 09 10:18:21 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045075586 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.4045075586
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_err.2762805704
Short name T209
Test name
Test status
Simulation time 65428897 ps
CPU time 1.63 seconds
Started Oct 09 10:18:17 AM UTC 24
Finished Oct 09 10:18:20 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762805704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.2762805704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_regwen.4137216088
Short name T115
Test name
Test status
Simulation time 16332092 ps
CPU time 1.3 seconds
Started Oct 09 10:18:16 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137216088 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.4137216088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_smoke.3286772097
Short name T271
Test name
Test status
Simulation time 31227987 ps
CPU time 1.34 seconds
Started Oct 09 10:18:16 AM UTC 24
Finished Oct 09 10:18:18 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286772097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.3286772097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/6.edn_stress_all.2509763798
Short name T117
Test name
Test status
Simulation time 350839658 ps
CPU time 6.84 seconds
Started Oct 09 10:18:17 AM UTC 24
Finished Oct 09 10:18:25 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509763798 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2509763798
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/60.edn_alert.1074357031
Short name T597
Test name
Test status
Simulation time 62742426 ps
CPU time 1.74 seconds
Started Oct 09 10:21:09 AM UTC 24
Finished Oct 09 10:21:12 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074357031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.1074357031
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/60.edn_err.3718780262
Short name T595
Test name
Test status
Simulation time 19446623 ps
CPU time 1.6 seconds
Started Oct 09 10:21:09 AM UTC 24
Finished Oct 09 10:21:12 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718780262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.3718780262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/60.edn_genbits.1272012794
Short name T596
Test name
Test status
Simulation time 94049378 ps
CPU time 1.68 seconds
Started Oct 09 10:21:09 AM UTC 24
Finished Oct 09 10:21:12 AM UTC 24
Peak memory 231320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272012794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1272012794
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/61.edn_alert.3680099729
Short name T599
Test name
Test status
Simulation time 51805477 ps
CPU time 1.77 seconds
Started Oct 09 10:21:10 AM UTC 24
Finished Oct 09 10:21:13 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680099729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.3680099729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/61.edn_err.2534192580
Short name T601
Test name
Test status
Simulation time 19032972 ps
CPU time 1.82 seconds
Started Oct 09 10:21:10 AM UTC 24
Finished Oct 09 10:21:14 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534192580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.2534192580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/61.edn_genbits.1322605391
Short name T598
Test name
Test status
Simulation time 44286493 ps
CPU time 2.18 seconds
Started Oct 09 10:21:09 AM UTC 24
Finished Oct 09 10:21:13 AM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322605391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1322605391
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/62.edn_alert.593508868
Short name T187
Test name
Test status
Simulation time 26937578 ps
CPU time 1.65 seconds
Started Oct 09 10:21:11 AM UTC 24
Finished Oct 09 10:21:15 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593508868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 62.edn_alert.593508868
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/62.edn_err.810610524
Short name T603
Test name
Test status
Simulation time 32393846 ps
CPU time 1.87 seconds
Started Oct 09 10:21:11 AM UTC 24
Finished Oct 09 10:21:15 AM UTC 24
Peak memory 231072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810610524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 62.edn_err.810610524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/62.edn_genbits.1678282887
Short name T600
Test name
Test status
Simulation time 65310133 ps
CPU time 1.82 seconds
Started Oct 09 10:21:10 AM UTC 24
Finished Oct 09 10:21:13 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678282887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1678282887
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/63.edn_alert.2503163902
Short name T605
Test name
Test status
Simulation time 28807351 ps
CPU time 1.95 seconds
Started Oct 09 10:21:14 AM UTC 24
Finished Oct 09 10:21:17 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503163902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.2503163902
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/63.edn_err.2461379317
Short name T228
Test name
Test status
Simulation time 20384890 ps
CPU time 1.43 seconds
Started Oct 09 10:21:14 AM UTC 24
Finished Oct 09 10:21:16 AM UTC 24
Peak memory 230996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461379317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.2461379317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/63.edn_genbits.1179244266
Short name T602
Test name
Test status
Simulation time 36884159 ps
CPU time 1.34 seconds
Started Oct 09 10:21:11 AM UTC 24
Finished Oct 09 10:21:14 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179244266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1179244266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/64.edn_alert.3370633655
Short name T151
Test name
Test status
Simulation time 53893418 ps
CPU time 1.75 seconds
Started Oct 09 10:21:14 AM UTC 24
Finished Oct 09 10:21:17 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370633655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.3370633655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/64.edn_err.565518021
Short name T143
Test name
Test status
Simulation time 73429132 ps
CPU time 1.6 seconds
Started Oct 09 10:21:14 AM UTC 24
Finished Oct 09 10:21:17 AM UTC 24
Peak memory 246612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565518021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 64.edn_err.565518021
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/64.edn_genbits.3769109271
Short name T606
Test name
Test status
Simulation time 130025071 ps
CPU time 1.92 seconds
Started Oct 09 10:21:14 AM UTC 24
Finished Oct 09 10:21:17 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769109271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3769109271
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/65.edn_alert.3609911974
Short name T607
Test name
Test status
Simulation time 39989195 ps
CPU time 1.58 seconds
Started Oct 09 10:21:15 AM UTC 24
Finished Oct 09 10:21:18 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609911974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.3609911974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/65.edn_err.3123626640
Short name T192
Test name
Test status
Simulation time 21180721 ps
CPU time 1.5 seconds
Started Oct 09 10:21:15 AM UTC 24
Finished Oct 09 10:21:18 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123626640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.3123626640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/65.edn_genbits.1353732680
Short name T604
Test name
Test status
Simulation time 44423789 ps
CPU time 1.57 seconds
Started Oct 09 10:21:14 AM UTC 24
Finished Oct 09 10:21:17 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353732680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1353732680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/66.edn_alert.827969435
Short name T608
Test name
Test status
Simulation time 31345791 ps
CPU time 1.89 seconds
Started Oct 09 10:21:16 AM UTC 24
Finished Oct 09 10:21:19 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827969435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 66.edn_alert.827969435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/66.edn_err.53472118
Short name T610
Test name
Test status
Simulation time 104135249 ps
CPU time 1.62 seconds
Started Oct 09 10:21:17 AM UTC 24
Finished Oct 09 10:21:20 AM UTC 24
Peak memory 242904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53472118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 66.edn_err.53472118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/66.edn_genbits.1005341169
Short name T614
Test name
Test status
Simulation time 72996865 ps
CPU time 3.84 seconds
Started Oct 09 10:21:15 AM UTC 24
Finished Oct 09 10:21:21 AM UTC 24
Peak memory 232272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005341169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1005341169
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/67.edn_alert.189396723
Short name T612
Test name
Test status
Simulation time 23267812 ps
CPU time 1.76 seconds
Started Oct 09 10:21:17 AM UTC 24
Finished Oct 09 10:21:20 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189396723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 67.edn_alert.189396723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/67.edn_err.3783500904
Short name T609
Test name
Test status
Simulation time 82878998 ps
CPU time 1.2 seconds
Started Oct 09 10:21:17 AM UTC 24
Finished Oct 09 10:21:20 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783500904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.3783500904
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/67.edn_genbits.2376024265
Short name T611
Test name
Test status
Simulation time 84206527 ps
CPU time 1.81 seconds
Started Oct 09 10:21:17 AM UTC 24
Finished Oct 09 10:21:20 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376024265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2376024265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/68.edn_alert.528524385
Short name T615
Test name
Test status
Simulation time 90947939 ps
CPU time 1.99 seconds
Started Oct 09 10:21:19 AM UTC 24
Finished Oct 09 10:21:22 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528524385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 68.edn_alert.528524385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/68.edn_err.604923338
Short name T146
Test name
Test status
Simulation time 30520271 ps
CPU time 1.89 seconds
Started Oct 09 10:21:20 AM UTC 24
Finished Oct 09 10:21:23 AM UTC 24
Peak memory 244640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604923338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 68.edn_err.604923338
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/68.edn_genbits.372634702
Short name T613
Test name
Test status
Simulation time 51098032 ps
CPU time 1.66 seconds
Started Oct 09 10:21:17 AM UTC 24
Finished Oct 09 10:21:21 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372634702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 68.edn_genbits.372634702
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/69.edn_alert.3994723155
Short name T617
Test name
Test status
Simulation time 29410796 ps
CPU time 1.71 seconds
Started Oct 09 10:21:20 AM UTC 24
Finished Oct 09 10:21:23 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994723155 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.3994723155
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/69.edn_err.682839260
Short name T616
Test name
Test status
Simulation time 27062113 ps
CPU time 1.15 seconds
Started Oct 09 10:21:20 AM UTC 24
Finished Oct 09 10:21:22 AM UTC 24
Peak memory 228964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682839260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 69.edn_err.682839260
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/69.edn_genbits.1876570128
Short name T618
Test name
Test status
Simulation time 40140015 ps
CPU time 1.98 seconds
Started Oct 09 10:21:20 AM UTC 24
Finished Oct 09 10:21:23 AM UTC 24
Peak memory 231268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876570128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1876570128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_alert.2922230302
Short name T141
Test name
Test status
Simulation time 39060316 ps
CPU time 1.32 seconds
Started Oct 09 10:18:20 AM UTC 24
Finished Oct 09 10:18:22 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922230302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.2922230302
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_alert_test.2222414456
Short name T365
Test name
Test status
Simulation time 138622491 ps
CPU time 0.99 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:23 AM UTC 24
Peak memory 216908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222414456 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2222414456
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_disable.2826508152
Short name T47
Test name
Test status
Simulation time 14172435 ps
CPU time 1.24 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:23 AM UTC 24
Peak memory 216800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826508152 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2826508152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.3019929450
Short name T78
Test name
Test status
Simulation time 92067067 ps
CPU time 1.33 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:24 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019929450 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.3019929450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_err.1871940273
Short name T8
Test name
Test status
Simulation time 26350284 ps
CPU time 1.59 seconds
Started Oct 09 10:18:20 AM UTC 24
Finished Oct 09 10:18:23 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871940273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.1871940273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_genbits.1941541389
Short name T132
Test name
Test status
Simulation time 75695127 ps
CPU time 1.64 seconds
Started Oct 09 10:18:20 AM UTC 24
Finished Oct 09 10:18:22 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941541389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1941541389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_intr.76770942
Short name T59
Test name
Test status
Simulation time 36970322 ps
CPU time 1.53 seconds
Started Oct 09 10:18:20 AM UTC 24
Finished Oct 09 10:18:22 AM UTC 24
Peak memory 237180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76770942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in
tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_intr.76770942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_regwen.1119388040
Short name T324
Test name
Test status
Simulation time 28935005 ps
CPU time 1.08 seconds
Started Oct 09 10:18:19 AM UTC 24
Finished Oct 09 10:18:21 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119388040 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.1119388040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_smoke.1074615138
Short name T125
Test name
Test status
Simulation time 39263303 ps
CPU time 1.35 seconds
Started Oct 09 10:18:18 AM UTC 24
Finished Oct 09 10:18:21 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074615138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.1074615138
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_stress_all.3712611513
Short name T265
Test name
Test status
Simulation time 238378899 ps
CPU time 5.47 seconds
Started Oct 09 10:18:20 AM UTC 24
Finished Oct 09 10:18:26 AM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712611513 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3712611513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.2651937809
Short name T527
Test name
Test status
Simulation time 9352498387 ps
CPU time 130.94 seconds
Started Oct 09 10:18:20 AM UTC 24
Finished Oct 09 10:20:33 AM UTC 24
Peak memory 234468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2651937809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_
with_rand_reset.2651937809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/70.edn_alert.1797026777
Short name T619
Test name
Test status
Simulation time 72182694 ps
CPU time 1.51 seconds
Started Oct 09 10:21:21 AM UTC 24
Finished Oct 09 10:21:24 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797026777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 70.edn_alert.1797026777
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/70.edn_err.2414731305
Short name T623
Test name
Test status
Simulation time 27682294 ps
CPU time 1.65 seconds
Started Oct 09 10:21:21 AM UTC 24
Finished Oct 09 10:21:24 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414731305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.2414731305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/70.edn_genbits.1115207549
Short name T621
Test name
Test status
Simulation time 52175100 ps
CPU time 1.64 seconds
Started Oct 09 10:21:21 AM UTC 24
Finished Oct 09 10:21:24 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115207549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1115207549
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/71.edn_alert.1168624674
Short name T135
Test name
Test status
Simulation time 85848377 ps
CPU time 1.93 seconds
Started Oct 09 10:21:21 AM UTC 24
Finished Oct 09 10:21:25 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168624674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.1168624674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/71.edn_err.3743157001
Short name T624
Test name
Test status
Simulation time 77458155 ps
CPU time 1.15 seconds
Started Oct 09 10:21:22 AM UTC 24
Finished Oct 09 10:21:25 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743157001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.3743157001
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/71.edn_genbits.590059121
Short name T622
Test name
Test status
Simulation time 46332515 ps
CPU time 1.53 seconds
Started Oct 09 10:21:21 AM UTC 24
Finished Oct 09 10:21:24 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590059121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.edn_genbits.590059121
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/72.edn_alert.2265061597
Short name T628
Test name
Test status
Simulation time 204986978 ps
CPU time 1.75 seconds
Started Oct 09 10:21:23 AM UTC 24
Finished Oct 09 10:21:26 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265061597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.2265061597
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/72.edn_err.449643106
Short name T627
Test name
Test status
Simulation time 46150373 ps
CPU time 1.45 seconds
Started Oct 09 10:21:24 AM UTC 24
Finished Oct 09 10:21:26 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449643106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 72.edn_err.449643106
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/72.edn_genbits.2579439068
Short name T626
Test name
Test status
Simulation time 98028154 ps
CPU time 1.63 seconds
Started Oct 09 10:21:22 AM UTC 24
Finished Oct 09 10:21:25 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579439068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2579439068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/73.edn_alert.671290728
Short name T629
Test name
Test status
Simulation time 74949980 ps
CPU time 1.61 seconds
Started Oct 09 10:21:24 AM UTC 24
Finished Oct 09 10:21:26 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671290728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 73.edn_alert.671290728
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/73.edn_err.2134008683
Short name T631
Test name
Test status
Simulation time 49049973 ps
CPU time 1.61 seconds
Started Oct 09 10:21:25 AM UTC 24
Finished Oct 09 10:21:27 AM UTC 24
Peak memory 238292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134008683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.2134008683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/73.edn_genbits.2455232233
Short name T630
Test name
Test status
Simulation time 89288399 ps
CPU time 2.22 seconds
Started Oct 09 10:21:24 AM UTC 24
Finished Oct 09 10:21:27 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455232233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2455232233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/74.edn_alert.2121488415
Short name T633
Test name
Test status
Simulation time 31564909 ps
CPU time 1.67 seconds
Started Oct 09 10:21:25 AM UTC 24
Finished Oct 09 10:21:28 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121488415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.2121488415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/74.edn_err.3619859038
Short name T634
Test name
Test status
Simulation time 25393444 ps
CPU time 1.78 seconds
Started Oct 09 10:21:25 AM UTC 24
Finished Oct 09 10:21:28 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619859038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.3619859038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/74.edn_genbits.299692336
Short name T632
Test name
Test status
Simulation time 69617948 ps
CPU time 1.59 seconds
Started Oct 09 10:21:25 AM UTC 24
Finished Oct 09 10:21:27 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299692336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 74.edn_genbits.299692336
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/75.edn_alert.944682953
Short name T636
Test name
Test status
Simulation time 50538280 ps
CPU time 1.63 seconds
Started Oct 09 10:21:26 AM UTC 24
Finished Oct 09 10:21:29 AM UTC 24
Peak memory 228964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944682953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 75.edn_alert.944682953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/75.edn_err.3502421364
Short name T635
Test name
Test status
Simulation time 36563365 ps
CPU time 1.18 seconds
Started Oct 09 10:21:26 AM UTC 24
Finished Oct 09 10:21:28 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502421364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.3502421364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/75.edn_genbits.3372520467
Short name T637
Test name
Test status
Simulation time 24906096 ps
CPU time 1.73 seconds
Started Oct 09 10:21:26 AM UTC 24
Finished Oct 09 10:21:29 AM UTC 24
Peak memory 228960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372520467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3372520467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/76.edn_alert.3371794656
Short name T641
Test name
Test status
Simulation time 25313648 ps
CPU time 1.65 seconds
Started Oct 09 10:21:27 AM UTC 24
Finished Oct 09 10:21:30 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371794656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.3371794656
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/76.edn_err.1522814458
Short name T640
Test name
Test status
Simulation time 135483492 ps
CPU time 1.59 seconds
Started Oct 09 10:21:27 AM UTC 24
Finished Oct 09 10:21:30 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522814458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.1522814458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/76.edn_genbits.2050222338
Short name T638
Test name
Test status
Simulation time 92573122 ps
CPU time 1.73 seconds
Started Oct 09 10:21:26 AM UTC 24
Finished Oct 09 10:21:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050222338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2050222338
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/77.edn_alert.3755658684
Short name T639
Test name
Test status
Simulation time 74197932 ps
CPU time 1.57 seconds
Started Oct 09 10:21:28 AM UTC 24
Finished Oct 09 10:21:30 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755658684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.3755658684
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/77.edn_err.3145852817
Short name T643
Test name
Test status
Simulation time 31805606 ps
CPU time 1.36 seconds
Started Oct 09 10:21:29 AM UTC 24
Finished Oct 09 10:21:31 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145852817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.3145852817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/77.edn_genbits.3294958861
Short name T359
Test name
Test status
Simulation time 52346768 ps
CPU time 2.83 seconds
Started Oct 09 10:21:28 AM UTC 24
Finished Oct 09 10:21:31 AM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294958861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3294958861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/78.edn_alert.3473499691
Short name T645
Test name
Test status
Simulation time 36332415 ps
CPU time 1.91 seconds
Started Oct 09 10:21:29 AM UTC 24
Finished Oct 09 10:21:32 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473499691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 78.edn_alert.3473499691
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/78.edn_err.3425007386
Short name T222
Test name
Test status
Simulation time 147372533 ps
CPU time 1.85 seconds
Started Oct 09 10:21:29 AM UTC 24
Finished Oct 09 10:21:32 AM UTC 24
Peak memory 243272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425007386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.3425007386
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/78.edn_genbits.2403985805
Short name T644
Test name
Test status
Simulation time 57692650 ps
CPU time 1.59 seconds
Started Oct 09 10:21:29 AM UTC 24
Finished Oct 09 10:21:31 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403985805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2403985805
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/79.edn_alert.4042298585
Short name T620
Test name
Test status
Simulation time 44128818 ps
CPU time 1.57 seconds
Started Oct 09 10:21:30 AM UTC 24
Finished Oct 09 10:21:33 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042298585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.4042298585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/79.edn_err.3682384528
Short name T646
Test name
Test status
Simulation time 28846366 ps
CPU time 1.73 seconds
Started Oct 09 10:21:30 AM UTC 24
Finished Oct 09 10:21:33 AM UTC 24
Peak memory 228936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682384528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.3682384528
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/79.edn_genbits.1770531649
Short name T648
Test name
Test status
Simulation time 116073671 ps
CPU time 2.98 seconds
Started Oct 09 10:21:30 AM UTC 24
Finished Oct 09 10:21:34 AM UTC 24
Peak memory 232112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770531649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1770531649
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_alert.2967636199
Short name T55
Test name
Test status
Simulation time 93488522 ps
CPU time 1.6 seconds
Started Oct 09 10:18:23 AM UTC 24
Finished Oct 09 10:18:25 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967636199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.2967636199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_alert_test.3837006472
Short name T366
Test name
Test status
Simulation time 14597545 ps
CPU time 1.43 seconds
Started Oct 09 10:18:23 AM UTC 24
Finished Oct 09 10:18:25 AM UTC 24
Peak memory 227632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837006472 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3837006472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_disable.2962280007
Short name T87
Test name
Test status
Simulation time 27091184 ps
CPU time 1.18 seconds
Started Oct 09 10:18:23 AM UTC 24
Finished Oct 09 10:18:25 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962280007 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2962280007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.3775559728
Short name T88
Test name
Test status
Simulation time 76984450 ps
CPU time 1.71 seconds
Started Oct 09 10:18:23 AM UTC 24
Finished Oct 09 10:18:26 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775559728 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.3775559728
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_err.3365753370
Short name T61
Test name
Test status
Simulation time 33887350 ps
CPU time 1.44 seconds
Started Oct 09 10:18:23 AM UTC 24
Finished Oct 09 10:18:25 AM UTC 24
Peak memory 238048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365753370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.3365753370
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_genbits.4078767413
Short name T50
Test name
Test status
Simulation time 58983102 ps
CPU time 1.81 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:24 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078767413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.4078767413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_intr.2616901736
Short name T119
Test name
Test status
Simulation time 27048292 ps
CPU time 1.11 seconds
Started Oct 09 10:18:22 AM UTC 24
Finished Oct 09 10:18:24 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616901736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.2616901736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_regwen.3811615830
Short name T323
Test name
Test status
Simulation time 24573386 ps
CPU time 1.36 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:24 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811615830 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.3811615830
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_smoke.4217329259
Short name T124
Test name
Test status
Simulation time 166006941 ps
CPU time 1.29 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:24 AM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217329259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.4217329259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_stress_all.412569916
Short name T120
Test name
Test status
Simulation time 102851950 ps
CPU time 3.11 seconds
Started Oct 09 10:18:21 AM UTC 24
Finished Oct 09 10:18:26 AM UTC 24
Peak memory 228068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412569916 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.412569916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.1343432421
Short name T236
Test name
Test status
Simulation time 2525384342 ps
CPU time 53.76 seconds
Started Oct 09 10:18:22 AM UTC 24
Finished Oct 09 10:19:17 AM UTC 24
Peak memory 232376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1343432421 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_
with_rand_reset.1343432421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/80.edn_alert.3932559373
Short name T274
Test name
Test status
Simulation time 92787395 ps
CPU time 1.89 seconds
Started Oct 09 10:21:31 AM UTC 24
Finished Oct 09 10:21:34 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932559373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.3932559373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/80.edn_err.1219097152
Short name T649
Test name
Test status
Simulation time 21034480 ps
CPU time 1.7 seconds
Started Oct 09 10:21:31 AM UTC 24
Finished Oct 09 10:21:34 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219097152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.1219097152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/80.edn_genbits.93627878
Short name T345
Test name
Test status
Simulation time 39344423 ps
CPU time 2.19 seconds
Started Oct 09 10:21:30 AM UTC 24
Finished Oct 09 10:21:33 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93627878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 80.edn_genbits.93627878
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/81.edn_alert.31077323
Short name T652
Test name
Test status
Simulation time 27833211 ps
CPU time 1.7 seconds
Started Oct 09 10:21:32 AM UTC 24
Finished Oct 09 10:21:35 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31077323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 81.edn_alert.31077323
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/81.edn_err.922912254
Short name T651
Test name
Test status
Simulation time 54934933 ps
CPU time 1.46 seconds
Started Oct 09 10:21:33 AM UTC 24
Finished Oct 09 10:21:35 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922912254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 81.edn_err.922912254
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/81.edn_genbits.3954593156
Short name T650
Test name
Test status
Simulation time 31622611 ps
CPU time 1.93 seconds
Started Oct 09 10:21:31 AM UTC 24
Finished Oct 09 10:21:34 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954593156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3954593156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/82.edn_alert.557485633
Short name T654
Test name
Test status
Simulation time 23651084 ps
CPU time 1.81 seconds
Started Oct 09 10:21:33 AM UTC 24
Finished Oct 09 10:21:36 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557485633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 82.edn_alert.557485633
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/82.edn_err.2552635161
Short name T167
Test name
Test status
Simulation time 24876588 ps
CPU time 1.62 seconds
Started Oct 09 10:21:33 AM UTC 24
Finished Oct 09 10:21:35 AM UTC 24
Peak memory 246812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552635161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.2552635161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/82.edn_genbits.476710937
Short name T653
Test name
Test status
Simulation time 86212042 ps
CPU time 1.61 seconds
Started Oct 09 10:21:33 AM UTC 24
Finished Oct 09 10:21:35 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476710937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 82.edn_genbits.476710937
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/83.edn_alert.3679465982
Short name T655
Test name
Test status
Simulation time 24982544 ps
CPU time 1.77 seconds
Started Oct 09 10:21:34 AM UTC 24
Finished Oct 09 10:21:37 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679465982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.3679465982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/83.edn_err.4101398713
Short name T168
Test name
Test status
Simulation time 49461957 ps
CPU time 1.41 seconds
Started Oct 09 10:21:34 AM UTC 24
Finished Oct 09 10:21:36 AM UTC 24
Peak memory 231060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101398713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.4101398713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/83.edn_genbits.340910863
Short name T346
Test name
Test status
Simulation time 43435772 ps
CPU time 1.81 seconds
Started Oct 09 10:21:33 AM UTC 24
Finished Oct 09 10:21:36 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340910863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 83.edn_genbits.340910863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/84.edn_alert.1333118676
Short name T202
Test name
Test status
Simulation time 94328677 ps
CPU time 1.67 seconds
Started Oct 09 10:21:35 AM UTC 24
Finished Oct 09 10:21:38 AM UTC 24
Peak memory 228976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333118676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.1333118676
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/84.edn_err.3603020488
Short name T223
Test name
Test status
Simulation time 102794861 ps
CPU time 1.93 seconds
Started Oct 09 10:21:35 AM UTC 24
Finished Oct 09 10:21:38 AM UTC 24
Peak memory 243132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603020488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.3603020488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/84.edn_genbits.2855435826
Short name T656
Test name
Test status
Simulation time 84094340 ps
CPU time 1.81 seconds
Started Oct 09 10:21:34 AM UTC 24
Finished Oct 09 10:21:37 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855435826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2855435826
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/85.edn_alert.941075314
Short name T657
Test name
Test status
Simulation time 41493954 ps
CPU time 1.61 seconds
Started Oct 09 10:21:35 AM UTC 24
Finished Oct 09 10:21:38 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941075314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 85.edn_alert.941075314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/85.edn_err.3186296561
Short name T658
Test name
Test status
Simulation time 20636824 ps
CPU time 1.55 seconds
Started Oct 09 10:21:35 AM UTC 24
Finished Oct 09 10:21:38 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186296561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.3186296561
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/85.edn_genbits.3516361566
Short name T660
Test name
Test status
Simulation time 75738505 ps
CPU time 2.27 seconds
Started Oct 09 10:21:35 AM UTC 24
Finished Oct 09 10:21:39 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516361566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3516361566
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/86.edn_alert.2079778378
Short name T661
Test name
Test status
Simulation time 43745756 ps
CPU time 1.24 seconds
Started Oct 09 10:21:37 AM UTC 24
Finished Oct 09 10:21:39 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079778378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.2079778378
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/86.edn_err.1961536829
Short name T662
Test name
Test status
Simulation time 28322463 ps
CPU time 1.78 seconds
Started Oct 09 10:21:37 AM UTC 24
Finished Oct 09 10:21:40 AM UTC 24
Peak memory 242904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961536829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.1961536829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/86.edn_genbits.1147455434
Short name T667
Test name
Test status
Simulation time 210129884 ps
CPU time 3.34 seconds
Started Oct 09 10:21:36 AM UTC 24
Finished Oct 09 10:21:41 AM UTC 24
Peak memory 230252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147455434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1147455434
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/87.edn_alert.3075732242
Short name T664
Test name
Test status
Simulation time 111337460 ps
CPU time 1.68 seconds
Started Oct 09 10:21:37 AM UTC 24
Finished Oct 09 10:21:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075732242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.3075732242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/87.edn_err.1924996873
Short name T663
Test name
Test status
Simulation time 18174036 ps
CPU time 1.51 seconds
Started Oct 09 10:21:37 AM UTC 24
Finished Oct 09 10:21:40 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924996873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 87.edn_err.1924996873
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/87.edn_genbits.2593430275
Short name T665
Test name
Test status
Simulation time 61947858 ps
CPU time 1.93 seconds
Started Oct 09 10:21:37 AM UTC 24
Finished Oct 09 10:21:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593430275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2593430275
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/88.edn_alert.1464673558
Short name T203
Test name
Test status
Simulation time 41734638 ps
CPU time 1.3 seconds
Started Oct 09 10:21:38 AM UTC 24
Finished Oct 09 10:21:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464673558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.1464673558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/88.edn_err.1911049204
Short name T666
Test name
Test status
Simulation time 29543006 ps
CPU time 1.28 seconds
Started Oct 09 10:21:38 AM UTC 24
Finished Oct 09 10:21:40 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911049204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.1911049204
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/88.edn_genbits.41231816
Short name T668
Test name
Test status
Simulation time 70319136 ps
CPU time 2.17 seconds
Started Oct 09 10:21:38 AM UTC 24
Finished Oct 09 10:21:41 AM UTC 24
Peak memory 230256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41231816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 88.edn_genbits.41231816
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/89.edn_alert.2442115030
Short name T233
Test name
Test status
Simulation time 253109162 ps
CPU time 1.77 seconds
Started Oct 09 10:21:39 AM UTC 24
Finished Oct 09 10:21:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442115030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.2442115030
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/89.edn_err.708090548
Short name T669
Test name
Test status
Simulation time 23590156 ps
CPU time 1.13 seconds
Started Oct 09 10:21:39 AM UTC 24
Finished Oct 09 10:21:42 AM UTC 24
Peak memory 228964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708090548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 89.edn_err.708090548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/89.edn_genbits.3061031050
Short name T336
Test name
Test status
Simulation time 87745077 ps
CPU time 1.99 seconds
Started Oct 09 10:21:39 AM UTC 24
Finished Oct 09 10:21:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061031050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3061031050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_alert.4269300808
Short name T89
Test name
Test status
Simulation time 92660619 ps
CPU time 1.73 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:29 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269300808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.4269300808
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_alert_test.3409760623
Short name T368
Test name
Test status
Simulation time 48199141 ps
CPU time 1.19 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:28 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409760623 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3409760623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_disable.1495461843
Short name T91
Test name
Test status
Simulation time 35946539 ps
CPU time 1.26 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:28 AM UTC 24
Peak memory 227040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495461843 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1495461843
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.2348593571
Short name T98
Test name
Test status
Simulation time 91775764 ps
CPU time 1.61 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:29 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348593571 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.2348593571
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_err.3157929997
Short name T9
Test name
Test status
Simulation time 25491186 ps
CPU time 1.08 seconds
Started Oct 09 10:18:26 AM UTC 24
Finished Oct 09 10:18:28 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157929997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.3157929997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_genbits.4257643019
Short name T48
Test name
Test status
Simulation time 87565144 ps
CPU time 1.76 seconds
Started Oct 09 10:18:24 AM UTC 24
Finished Oct 09 10:18:27 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257643019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4257643019
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_intr.522711658
Short name T30
Test name
Test status
Simulation time 36807337 ps
CPU time 1.02 seconds
Started Oct 09 10:18:24 AM UTC 24
Finished Oct 09 10:18:27 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522711658 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.522711658
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_regwen.4071155574
Short name T325
Test name
Test status
Simulation time 23897908 ps
CPU time 1.27 seconds
Started Oct 09 10:18:24 AM UTC 24
Finished Oct 09 10:18:26 AM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071155574 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.4071155574
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_smoke.418707745
Short name T367
Test name
Test status
Simulation time 69403714 ps
CPU time 1.25 seconds
Started Oct 09 10:18:24 AM UTC 24
Finished Oct 09 10:18:26 AM UTC 24
Peak memory 226920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418707745 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.edn_smoke.418707745
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_stress_all.2349282396
Short name T116
Test name
Test status
Simulation time 489807045 ps
CPU time 3.65 seconds
Started Oct 09 10:18:24 AM UTC 24
Finished Oct 09 10:18:29 AM UTC 24
Peak memory 227996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349282396 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2349282396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.1016581368
Short name T537
Test name
Test status
Simulation time 4786129358 ps
CPU time 130.29 seconds
Started Oct 09 10:18:24 AM UTC 24
Finished Oct 09 10:20:37 AM UTC 24
Peak memory 230388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1016581368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.1016581368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/90.edn_alert.228960495
Short name T672
Test name
Test status
Simulation time 151696954 ps
CPU time 1.74 seconds
Started Oct 09 10:21:39 AM UTC 24
Finished Oct 09 10:21:43 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228960495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 90.edn_alert.228960495
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/90.edn_err.1696583756
Short name T671
Test name
Test status
Simulation time 21759404 ps
CPU time 1.45 seconds
Started Oct 09 10:21:39 AM UTC 24
Finished Oct 09 10:21:42 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696583756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 90.edn_err.1696583756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/90.edn_genbits.1169669876
Short name T670
Test name
Test status
Simulation time 75662788 ps
CPU time 1.14 seconds
Started Oct 09 10:21:39 AM UTC 24
Finished Oct 09 10:21:42 AM UTC 24
Peak memory 226980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169669876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1169669876
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/91.edn_alert.2521127597
Short name T199
Test name
Test status
Simulation time 88250341 ps
CPU time 1.81 seconds
Started Oct 09 10:21:41 AM UTC 24
Finished Oct 09 10:21:44 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521127597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.2521127597
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/91.edn_err.3829456181
Short name T206
Test name
Test status
Simulation time 20386602 ps
CPU time 1.55 seconds
Started Oct 09 10:21:41 AM UTC 24
Finished Oct 09 10:21:43 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829456181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 91.edn_err.3829456181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/91.edn_genbits.703439787
Short name T674
Test name
Test status
Simulation time 77629579 ps
CPU time 1.93 seconds
Started Oct 09 10:21:40 AM UTC 24
Finished Oct 09 10:21:44 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703439787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 91.edn_genbits.703439787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/92.edn_alert.3213980160
Short name T673
Test name
Test status
Simulation time 82913011 ps
CPU time 1.21 seconds
Started Oct 09 10:21:41 AM UTC 24
Finished Oct 09 10:21:43 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213980160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 92.edn_alert.3213980160
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/92.edn_err.987000732
Short name T676
Test name
Test status
Simulation time 23946428 ps
CPU time 1.42 seconds
Started Oct 09 10:21:42 AM UTC 24
Finished Oct 09 10:21:44 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987000732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 92.edn_err.987000732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/92.edn_genbits.1997857453
Short name T675
Test name
Test status
Simulation time 47832756 ps
CPU time 2.14 seconds
Started Oct 09 10:21:41 AM UTC 24
Finished Oct 09 10:21:44 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997857453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1997857453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/93.edn_alert.2954380194
Short name T679
Test name
Test status
Simulation time 48360595 ps
CPU time 1.52 seconds
Started Oct 09 10:21:42 AM UTC 24
Finished Oct 09 10:21:45 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954380194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.2954380194
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/93.edn_err.1924908314
Short name T677
Test name
Test status
Simulation time 19476466 ps
CPU time 1.19 seconds
Started Oct 09 10:21:42 AM UTC 24
Finished Oct 09 10:21:44 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924908314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.1924908314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/93.edn_genbits.1661450078
Short name T678
Test name
Test status
Simulation time 86914751 ps
CPU time 1.34 seconds
Started Oct 09 10:21:42 AM UTC 24
Finished Oct 09 10:21:44 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661450078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1661450078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/94.edn_alert.577832787
Short name T681
Test name
Test status
Simulation time 40987268 ps
CPU time 1.47 seconds
Started Oct 09 10:21:43 AM UTC 24
Finished Oct 09 10:21:46 AM UTC 24
Peak memory 229032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577832787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 94.edn_alert.577832787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/94.edn_err.2833108262
Short name T176
Test name
Test status
Simulation time 85615610 ps
CPU time 1.44 seconds
Started Oct 09 10:21:43 AM UTC 24
Finished Oct 09 10:21:46 AM UTC 24
Peak memory 242852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833108262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.2833108262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/94.edn_genbits.4191915163
Short name T683
Test name
Test status
Simulation time 36210735 ps
CPU time 1.96 seconds
Started Oct 09 10:21:43 AM UTC 24
Finished Oct 09 10:21:46 AM UTC 24
Peak memory 229220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191915163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4191915163
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/95.edn_alert.3619470194
Short name T680
Test name
Test status
Simulation time 71412990 ps
CPU time 1.2 seconds
Started Oct 09 10:21:43 AM UTC 24
Finished Oct 09 10:21:46 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619470194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.3619470194
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/95.edn_err.2455268256
Short name T682
Test name
Test status
Simulation time 33325027 ps
CPU time 1.34 seconds
Started Oct 09 10:21:43 AM UTC 24
Finished Oct 09 10:21:46 AM UTC 24
Peak memory 244764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455268256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.2455268256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/95.edn_genbits.2359460680
Short name T339
Test name
Test status
Simulation time 236628706 ps
CPU time 2.98 seconds
Started Oct 09 10:21:43 AM UTC 24
Finished Oct 09 10:21:47 AM UTC 24
Peak memory 232180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359460680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2359460680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/96.edn_alert.2084988870
Short name T275
Test name
Test status
Simulation time 91830155 ps
CPU time 1.8 seconds
Started Oct 09 10:21:45 AM UTC 24
Finished Oct 09 10:21:48 AM UTC 24
Peak memory 229024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084988870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.2084988870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/96.edn_err.1084848007
Short name T685
Test name
Test status
Simulation time 58606543 ps
CPU time 1.94 seconds
Started Oct 09 10:21:45 AM UTC 24
Finished Oct 09 10:21:48 AM UTC 24
Peak memory 242984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084848007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 96.edn_err.1084848007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/96.edn_genbits.866043591
Short name T686
Test name
Test status
Simulation time 30139895 ps
CPU time 2.2 seconds
Started Oct 09 10:21:45 AM UTC 24
Finished Oct 09 10:21:48 AM UTC 24
Peak memory 230256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866043591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 96.edn_genbits.866043591
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/97.edn_alert.3759690184
Short name T684
Test name
Test status
Simulation time 33413683 ps
CPU time 1.48 seconds
Started Oct 09 10:21:45 AM UTC 24
Finished Oct 09 10:21:47 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759690184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.3759690184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/97.edn_err.2681142368
Short name T687
Test name
Test status
Simulation time 31554884 ps
CPU time 1.36 seconds
Started Oct 09 10:21:46 AM UTC 24
Finished Oct 09 10:21:48 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681142368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 97.edn_err.2681142368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/97.edn_genbits.1785662869
Short name T355
Test name
Test status
Simulation time 437083106 ps
CPU time 2.56 seconds
Started Oct 09 10:21:45 AM UTC 24
Finished Oct 09 10:21:48 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785662869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1785662869
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/98.edn_alert.700628737
Short name T690
Test name
Test status
Simulation time 104140504 ps
CPU time 1.79 seconds
Started Oct 09 10:21:46 AM UTC 24
Finished Oct 09 10:21:49 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700628737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 98.edn_alert.700628737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/98.edn_err.1648956852
Short name T688
Test name
Test status
Simulation time 25788103 ps
CPU time 1.57 seconds
Started Oct 09 10:21:46 AM UTC 24
Finished Oct 09 10:21:49 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648956852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.1648956852
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/98.edn_genbits.807219581
Short name T689
Test name
Test status
Simulation time 32274229 ps
CPU time 1.66 seconds
Started Oct 09 10:21:46 AM UTC 24
Finished Oct 09 10:21:49 AM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807219581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 98.edn_genbits.807219581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/99.edn_alert.1198287907
Short name T693
Test name
Test status
Simulation time 24377295 ps
CPU time 1.67 seconds
Started Oct 09 10:21:47 AM UTC 24
Finished Oct 09 10:21:50 AM UTC 24
Peak memory 228736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198287907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 99.edn_alert.1198287907
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/99.edn_err.1740537608
Short name T691
Test name
Test status
Simulation time 18560430 ps
CPU time 1.44 seconds
Started Oct 09 10:21:47 AM UTC 24
Finished Oct 09 10:21:50 AM UTC 24
Peak memory 228968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740537608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.1740537608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/default/99.edn_genbits.825290678
Short name T694
Test name
Test status
Simulation time 100435244 ps
CPU time 1.7 seconds
Started Oct 09 10:21:47 AM UTC 24
Finished Oct 09 10:21:50 AM UTC 24
Peak memory 228748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825290678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 99.edn_genbits.825290678
Directory /workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/99.edn_genbits/latest
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