Cond split page
dashboard | hierarchy | modlist | groups | tests | asserts
Go back
 LINE       302
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode)
             ------------1------------    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T21,T4
11CoveredT1,T2,T3

 LINE       307
 EXPRESSION (sfifo_rescmd_int_err || sfifo_gencmd_int_err || edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             ----------1---------    ----------2---------    --------3-------    ---------4---------    ---------5--------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT3,T28,T15
00010CoveredT4,T15,T68
00100CoveredT6,T15,T8
01000CoveredT15,T16,T17
10000CoveredT15,T16,T17

 LINE       314
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T28
10CoveredT27,T29,T30

 LINE       314
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT15,T27,T16
10CoveredT1,T2,T3
11CoveredT15,T27,T16

 LINE       314
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T27,T16
10CoveredT15,T16,T17

 LINE       320
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T16,T17

 LINE       322
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T27,T16

 LINE       324
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T28

 LINE       326
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T28

 LINE       328
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT6,T15,T8

 LINE       331
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT29,T30,T31
100CoveredT113,T114

 LINE       335
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT32,T33
100CoveredT34,T112

 LINE       339
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT15,T27,T16
100CoveredT15,T16,T17

 LINE       347
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------
-1--2-StatusTests
01CoveredT15,T16,T17
10CoveredT1,T2,T3
11CoveredT15,T16,T17

 LINE       350
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------
-1--2-StatusTests
01CoveredT15,T27,T16
10CoveredT1,T2,T3
11CoveredT15,T27,T16

 LINE       367
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------
-1--2-StatusTests
01CoveredT29,T30,T31
10CoveredT1,T2,T3
11CoveredT29,T30,T31

 LINE       370
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------
-1--2-StatusTests
01CoveredT32,T33,T34
10CoveredT1,T2,T3
11CoveredT32,T33,T34

 LINE       373
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT15,T27,T16
10CoveredT1,T2,T3
11CoveredT15,T27,T16

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT71,T107,T115
11CoveredT71,T107,T115

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT71,T107,T115

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT9,T40,T116
11CoveredT9,T40,T116

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T116

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT73,T61,T81
11CoveredT73,T61,T81

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT73,T61,T81

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT117,T118,T119
11CoveredT117,T118,T119

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT117,T118,T119

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT9,T120,T121
11CoveredT9,T120,T121

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T120,T121

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT19,T61,T116
11CoveredT19,T61,T116

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T61,T116

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT38,T122,T123
11CoveredT38,T122,T123

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T122,T123

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT10,T19,T7
11CoveredT10,T19,T7

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T19,T7

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT10,T105,T29
11CoveredT10,T105,T29

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T105,T29

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT116,T101,T76
11CoveredT116,T101,T76

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT116,T101,T76

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT5,T60,T75
11CoveredT5,T60,T75

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T60,T75

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT61,T124,T106
11CoveredT61,T124,T106

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT61,T124,T106

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT125,T126,T127
11CoveredT125,T126,T127

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT125,T126,T127

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT26,T75,T128
11CoveredT26,T75,T128

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T75,T128

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT9,T5,T43
10CoveredT20,T5,T129
11CoveredT20,T5,T129

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T5,T129

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT8,T130,T131
11CoveredT8,T130,T131

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T130,T131

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT5,T60,T61
11CoveredT5,T60,T61

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T60,T61

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT14,T25,T31
11CoveredT14,T25,T31

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T25,T31

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT115,T132,T82
11CoveredT115,T132,T82

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT115,T132,T82

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT8,T54,T133
11CoveredT8,T54,T133

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T54,T133

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT43,T134,T76
11CoveredT43,T134,T76

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T134,T76

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT7,T91,T81
11CoveredT7,T91,T81

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T91,T81

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10CoveredT61,T91,T59
11CoveredT61,T91,T59

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT61,T91,T59

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT20,T9,T5
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       382
 EXPRESSION (edn_enable_fo[CsrngAckErr] && csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))
             -------------1------------    ------------2------------    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT22,T135,T42
101Not Covered
110CoveredT1,T2,T3
111CoveredT22,T14,T26

 LINE       382
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T14,T26

 LINE       388
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------    ------6------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT22,T14,T26
000010CoveredT22,T136,T137
000100CoveredT14,T84,T138
001000CoveredT26,T42,T121
010000CoveredT135,T58,T139
100000CoveredT22,T14,T26

 LINE       407
 EXPRESSION (event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err)
             ---------1---------    ----------2---------    ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT3,T4,T28

 LINE       410
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT66,T69,T72
10CoveredT1,T2,T3
11CoveredT23,T66,T69

 LINE       414
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT23,T66,T69
10CoveredT1,T2,T3
11CoveredT23,T66,T69

 LINE       490
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T38,T111
11CoveredT1,T2,T3

 LINE       502
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       503
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT9,T10,T6
10CoveredT1,T2,T3
11CoveredT9,T10,T14

 LINE       504
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT9,T10,T18
10CoveredT1,T2,T3
11CoveredT9,T10,T18

 LINE       507
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       507
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T21,T4

 LINE       507
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T21,T4

 LINE       507
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T26,T40

 LINE       507
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT20,T26,T40
0010CoveredT20,T21,T4
0100CoveredT20,T21,T4
1000CoveredT1,T2,T3

 LINE       523
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       527
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       527
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T18

 LINE       527
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T10,T18
10CoveredT9,T10,T18

 LINE       527
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT9,T10,T18
1CoveredT9,T10,T18

 LINE       527
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T6

 LINE       527
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T10,T6
10CoveredT9,T10,T14

 LINE       527
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT9,T10,T14
1CoveredT9,T10,T6

 LINE       527
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       527
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       543
 EXPRESSION (((!edn_enable_fo[CsrngCmdReqValidOut])) ? 1'b0 : ((cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && ((!csrng_cmd_i.csrng_req_ready))))
             -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       543
 SUB-EXPRESSION ((cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && ((!csrng_cmd_i.csrng_req_ready)))
                 -----------------------1-----------------------    ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       543
 SUB-EXPRESSION (cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q)
                 ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT80,T140,T141

 LINE       550
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T14

 LINE       550
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T18

 LINE       550
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T10,T18
10CoveredT9,T10,T18

 LINE       550
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T6

 LINE       550
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T10,T6
10CoveredT9,T10,T18

 LINE       550
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       558
 EXPRESSION ((cs_cmd_req_vld_out_q && ((!reject_csrng_entropy))) || cs_cmd_req_vld_hold_q)
             -------------------------1-------------------------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T42,T142
10CoveredT1,T2,T3

 LINE       558
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && ((!reject_csrng_entropy)))
                 ----------1---------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT26,T42,T142
11CoveredT1,T2,T3

 LINE       566
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT22,T26,T135
111CoveredT1,T2,T3

 LINE       570
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T20,T21

 LINE       570
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       570
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T20,T21

 LINE       582
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       582
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%