| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.53 | 98.23 | 93.85 | 97.02 | 90.70 | 96.33 | 99.77 | 92.80 |
| T1008 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3992419772 | Oct 12 02:41:12 PM UTC 24 | Oct 12 02:41:15 PM UTC 24 | 29855258 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1826077060 | Oct 12 02:41:14 PM UTC 24 | Oct 12 02:41:16 PM UTC 24 | 75549459 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.985125879 | Oct 12 02:41:14 PM UTC 24 | Oct 12 02:41:16 PM UTC 24 | 12983969 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.947462547 | Oct 12 02:41:14 PM UTC 24 | Oct 12 02:41:16 PM UTC 24 | 25299419 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1494567188 | Oct 12 02:41:14 PM UTC 24 | Oct 12 02:41:16 PM UTC 24 | 223105225 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.2036224729 | Oct 12 02:41:12 PM UTC 24 | Oct 12 02:41:16 PM UTC 24 | 72302349 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.3884601204 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:17 PM UTC 24 | 61293182 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1371074537 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:17 PM UTC 24 | 20032793 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2490588848 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:17 PM UTC 24 | 53989190 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.3997612463 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:17 PM UTC 24 | 39843582 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.4121860095 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:17 PM UTC 24 | 82398481 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3462836216 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:18 PM UTC 24 | 53944271 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.2673605372 | Oct 12 02:41:16 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 18079532 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1731101627 | Oct 12 02:41:16 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 59479210 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.2038186547 | Oct 12 02:41:17 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 44334252 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.4088218739 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 316983510 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3440783497 | Oct 12 02:41:17 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 20399318 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2676650199 | Oct 12 02:41:17 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 301838015 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2324894251 | Oct 12 02:41:16 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 33106636 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3301139992 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:19 PM UTC 24 | 270260934 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.1848885349 | Oct 12 02:41:16 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 27056768 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.511027770 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 19476763 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1279044956 | Oct 12 02:41:15 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 193252489 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2521694540 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 19986902 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1195413014 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 86129694 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1679308521 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 68733044 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1704397794 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:20 PM UTC 24 | 35819687 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.2191704903 | Oct 12 02:41:16 PM UTC 24 | Oct 12 02:41:21 PM UTC 24 | 100444746 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1890815239 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:21 PM UTC 24 | 84160972 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2342416288 | Oct 12 02:41:18 PM UTC 24 | Oct 12 02:41:22 PM UTC 24 | 151122690 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.2887893683 | Oct 12 02:41:20 PM UTC 24 | Oct 12 02:41:22 PM UTC 24 | 20787440 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.4220479793 | Oct 12 02:41:20 PM UTC 24 | Oct 12 02:41:22 PM UTC 24 | 13529178 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2139637690 | Oct 12 02:41:20 PM UTC 24 | Oct 12 02:41:23 PM UTC 24 | 15734606 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.107689975 | Oct 12 02:41:20 PM UTC 24 | Oct 12 02:41:23 PM UTC 24 | 76457391 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2210079066 | Oct 12 02:41:19 PM UTC 24 | Oct 12 02:41:23 PM UTC 24 | 111173260 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1751072465 | Oct 12 02:41:20 PM UTC 24 | Oct 12 02:41:24 PM UTC 24 | 498643412 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.3703869610 | Oct 12 02:41:22 PM UTC 24 | Oct 12 02:41:24 PM UTC 24 | 67216806 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.2441744805 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 16743910 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.958751312 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 169001403 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2212409076 | Oct 12 02:41:22 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 44584470 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.2426642370 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 10804764 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.4061802664 | Oct 12 02:41:22 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 95750348 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.1242817014 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 17737377 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3385854380 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 18962507 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2778228812 | Oct 12 02:41:22 PM UTC 24 | Oct 12 02:41:25 PM UTC 24 | 119195211 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.764669131 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:26 PM UTC 24 | 44030964 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.3660921102 | Oct 12 02:41:22 PM UTC 24 | Oct 12 02:41:26 PM UTC 24 | 79599042 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.452219331 | Oct 12 02:41:20 PM UTC 24 | Oct 12 02:41:26 PM UTC 24 | 1753663918 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.486100885 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:26 PM UTC 24 | 92190681 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.4244438185 | Oct 12 02:41:22 PM UTC 24 | Oct 12 02:41:26 PM UTC 24 | 121372533 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2756043174 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:28 PM UTC 24 | 70068785 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2624724182 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:28 PM UTC 24 | 39241557 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.3842272214 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:28 PM UTC 24 | 23710374 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.4167307185 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:28 PM UTC 24 | 163138504 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4197922761 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:28 PM UTC 24 | 20175813 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1082122534 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:29 PM UTC 24 | 280902049 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.2550988126 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:29 PM UTC 24 | 214712466 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.2195738921 | Oct 12 02:41:25 PM UTC 24 | Oct 12 02:41:29 PM UTC 24 | 79431022 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.339551950 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 10806844 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.4177429902 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 20966442 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.836209942 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 16677670 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2972383746 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 24615396 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1534853976 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 30705899 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3436735179 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 44157536 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.1897044560 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 127302967 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.168939449 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 28619099 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1334202757 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 16197503 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2522063521 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 45623365 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2976581950 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 22198674 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.1728658524 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:30 PM UTC 24 | 59388556 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3585843131 | Oct 12 02:41:28 PM UTC 24 | Oct 12 02:41:31 PM UTC 24 | 56782831 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.91003392 | Oct 12 02:41:30 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 33723651 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3807722900 | Oct 12 02:41:30 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 27680156 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.2631416563 | Oct 12 02:41:31 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 40363876 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1724901200 | Oct 12 02:41:30 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 55146303 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.1152146138 | Oct 12 02:41:31 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 24335110 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.2828348112 | Oct 12 02:41:30 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 29670031 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3186022365 | Oct 12 02:41:31 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 13414205 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.2451295103 | Oct 12 02:41:31 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 12907959 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1301397263 | Oct 12 02:41:30 PM UTC 24 | Oct 12 02:41:33 PM UTC 24 | 13356051 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.1742576367 | Oct 12 02:41:32 PM UTC 24 | Oct 12 02:41:34 PM UTC 24 | 23092262 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.3700255037 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:35 PM UTC 24 | 90345498 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3682660930 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:35 PM UTC 24 | 17859444 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3777019726 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:35 PM UTC 24 | 32044403 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.1448626725 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:35 PM UTC 24 | 20021415 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.6381848 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:35 PM UTC 24 | 41057460 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3036666459 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:35 PM UTC 24 | 51162543 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.214838287 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:36 PM UTC 24 | 19479000 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1821567602 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:36 PM UTC 24 | 83167515 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1075989362 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:36 PM UTC 24 | 38270063 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1501111398 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:36 PM UTC 24 | 44758497 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.1610285479 | Oct 12 02:41:33 PM UTC 24 | Oct 12 02:41:36 PM UTC 24 | 30702246 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.1287075926 | Oct 12 02:41:34 PM UTC 24 | Oct 12 02:41:36 PM UTC 24 | 28312135 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1741864734 | Oct 12 02:41:34 PM UTC 24 | Oct 12 02:41:37 PM UTC 24 | 36573910 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3094840569 | Oct 12 02:41:23 PM UTC 24 | Oct 12 02:41:37 PM UTC 24 | 892112589 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_alert.2188018016 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 111482943 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:14:35 PM UTC 24 |
| Finished | Oct 12 02:14:38 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188018016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_alert.2188018016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_genbits.2216565883 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 80797578 ps |
| CPU time | 3 seconds |
| Started | Oct 12 02:14:42 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216565883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2216565883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_sec_cm.484197261 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3166044535 ps |
| CPU time | 6.37 seconds |
| Started | Oct 12 02:14:36 PM UTC 24 |
| Finished | Oct 12 02:14:44 PM UTC 24 |
| Peak memory | 263988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484197261 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.484197261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_stress_all.2432193116 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 319792393 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 02:14:34 PM UTC 24 |
| Finished | Oct 12 02:14:38 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432193116 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2432193116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_genbits.1530232338 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 31661963 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530232338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1530232338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2234600991 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 162348358 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:14:53 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234600991 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2234600991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.1677968506 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 604327262 ps |
| CPU time | 15.03 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:15:08 PM UTC 24 |
| Peak memory | 231128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677968506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_ with_rand_reset.1677968506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_alert.4225592753 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 49460539 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:14:57 PM UTC 24 |
| Finished | Oct 12 02:14:59 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225592753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.edn_alert.4225592753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_sec_cm.3248869169 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 518733761 ps |
| CPU time | 5.62 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:54 PM UTC 24 |
| Peak memory | 261576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248869169 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3248869169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_alert.2203306824 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 97054232 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 02:14:40 PM UTC 24 |
| Finished | Oct 12 02:14:43 PM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203306824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_alert.2203306824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_regwen.978557446 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 27567925 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:14:39 PM UTC 24 |
| Finished | Oct 12 02:14:41 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978557446 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_regwen.978557446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.972694646 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 124497350 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:47 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972694646 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.972694646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_alert.2950152199 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 196473951 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:18 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950152199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_alert.2950152199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_stress_all.614898008 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 827571091 ps |
| CPU time | 5.09 seconds |
| Started | Oct 12 02:15:02 PM UTC 24 |
| Finished | Oct 12 02:15:09 PM UTC 24 |
| Peak memory | 233172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614898008 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.614898008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_disable.1205593405 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 15017963 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:14:40 PM UTC 24 |
| Finished | Oct 12 02:14:43 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205593405 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1205593405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.3145236483 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 245577655 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:53 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145236483 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.3145236483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.1615803078 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 374477891 ps |
| CPU time | 2.69 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615803078 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1615803078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.1797998459 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 20766370 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:04 PM UTC 24 |
| Peak memory | 216640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797998459 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1797998459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_alert.1374347957 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 23089153 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374347957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.edn_alert.1374347957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_disable.887071595 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 35840781 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:15:28 PM UTC 24 |
| Finished | Oct 12 02:15:30 PM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887071595 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.887071595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.1386969931 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 42587723 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:21 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386969931 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.1386969931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_disable.399075273 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 34620174 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399075273 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.399075273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_disable.2423559121 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 13339290 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:16:10 PM UTC 24 |
| Finished | Oct 12 02:16:13 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423559121 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2423559121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_alert_test.2666029238 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 17109470 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 228616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666029238 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2666029238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_stress_all.3129964075 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 188296017 ps |
| CPU time | 4.72 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:14:58 PM UTC 24 |
| Peak memory | 228980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129964075 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3129964075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_intr.2629560842 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 23717165 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:14:54 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629560842 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2629560842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_alert.1571443540 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 27741362 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:15:09 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571443540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_alert.1571443540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_intr.533089308 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 20235336 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:15:36 PM UTC 24 |
| Finished | Oct 12 02:15:39 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533089308 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.533089308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_err.3790738741 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 19463136 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:09 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790738741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 14.edn_err.3790738741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.2993858633 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 44144838 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993858633 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.2993858633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_alert.140471584 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 74393067 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:30 PM UTC 24 |
| Finished | Oct 12 02:16:40 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140471584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 46.edn_alert.140471584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_err.2961078254 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 21487688 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 238444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961078254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 29.edn_err.2961078254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_alert.314603062 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 153682120 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 02:15:58 PM UTC 24 |
| Finished | Oct 12 02:16:01 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314603062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 37.edn_alert.314603062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/114.edn_genbits.1329381575 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 44328682 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329381575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1329381575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/114.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/105.edn_alert.2570487256 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 26833715 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570487256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 105.edn_alert.2570487256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/105.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_alert.910259135 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 22044150 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 02:15:52 PM UTC 24 |
| Finished | Oct 12 02:15:55 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910259135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 35.edn_alert.910259135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.2578316595 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 68269716 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:14:35 PM UTC 24 |
| Finished | Oct 12 02:14:38 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578316595 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.2578316595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_err.4196858118 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 33058311 ps |
| CPU time | 1 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:03 PM UTC 24 |
| Peak memory | 246008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196858118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 10.edn_err.4196858118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/101.edn_alert.330097984 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 29223239 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330097984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 101.edn_alert.330097984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/101.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_alert.1762590540 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 104271693 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:15:08 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762590540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_alert.1762590540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/122.edn_alert.3901526154 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 86563419 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901526154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 122.edn_alert.3901526154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/122.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_alert.2307861770 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 83063747 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307861770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_alert.2307861770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/170.edn_alert.1522971558 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 49134172 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522971558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 170.edn_alert.1522971558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/170.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/172.edn_alert.2108738676 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 228961837 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108738676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 172.edn_alert.2108738676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/172.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_disable.1596745304 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 29417313 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596745304 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1596745304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_err.463505827 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 31129408 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:15:33 PM UTC 24 |
| Finished | Oct 12 02:15:35 PM UTC 24 |
| Peak memory | 238244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463505827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 26.edn_err.463505827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_disable.3651254414 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 10592462 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:15:53 PM UTC 24 |
| Finished | Oct 12 02:15:55 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651254414 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3651254414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_genbits.3395860325 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 48234602 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:47 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395860325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3395860325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_genbits.1983469284 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 130754796 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:16:30 PM UTC 24 |
| Finished | Oct 12 02:16:40 PM UTC 24 |
| Peak memory | 232188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983469284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1983469284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_alert.4265126100 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 54198539 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:04 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265126100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_alert.4265126100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_genbits.3856639781 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 41579202 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:18 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856639781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3856639781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.2854873495 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3663312545 ps |
| CPU time | 52.42 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 231584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854873495 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all _with_rand_reset.2854873495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_genbits.896369912 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 121657502 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 02:15:57 PM UTC 24 |
| Finished | Oct 12 02:16:00 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896369912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.edn_genbits.896369912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_genbits.2883585319 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 41596765 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:14:54 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883585319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2883585319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/100.edn_alert.1189337018 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 85073202 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189337018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 100.edn_alert.1189337018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/100.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_stress_all.184926163 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 968484316 ps |
| CPU time | 5.3 seconds |
| Started | Oct 12 02:14:57 PM UTC 24 |
| Finished | Oct 12 02:15:03 PM UTC 24 |
| Peak memory | 231028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184926163 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.184926163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_genbits.3626505955 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 39926049 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626505955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3626505955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_intr.3490752353 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 29802670 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:15:39 PM UTC 24 |
| Finished | Oct 12 02:15:41 PM UTC 24 |
| Peak memory | 230036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490752353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3490752353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.1705798002 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 128747787 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:40:58 PM UTC 24 |
| Finished | Oct 12 02:41:01 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705798002 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1705798002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.922327871 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 51725487 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 02:41:00 PM UTC 24 |
| Finished | Oct 12 02:41:03 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922327871 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.922327871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/118.edn_genbits.3259267128 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 90957431 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259267128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3259267128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/118.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/122.edn_genbits.1044543958 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 65616398 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:17:26 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044543958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1044543958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/122.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/124.edn_genbits.4097127483 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 326939940 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097127483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4097127483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/124.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/130.edn_genbits.3877253914 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 41558982 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:17:30 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877253914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3877253914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/130.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_stress_all.3560241983 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 529736335 ps |
| CPU time | 3.12 seconds |
| Started | Oct 12 02:15:09 PM UTC 24 |
| Finished | Oct 12 02:15:13 PM UTC 24 |
| Peak memory | 229060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560241983 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3560241983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/176.edn_genbits.3419533291 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 278823310 ps |
| CPU time | 3.78 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419533291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3419533291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/176.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/199.edn_genbits.3437996847 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 43077892 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437996847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3437996847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/199.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/257.edn_genbits.1748333374 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 41844706 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:18:09 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748333374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1748333374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/257.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_intr.1106831057 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 21975403 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:15:30 PM UTC 24 |
| Finished | Oct 12 02:15:32 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106831057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1106831057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_intr.2551914446 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 32343855 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:03 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551914446 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2551914446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_err.2450158059 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26074273 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:14:40 PM UTC 24 |
| Finished | Oct 12 02:14:43 PM UTC 24 |
| Peak memory | 248160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450158059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.edn_err.2450158059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/113.edn_genbits.1013106832 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 33983791 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013106832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1013106832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/113.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.3305809043 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 514098355 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 02:40:58 PM UTC 24 |
| Finished | Oct 12 02:41:03 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305809043 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3305809043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.2879705013 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 18135757 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:40:57 PM UTC 24 |
| Finished | Oct 12 02:40:59 PM UTC 24 |
| Peak memory | 217368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879705013 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2879705013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.229174692 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 112251484 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:41:00 PM UTC 24 |
| Finished | Oct 12 02:41:02 PM UTC 24 |
| Peak memory | 227072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =229174692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.229174692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1520063333 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 12815823 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:40:58 PM UTC 24 |
| Finished | Oct 12 02:41:00 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520063333 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1520063333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.3413467386 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 26432870 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:40:57 PM UTC 24 |
| Finished | Oct 12 02:41:00 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413467386 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3413467386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.709378830 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 76251567 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:40:59 PM UTC 24 |
| Finished | Oct 12 02:41:01 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709378830 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.709378830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.287900591 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 964002430 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 02:40:57 PM UTC 24 |
| Finished | Oct 12 02:41:03 PM UTC 24 |
| Peak memory | 228092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287900591 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.287900591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.3416685862 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 211694796 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:40:57 PM UTC 24 |
| Finished | Oct 12 02:41:00 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416685862 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3416685862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.3433854933 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 112556709 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:04 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433854933 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3433854933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.187848392 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 215391032 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:06 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187848392 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.187848392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.33725861 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 15665974 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:41:00 PM UTC 24 |
| Finished | Oct 12 02:41:02 PM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33725861 -assert nopostproc +UVM_TESTNAME=edn_ base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.33725861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3089318902 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 71602746 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:04 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3089318902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3089318902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.1834162164 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 14188590 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:04 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834162164 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1834162164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.693584844 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 25831288 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:41:00 PM UTC 24 |
| Finished | Oct 12 02:41:02 PM UTC 24 |
| Peak memory | 216660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693584844 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.693584844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.3157571225 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 26132780 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:05 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157571225 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.3157571225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.2271976451 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 364233223 ps |
| CPU time | 5.29 seconds |
| Started | Oct 12 02:41:00 PM UTC 24 |
| Finished | Oct 12 02:41:06 PM UTC 24 |
| Peak memory | 228112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271976451 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2271976451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2490588848 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 53989190 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:17 PM UTC 24 |
| Peak memory | 229124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2490588848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2490588848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1371074537 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 20032793 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:17 PM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371074537 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1371074537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.3884601204 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 61293182 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:17 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884601204 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3884601204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3462836216 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 53944271 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:18 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462836216 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.3462836216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1279044956 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 193252489 ps |
| CPU time | 4.02 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279044956 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1279044956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.4121860095 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 82398481 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:17 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121860095 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4121860095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2324894251 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 33106636 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:41:16 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2324894251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2324894251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.2673605372 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 18079532 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:41:16 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673605372 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2673605372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.3997612463 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 39843582 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:17 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997612463 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3997612463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1731101627 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 59479210 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:41:16 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 216716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731101627 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.1731101627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3301139992 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 270260934 ps |
| CPU time | 3.12 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 228100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301139992 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3301139992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.4088218739 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 316983510 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 02:41:15 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 217752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088218739 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4088218739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1704397794 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 35819687 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 227076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1704397794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1704397794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.2038186547 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 44334252 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:41:17 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038186547 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2038186547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3440783497 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 20399318 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:41:17 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440783497 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3440783497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2676650199 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 301838015 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:41:17 PM UTC 24 |
| Finished | Oct 12 02:41:19 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676650199 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.2676650199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.1848885349 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 27056768 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 02:41:16 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848885349 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1848885349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.2191704903 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 100444746 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 02:41:16 PM UTC 24 |
| Finished | Oct 12 02:41:21 PM UTC 24 |
| Peak memory | 217752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191704903 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2191704903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1195413014 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 86129694 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1195413014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1195413014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.511027770 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 19476763 ps |
| CPU time | 1 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511027770 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.511027770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2521694540 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 19986902 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521694540 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2521694540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1679308521 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 68733044 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:20 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679308521 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.1679308521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2342416288 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 151122690 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:22 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342416288 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2342416288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1890815239 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 84160972 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 02:41:18 PM UTC 24 |
| Finished | Oct 12 02:41:21 PM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890815239 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1890815239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.107689975 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 76457391 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:41:20 PM UTC 24 |
| Finished | Oct 12 02:41:23 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =107689975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.107689975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.4220479793 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 13529178 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:41:20 PM UTC 24 |
| Finished | Oct 12 02:41:22 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220479793 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4220479793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2139637690 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 15734606 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:41:20 PM UTC 24 |
| Finished | Oct 12 02:41:23 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139637690 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2139637690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.2887893683 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 20787440 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 02:41:20 PM UTC 24 |
| Finished | Oct 12 02:41:22 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887893683 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.2887893683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2210079066 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 111173260 ps |
| CPU time | 3.01 seconds |
| Started | Oct 12 02:41:19 PM UTC 24 |
| Finished | Oct 12 02:41:23 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210079066 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2210079066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1751072465 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 498643412 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 02:41:20 PM UTC 24 |
| Finished | Oct 12 02:41:24 PM UTC 24 |
| Peak memory | 217752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751072465 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1751072465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2212409076 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 44584470 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2212409076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2212409076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.699436 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 36411448 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:24 PM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699436 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.699436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.3703869610 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 67216806 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:24 PM UTC 24 |
| Peak memory | 216576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703869610 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3703869610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2778228812 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 119195211 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778228812 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.2778228812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.452219331 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 1753663918 ps |
| CPU time | 4.22 seconds |
| Started | Oct 12 02:41:20 PM UTC 24 |
| Finished | Oct 12 02:41:26 PM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452219331 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.452219331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.4061802664 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 95750348 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 226460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061802664 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4061802664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.764669131 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 44030964 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:26 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =764669131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.764669131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.958751312 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 169001403 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958751312 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.958751312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.2441744805 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 16743910 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441744805 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2441744805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3385854380 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 18962507 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385854380 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.3385854380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.4244438185 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 121372533 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:26 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244438185 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4244438185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.3660921102 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 79599042 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 02:41:22 PM UTC 24 |
| Finished | Oct 12 02:41:26 PM UTC 24 |
| Peak memory | 218008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660921102 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3660921102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2756043174 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 70068785 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:28 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2756043174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2756043174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.1242817014 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 17737377 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 214936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242817014 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1242817014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.2426642370 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 10804764 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:25 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426642370 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2426642370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2624724182 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 39241557 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:28 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624724182 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.2624724182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.486100885 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 92190681 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:26 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486100885 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.486100885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3094840569 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 892112589 ps |
| CPU time | 13.03 seconds |
| Started | Oct 12 02:41:23 PM UTC 24 |
| Finished | Oct 12 02:41:37 PM UTC 24 |
| Peak memory | 217168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094840569 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3094840569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4197922761 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 20175813 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:28 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4197922761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4197922761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.4167307185 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 163138504 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:28 PM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167307185 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.4167307185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.3842272214 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 23710374 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:28 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842272214 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3842272214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1082122534 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 280902049 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:29 PM UTC 24 |
| Peak memory | 216716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082122534 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1082122534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.2195738921 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 79431022 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:29 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195738921 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2195738921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.2550988126 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 214712466 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 02:41:25 PM UTC 24 |
| Finished | Oct 12 02:41:29 PM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550988126 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2550988126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2972383746 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 24615396 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2972383746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2972383746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1534853976 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 30705899 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534853976 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1534853976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.339551950 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 10806844 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339551950 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.339551950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.1728658524 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 59388556 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728658524 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.1728658524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.1897044560 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 127302967 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 231024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897044560 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1897044560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3585843131 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 56782831 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:31 PM UTC 24 |
| Peak memory | 227008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585843131 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3585843131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.3946100044 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 84799729 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:41:03 PM UTC 24 |
| Finished | Oct 12 02:41:06 PM UTC 24 |
| Peak memory | 216724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946100044 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3946100044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.3769137569 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 264542856 ps |
| CPU time | 4.92 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:08 PM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769137569 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3769137569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2238851142 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 17173408 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:04 PM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238851142 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2238851142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1661016225 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 47713209 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 02:41:03 PM UTC 24 |
| Finished | Oct 12 02:41:06 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1661016225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1661016225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.1205510989 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 22711443 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:04 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205510989 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1205510989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.2590425155 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 50703634 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:41:03 PM UTC 24 |
| Finished | Oct 12 02:41:06 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590425155 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.2590425155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.980830278 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 106560240 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:05 PM UTC 24 |
| Peak memory | 226944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980830278 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.980830278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.1429280070 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 391903048 ps |
| CPU time | 2.35 seconds |
| Started | Oct 12 02:41:02 PM UTC 24 |
| Finished | Oct 12 02:41:05 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429280070 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1429280070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.1334202757 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 16197503 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334202757 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1334202757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3436735179 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 44157536 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436735179 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3436735179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.836209942 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 16677670 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836209942 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.836209942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.168939449 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 28619099 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168939449 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.168939449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2976581950 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 22198674 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976581950 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2976581950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2522063521 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 45623365 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522063521 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2522063521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.4177429902 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 20966442 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 02:41:28 PM UTC 24 |
| Finished | Oct 12 02:41:30 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177429902 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4177429902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3807722900 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 27680156 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:41:30 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807722900 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3807722900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.91003392 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 33723651 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 02:41:30 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91003392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.91003392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1724901200 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 55146303 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 02:41:30 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724901200 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1724901200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.1807219869 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 44629185 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:08 PM UTC 24 |
| Peak memory | 216640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807219869 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1807219869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.3058561568 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 36894147 ps |
| CPU time | 2.73 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:10 PM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058561568 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3058561568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.20763077 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 14195441 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:41:05 PM UTC 24 |
| Finished | Oct 12 02:41:06 PM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20763077 -assert nopostproc +UVM_TESTNAME=edn_ base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.20763077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.774513898 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 60668735 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:09 PM UTC 24 |
| Peak memory | 228092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =774513898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.774513898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.3832475920 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 100514930 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:41:05 PM UTC 24 |
| Finished | Oct 12 02:41:07 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832475920 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3832475920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.3154470316 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 15634396 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:41:05 PM UTC 24 |
| Finished | Oct 12 02:41:07 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154470316 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3154470316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1902494069 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 41415160 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:09 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902494069 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1902494069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.766969350 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 46055778 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 02:41:03 PM UTC 24 |
| Finished | Oct 12 02:41:07 PM UTC 24 |
| Peak memory | 228060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766969350 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.766969350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.1931170732 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 670937338 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 02:41:04 PM UTC 24 |
| Finished | Oct 12 02:41:08 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931170732 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1931170732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1301397263 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 13356051 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:41:30 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301397263 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1301397263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.2828348112 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 29670031 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:41:30 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828348112 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2828348112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.2631416563 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 40363876 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 02:41:31 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631416563 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2631416563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.1152146138 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 24335110 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:41:31 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152146138 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1152146138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.2451295103 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 12907959 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:41:31 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451295103 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2451295103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3186022365 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 13414205 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 02:41:31 PM UTC 24 |
| Finished | Oct 12 02:41:33 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186022365 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3186022365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.1742576367 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 23092262 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 02:41:32 PM UTC 24 |
| Finished | Oct 12 02:41:34 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742576367 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1742576367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.1448626725 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 20021415 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:35 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448626725 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1448626725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3777019726 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 32044403 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:35 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777019726 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3777019726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.1610285479 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 30702246 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:36 PM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610285479 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1610285479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.3673226900 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 129935110 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:10 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673226900 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3673226900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.2490672411 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 922979984 ps |
| CPU time | 6.4 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:15 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490672411 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2490672411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.3129190622 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 14744225 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:10 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129190622 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3129190622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2471001484 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 105435505 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:10 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2471001484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2471001484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.4250455785 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 28054375 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:09 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250455785 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4250455785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.2865603720 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 11976833 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:08 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865603720 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2865603720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.1807098604 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 100419748 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:10 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807098604 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.1807098604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.47430966 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 25153929 ps |
| CPU time | 2.26 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:09 PM UTC 24 |
| Peak memory | 228312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47430966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.47430966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.1992442084 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 215000415 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 02:41:06 PM UTC 24 |
| Finished | Oct 12 02:41:09 PM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992442084 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1992442084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1501111398 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 44758497 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:36 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501111398 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1501111398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1075989362 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 38270063 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:36 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075989362 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1075989362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1821567602 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 83167515 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:36 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821567602 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1821567602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.6381848 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 41057460 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:35 PM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6381848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.6381848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3036666459 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 51162543 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:35 PM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036666459 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3036666459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.3700255037 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 90345498 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:35 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700255037 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3700255037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3682660930 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 17859444 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:35 PM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682660930 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3682660930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.214838287 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 19479000 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 02:41:33 PM UTC 24 |
| Finished | Oct 12 02:41:36 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214838287 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.214838287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.1287075926 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 28312135 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 02:41:34 PM UTC 24 |
| Finished | Oct 12 02:41:36 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287075926 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1287075926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1741864734 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 36573910 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 02:41:34 PM UTC 24 |
| Finished | Oct 12 02:41:37 PM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741864734 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1741864734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1490823419 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 84633192 ps |
| CPU time | 2.28 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:12 PM UTC 24 |
| Peak memory | 228184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1490823419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1490823419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.106172143 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 37128999 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:11 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106172143 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.106172143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.2662878548 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 80393178 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:11 PM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662878548 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2662878548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.3083876703 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 55418798 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:11 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083876703 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.3083876703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.827218746 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 114536975 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:41:07 PM UTC 24 |
| Finished | Oct 12 02:41:11 PM UTC 24 |
| Peak memory | 227996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827218746 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.827218746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.3196818718 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 78062297 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:41:08 PM UTC 24 |
| Finished | Oct 12 02:41:10 PM UTC 24 |
| Peak memory | 227008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196818718 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3196818718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3001149181 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 26799711 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3001149181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3001149181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.4076875750 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 47979562 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076875750 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4076875750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2058931154 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 38727493 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:11 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058931154 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2058931154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3743609254 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 16299376 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743609254 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.3743609254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.3533908513 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 43620735 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 02:41:09 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533908513 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3533908513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.4267905242 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 200239149 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:14 PM UTC 24 |
| Peak memory | 228068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4267905242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.4267905242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.195381490 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 13911753 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 216112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195381490 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.195381490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3195214285 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 10998219 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195214285 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3195214285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.187034883 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 94383913 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:13 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187034883 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.187034883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.657368199 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 57152854 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:14 PM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657368199 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.657368199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.931132346 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 352710216 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:14 PM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931132346 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.931132346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3992419772 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 29855258 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:41:12 PM UTC 24 |
| Finished | Oct 12 02:41:15 PM UTC 24 |
| Peak memory | 226956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3992419772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3992419772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2721912996 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 13823871 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:41:12 PM UTC 24 |
| Finished | Oct 12 02:41:15 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721912996 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2721912996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.893514085 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 30396309 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:41:12 PM UTC 24 |
| Finished | Oct 12 02:41:14 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893514085 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.893514085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3381639227 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 126472297 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:41:12 PM UTC 24 |
| Finished | Oct 12 02:41:15 PM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381639227 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.3381639227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2557769408 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 121807891 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:15 PM UTC 24 |
| Peak memory | 228120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557769408 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2557769408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.4022802066 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 111660700 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 02:41:11 PM UTC 24 |
| Finished | Oct 12 02:41:14 PM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022802066 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4022802066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3825614170 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 16063852 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:41:14 PM UTC 24 |
| Finished | Oct 12 02:41:16 PM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3825614170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3825614170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.947462547 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 25299419 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:41:14 PM UTC 24 |
| Finished | Oct 12 02:41:16 PM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947462547 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.947462547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.985125879 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 12983969 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:41:14 PM UTC 24 |
| Finished | Oct 12 02:41:16 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985125879 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.985125879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1826077060 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 75549459 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:41:14 PM UTC 24 |
| Finished | Oct 12 02:41:16 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826077060 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.1826077060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.2036224729 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 72302349 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:41:12 PM UTC 24 |
| Finished | Oct 12 02:41:16 PM UTC 24 |
| Peak memory | 228344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036224729 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2036224729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1494567188 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 223105225 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:41:14 PM UTC 24 |
| Finished | Oct 12 02:41:16 PM UTC 24 |
| Peak memory | 227008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494567188 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1494567188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_alert_test.3234780650 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12872165 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:14:36 PM UTC 24 |
| Finished | Oct 12 02:14:39 PM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234780650 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3234780650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_disable.3806135327 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11762941 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:14:35 PM UTC 24 |
| Finished | Oct 12 02:14:37 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806135327 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3806135327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_err.3146942658 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 18571463 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:14:35 PM UTC 24 |
| Finished | Oct 12 02:14:38 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146942658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.edn_err.3146942658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_genbits.810169156 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 47613982 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 02:14:34 PM UTC 24 |
| Finished | Oct 12 02:14:37 PM UTC 24 |
| Peak memory | 231348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810169156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.edn_genbits.810169156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_intr.3266715535 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 34667269 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:14:34 PM UTC 24 |
| Finished | Oct 12 02:14:36 PM UTC 24 |
| Peak memory | 228160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266715535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3266715535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_regwen.1892481714 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 28141152 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:14:32 PM UTC 24 |
| Finished | Oct 12 02:14:34 PM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892481714 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.edn_regwen.1892481714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_smoke.3815427956 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 47000901 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:14:31 PM UTC 24 |
| Finished | Oct 12 02:14:34 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815427956 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_smoke.3815427956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.377996899 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 12138009994 ps |
| CPU time | 85.02 seconds |
| Started | Oct 12 02:14:34 PM UTC 24 |
| Finished | Oct 12 02:16:01 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377996899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_w ith_rand_reset.377996899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_alert_test.2121568997 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 31244434 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:14:42 PM UTC 24 |
| Finished | Oct 12 02:14:44 PM UTC 24 |
| Peak memory | 217720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121568997 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2121568997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.3577890639 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 62819235 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:14:40 PM UTC 24 |
| Finished | Oct 12 02:14:43 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577890639 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3577890639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_genbits.3361134712 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 111555915 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:14:39 PM UTC 24 |
| Finished | Oct 12 02:14:41 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361134712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3361134712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_intr.58591977 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 28155818 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:14:39 PM UTC 24 |
| Finished | Oct 12 02:14:41 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58591977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.edn_intr.58591977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_sec_cm.1796596126 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 475970256 ps |
| CPU time | 7.48 seconds |
| Started | Oct 12 02:14:42 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 261812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796596126 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1796596126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_smoke.1617225277 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15689816 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:14:38 PM UTC 24 |
| Finished | Oct 12 02:14:41 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617225277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_smoke.1617225277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/1.edn_stress_all.2978087900 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 520070082 ps |
| CPU time | 4.17 seconds |
| Started | Oct 12 02:14:39 PM UTC 24 |
| Finished | Oct 12 02:14:44 PM UTC 24 |
| Peak memory | 229304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978087900 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2978087900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_alert_test.2896179695 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 13686893 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:15:02 PM UTC 24 |
| Finished | Oct 12 02:15:04 PM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896179695 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2896179695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_disable.2125675124 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 151567374 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:04 PM UTC 24 |
| Peak memory | 228096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125675124 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2125675124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.38879258 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 362993377 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:03 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38879258 -assert nopostproc +UVM_TESTNAME=edn_disab le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.38879258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_genbits.2766385717 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 86993344 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:04 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766385717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2766385717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_smoke.2001521412 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 28998034 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:15:00 PM UTC 24 |
| Finished | Oct 12 02:15:02 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001521412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_smoke.2001521412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/10.edn_stress_all.669283541 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 380408017 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 02:15:01 PM UTC 24 |
| Finished | Oct 12 02:15:05 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669283541 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.669283541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/10.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/100.edn_genbits.2591083925 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 64440908 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591083925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2591083925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/100.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/101.edn_genbits.3225311930 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 50471071 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225311930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3225311930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/101.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/102.edn_alert.2121067132 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 64016509 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121067132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 102.edn_alert.2121067132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/102.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/102.edn_genbits.3651557095 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 86790680 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651557095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3651557095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/102.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/103.edn_alert.3942870293 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 23251168 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942870293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 103.edn_alert.3942870293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/103.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/103.edn_genbits.1674941864 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 135019569 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:24 PM UTC 24 |
| Peak memory | 233336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674941864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1674941864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/103.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/104.edn_alert.712966731 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 273353530 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712966731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 104.edn_alert.712966731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/104.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/104.edn_genbits.1035895628 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 72253065 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:23 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035895628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1035895628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/104.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/105.edn_genbits.4166774140 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 42011851 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:23 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166774140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4166774140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/105.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/106.edn_alert.475429591 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 41824357 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475429591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 106.edn_alert.475429591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/106.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/106.edn_genbits.2366619650 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 54749013 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:23 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366619650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2366619650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/106.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/107.edn_alert.3281906558 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 24213863 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:23 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281906558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 107.edn_alert.3281906558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/107.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/107.edn_genbits.2723188537 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 30699961 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:23 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723188537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2723188537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/107.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/108.edn_alert.2645993472 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 62723321 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:17:22 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645993472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 108.edn_alert.2645993472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/108.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/108.edn_genbits.3159256921 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 36375563 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:17:20 PM UTC 24 |
| Finished | Oct 12 02:17:23 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159256921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3159256921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/108.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/109.edn_alert.1434052089 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 49774680 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:22 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434052089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 109.edn_alert.1434052089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/109.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/109.edn_genbits.3138948554 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 41216648 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:17:22 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138948554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3138948554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/109.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_alert.3306541062 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 34310726 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306541062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_alert.3306541062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_alert_test.158863092 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 14753612 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158863092 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.158863092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_disable.1407873240 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 75766962 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407873240 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1407873240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.1722666773 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 57702479 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722666773 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.1722666773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_err.1964517210 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 36044301 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 244136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964517210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 11.edn_err.1964517210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_genbits.1135935886 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 51308300 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:02 PM UTC 24 |
| Finished | Oct 12 02:15:05 PM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135935886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1135935886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_intr.4141930594 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 30247581 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141930594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4141930594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/11.edn_smoke.3575290894 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 16711799 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:15:02 PM UTC 24 |
| Finished | Oct 12 02:15:05 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575290894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_smoke.3575290894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/11.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/110.edn_alert.4056504917 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 119758786 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056504917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 110.edn_alert.4056504917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/110.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/110.edn_genbits.235004038 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 146544981 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 02:17:22 PM UTC 24 |
| Finished | Oct 12 02:17:26 PM UTC 24 |
| Peak memory | 233156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235004038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 110.edn_genbits.235004038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/110.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/111.edn_alert.1636191426 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 111804182 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636191426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 111.edn_alert.1636191426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/111.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/111.edn_genbits.2235832175 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 52890348 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:26 PM UTC 24 |
| Peak memory | 231208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235832175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2235832175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/111.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/112.edn_alert.363856330 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 107267287 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363856330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 112.edn_alert.363856330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/112.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/112.edn_genbits.2228730395 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 34005648 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228730395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2228730395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/112.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/113.edn_alert.1903199369 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 25833294 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:17:23 PM UTC 24 |
| Finished | Oct 12 02:17:25 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903199369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 113.edn_alert.1903199369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/113.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/114.edn_alert.3392705887 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 47600095 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:27 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392705887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 114.edn_alert.3392705887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/114.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/115.edn_alert.4282244063 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 25933750 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282244063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 115.edn_alert.4282244063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/115.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/115.edn_genbits.3933470941 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 84166387 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:27 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933470941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3933470941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/115.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/116.edn_alert.3858477645 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 292022002 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:27 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858477645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 116.edn_alert.3858477645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/116.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/116.edn_genbits.2555190826 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 61644946 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555190826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2555190826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/116.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/117.edn_alert.4110234007 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 77504050 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110234007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 117.edn_alert.4110234007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/117.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/117.edn_genbits.658156990 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 39719177 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658156990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 117.edn_genbits.658156990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/117.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/118.edn_alert.2026993497 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 46580569 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026993497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 118.edn_alert.2026993497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/118.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/119.edn_alert.4087196088 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 48877400 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087196088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 119.edn_alert.4087196088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/119.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/119.edn_genbits.585742833 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 145862178 ps |
| CPU time | 3.57 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 231028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585742833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 119.edn_genbits.585742833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/119.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_alert_test.134947014 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 16084776 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:15:06 PM UTC 24 |
| Finished | Oct 12 02:15:09 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134947014 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.134947014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_disable.543246235 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 13022065 ps |
| CPU time | 1 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:15:07 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543246235 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.543246235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.3473048186 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 42932296 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:15:08 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473048186 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.3473048186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_err.2663021574 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 23062643 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:15:07 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663021574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 12.edn_err.2663021574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_genbits.2923473073 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 29133908 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923473073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2923473073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_intr.2520800062 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 40008158 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:15:07 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520800062 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2520800062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_smoke.2622758825 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 25674514 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:15:04 PM UTC 24 |
| Finished | Oct 12 02:15:06 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622758825 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_smoke.2622758825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_stress_all.435380557 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 548681671 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 229052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435380557 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.435380557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.49058936 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3786670938 ps |
| CPU time | 64.34 seconds |
| Started | Oct 12 02:15:05 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 231220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49058936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_w ith_rand_reset.49058936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/120.edn_alert.1726088671 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 26731903 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726088671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 120.edn_alert.1726088671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/120.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/120.edn_genbits.851716200 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 76710194 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:25 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851716200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 120.edn_genbits.851716200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/120.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/121.edn_alert.793628227 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 153853555 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:17:26 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 230000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793628227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 121.edn_alert.793628227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/121.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/121.edn_genbits.982280078 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 50130556 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:17:26 PM UTC 24 |
| Finished | Oct 12 02:17:28 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982280078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 121.edn_genbits.982280078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/121.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/123.edn_alert.1216721766 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 26784663 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216721766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 123.edn_alert.1216721766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/123.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/123.edn_genbits.1927699161 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 94783704 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 231672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927699161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1927699161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/123.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/124.edn_alert.3931972161 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 44812325 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931972161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 124.edn_alert.3931972161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/124.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/125.edn_alert.3855820430 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 38407397 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855820430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 125.edn_alert.3855820430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/125.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/125.edn_genbits.2604448115 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 26945534 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604448115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2604448115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/125.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/126.edn_alert.515257374 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 25249840 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:31 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515257374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 126.edn_alert.515257374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/126.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/126.edn_genbits.2287398366 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 216725567 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:31 PM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287398366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2287398366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/126.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/127.edn_alert.3349449641 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 83907708 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:30 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349449641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 127.edn_alert.3349449641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/127.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/127.edn_genbits.2677462492 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 42684341 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:31 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677462492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2677462492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/127.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/128.edn_alert.1355743710 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 81376342 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:17:30 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355743710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 128.edn_alert.1355743710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/128.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/128.edn_genbits.956636076 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 56793466 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:17:28 PM UTC 24 |
| Finished | Oct 12 02:17:31 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956636076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 128.edn_genbits.956636076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/128.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/129.edn_alert.1890297138 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 51420812 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:17:30 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890297138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 129.edn_alert.1890297138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/129.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/129.edn_genbits.367799286 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 69191939 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:17:30 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367799286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 129.edn_genbits.367799286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/129.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_alert.205407247 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 90452167 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:15:08 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205407247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 13.edn_alert.205407247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_alert_test.3307404392 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 47480181 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:08 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 217352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307404392 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3307404392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_disable.1610266435 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 22913453 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:15:08 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610266435 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1610266435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2587532718 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 44418534 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:15:08 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587532718 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2587532718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_err.1864812267 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 20478227 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:15:08 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 238444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864812267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 13.edn_err.1864812267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_genbits.3706063538 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 30323804 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:15:06 PM UTC 24 |
| Finished | Oct 12 02:15:09 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706063538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3706063538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_intr.202814935 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 26097982 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:15:07 PM UTC 24 |
| Finished | Oct 12 02:15:09 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202814935 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.202814935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_smoke.1222108228 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 25422029 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:15:06 PM UTC 24 |
| Finished | Oct 12 02:15:08 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222108228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_smoke.1222108228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_stress_all.101749633 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 309777967 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 02:15:06 PM UTC 24 |
| Finished | Oct 12 02:15:10 PM UTC 24 |
| Peak memory | 231412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101749633 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.101749633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.83772922 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 7383267728 ps |
| CPU time | 40.53 seconds |
| Started | Oct 12 02:15:07 PM UTC 24 |
| Finished | Oct 12 02:15:49 PM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83772922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_w ith_rand_reset.83772922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/130.edn_alert.3999005759 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 44885583 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999005759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 130.edn_alert.3999005759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/130.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/131.edn_alert.57115464 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 68093362 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 227908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57115464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.57115464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/131.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/131.edn_genbits.1525847794 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 167475830 ps |
| CPU time | 3.14 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:35 PM UTC 24 |
| Peak memory | 233052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525847794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1525847794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/131.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/132.edn_alert.2951822059 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 52167383 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951822059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 132.edn_alert.2951822059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/132.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/132.edn_genbits.2854423384 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 138425389 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854423384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2854423384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/132.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/133.edn_alert.2741310004 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 88017472 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741310004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 133.edn_alert.2741310004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/133.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/133.edn_genbits.2425110448 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 106112657 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425110448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2425110448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/133.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/134.edn_alert.1453285416 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 25458657 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453285416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 134.edn_alert.1453285416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/134.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/134.edn_genbits.1090206923 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 68286874 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 230188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090206923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1090206923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/134.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/135.edn_alert.4283141937 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 73493247 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283141937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 135.edn_alert.4283141937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/135.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/135.edn_genbits.2001082821 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 50082686 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:31 PM UTC 24 |
| Finished | Oct 12 02:17:33 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001082821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2001082821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/135.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/136.edn_alert.3388395051 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 56401388 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:35 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388395051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 136.edn_alert.3388395051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/136.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/136.edn_genbits.4063025706 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 70068861 ps |
| CPU time | 2.69 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:37 PM UTC 24 |
| Peak memory | 233076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063025706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4063025706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/136.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/137.edn_alert.4030745320 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 79871394 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030745320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 137.edn_alert.4030745320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/137.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/137.edn_genbits.556620854 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 45999867 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:35 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556620854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 137.edn_genbits.556620854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/137.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/138.edn_alert.9683044 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 93602754 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:35 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9683044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.9683044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/138.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/138.edn_genbits.2218375911 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 52763366 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:35 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218375911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2218375911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/138.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/139.edn_alert.600222582 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 47164198 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600222582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 139.edn_alert.600222582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/139.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/139.edn_genbits.211692373 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 90865888 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 229120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211692373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 139.edn_genbits.211692373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/139.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_alert_test.1103902527 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 16185776 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:13 PM UTC 24 |
| Peak memory | 217492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103902527 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1103902527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_disable.839830372 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29739929 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:12 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839830372 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.839830372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.3138059698 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 77881220 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:13 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138059698 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.3138059698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_genbits.220796932 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 68315075 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:15:09 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220796932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.edn_genbits.220796932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_intr.3725214894 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 25067562 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:15:09 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 228108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725214894 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3725214894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/14.edn_smoke.1074961687 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 73541793 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:08 PM UTC 24 |
| Finished | Oct 12 02:15:11 PM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074961687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_smoke.1074961687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/14.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/140.edn_alert.3734328527 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 122492596 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:35 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734328527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 140.edn_alert.3734328527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/140.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/140.edn_genbits.2336614089 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 43199107 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336614089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2336614089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/140.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/141.edn_alert.3794097838 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 29762764 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794097838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 141.edn_alert.3794097838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/141.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/141.edn_genbits.2780643587 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 71605548 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:17:33 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780643587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2780643587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/141.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/142.edn_alert.3762888582 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 26832272 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:17:34 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762888582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 142.edn_alert.3762888582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/142.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/142.edn_genbits.992635113 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 40256627 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:34 PM UTC 24 |
| Finished | Oct 12 02:17:36 PM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992635113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 142.edn_genbits.992635113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/142.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/143.edn_alert.2592127647 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 28108967 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592127647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 143.edn_alert.2592127647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/143.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/143.edn_genbits.260287902 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 91704201 ps |
| CPU time | 2.98 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:40 PM UTC 24 |
| Peak memory | 233084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260287902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 143.edn_genbits.260287902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/143.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/144.edn_alert.1626968163 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 76250614 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626968163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 144.edn_alert.1626968163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/144.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/144.edn_genbits.1315986546 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 37349326 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315986546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1315986546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/144.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/145.edn_alert.1418093241 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 44496718 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418093241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 145.edn_alert.1418093241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/145.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/145.edn_genbits.2601100833 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 141153183 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601100833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2601100833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/145.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/146.edn_alert.1844701785 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 94961940 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844701785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 146.edn_alert.1844701785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/146.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/146.edn_genbits.2579876199 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 48544341 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:40 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579876199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2579876199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/146.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/147.edn_alert.1700328718 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 27047671 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700328718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 147.edn_alert.1700328718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/147.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/147.edn_genbits.1118724605 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 43466743 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:39 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118724605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1118724605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/147.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/148.edn_alert.1859570077 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 22737653 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859570077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 148.edn_alert.1859570077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/148.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/148.edn_genbits.3422857202 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 95682106 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422857202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3422857202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/148.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/149.edn_alert.3019182660 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 35645820 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:38 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019182660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 149.edn_alert.3019182660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/149.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/149.edn_genbits.2183709511 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 113672410 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:39 PM UTC 24 |
| Peak memory | 230164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183709511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2183709511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/149.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_alert.2644520604 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 26145107 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644520604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.edn_alert.2644520604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_alert_test.3674513747 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 16392451 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:14 PM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674513747 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3674513747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_disable.481099979 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 82316535 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:14 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481099979 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.481099979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.3693137576 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 37179395 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693137576 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.3693137576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_err.4269593573 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 36093562 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:14 PM UTC 24 |
| Peak memory | 238428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269593573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 15.edn_err.4269593573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_genbits.2388397816 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 72598961 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:13 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388397816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2388397816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_intr.246549616 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 27060106 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:12 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246549616 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.246549616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_smoke.2121075092 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 44675437 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:13 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121075092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.edn_smoke.2121075092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_stress_all.1713821456 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 227660557 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 229048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713821456 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1713821456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.225639820 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 9356080839 ps |
| CPU time | 59.45 seconds |
| Started | Oct 12 02:15:10 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 231300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225639820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_ with_rand_reset.225639820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/150.edn_alert.3974022830 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 54128231 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:39 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974022830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 150.edn_alert.3974022830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/150.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/150.edn_genbits.3336487655 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 105271905 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:36 PM UTC 24 |
| Finished | Oct 12 02:17:39 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336487655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3336487655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/150.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/151.edn_alert.1871968804 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 68136918 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:17:38 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871968804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 151.edn_alert.1871968804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/151.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/151.edn_genbits.1950282045 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 47589316 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:17:37 PM UTC 24 |
| Finished | Oct 12 02:17:40 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950282045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1950282045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/151.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/152.edn_alert.577314127 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 46749753 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577314127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 152.edn_alert.577314127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/152.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/152.edn_genbits.830347698 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 31719431 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830347698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 152.edn_genbits.830347698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/152.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/153.edn_alert.1185938987 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 174080649 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185938987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 153.edn_alert.1185938987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/153.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/153.edn_genbits.264412458 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 79106729 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264412458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 153.edn_genbits.264412458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/153.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/154.edn_alert.4217008042 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 41788695 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217008042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 154.edn_alert.4217008042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/154.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/154.edn_genbits.1912586747 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 66083562 ps |
| CPU time | 2.43 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:42 PM UTC 24 |
| Peak memory | 231016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912586747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1912586747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/154.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/155.edn_alert.1129183292 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 142826393 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129183292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 155.edn_alert.1129183292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/155.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/155.edn_genbits.2342059195 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 101312587 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342059195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2342059195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/155.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/156.edn_alert.2730459003 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 42799155 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:42 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730459003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 156.edn_alert.2730459003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/156.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/156.edn_genbits.1273961996 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 62334679 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:17:39 PM UTC 24 |
| Finished | Oct 12 02:17:41 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273961996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1273961996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/156.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/157.edn_alert.3916211036 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 27887228 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:42 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916211036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 157.edn_alert.3916211036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/157.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/157.edn_genbits.1914303126 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 73158574 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914303126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1914303126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/157.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/158.edn_alert.1159453453 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 38982044 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:42 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159453453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 158.edn_alert.1159453453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/158.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/158.edn_genbits.1126712773 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 78012045 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:42 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126712773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1126712773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/158.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/159.edn_alert.2594970598 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 58107725 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594970598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 159.edn_alert.2594970598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/159.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/159.edn_genbits.1516139465 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 36427388 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516139465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1516139465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/159.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_alert_test.3036616207 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 52908179 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036616207 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3036616207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_err.2223597305 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 28629182 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223597305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 16.edn_err.2223597305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_genbits.1942053812 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 60424616 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 233220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942053812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1942053812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_intr.3175560801 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 23138123 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:15 PM UTC 24 |
| Peak memory | 238508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175560801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3175560801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_smoke.1240378746 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 52917069 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:14 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240378746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_smoke.1240378746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/16.edn_stress_all.472412219 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 510164219 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 02:15:12 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 231096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472412219 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.472412219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/16.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/160.edn_alert.2806419873 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 64985360 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806419873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 160.edn_alert.2806419873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/160.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/160.edn_genbits.4292904912 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 88198337 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292904912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4292904912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/160.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/161.edn_alert.3679744208 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 42687262 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:42 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679744208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 161.edn_alert.3679744208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/161.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/161.edn_genbits.3269473854 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 140500180 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269473854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3269473854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/161.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/162.edn_alert.1751843346 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 102186806 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751843346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 162.edn_alert.1751843346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/162.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/162.edn_genbits.1578832554 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 26884349 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:17:40 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578832554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1578832554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/162.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/163.edn_alert.1294871016 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 26160456 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:17:41 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294871016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 163.edn_alert.1294871016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/163.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/163.edn_genbits.555447975 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 30672172 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:41 PM UTC 24 |
| Finished | Oct 12 02:17:43 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555447975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 163.edn_genbits.555447975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/163.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/164.edn_alert.2600771132 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 29250594 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600771132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 164.edn_alert.2600771132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/164.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/164.edn_genbits.3606530166 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 117198248 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 227652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606530166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3606530166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/164.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/165.edn_alert.2817993529 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 42588882 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817993529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 165.edn_alert.2817993529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/165.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/165.edn_genbits.4268196377 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 34216091 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268196377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4268196377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/165.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/166.edn_alert.453409439 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 109700714 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453409439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 166.edn_alert.453409439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/166.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/166.edn_genbits.1784493827 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 79908236 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784493827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1784493827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/166.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/167.edn_alert.2153225465 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 50995998 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153225465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 167.edn_alert.2153225465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/167.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/167.edn_genbits.3146869252 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 137572498 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:47 PM UTC 24 |
| Peak memory | 233148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146869252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3146869252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/167.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/168.edn_alert.4091281118 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 25820850 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091281118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 168.edn_alert.4091281118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/168.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/168.edn_genbits.615205397 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 67618089 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:45 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615205397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 168.edn_genbits.615205397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/168.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/169.edn_alert.3678185254 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 25106781 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678185254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 169.edn_alert.3678185254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/169.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/169.edn_genbits.3822697671 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 51799316 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822697671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3822697671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/169.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_alert_test.2616237461 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 40337807 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:17 PM UTC 24 |
| Peak memory | 217492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616237461 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2616237461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_disable.572890542 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 21599260 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:17 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572890542 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.572890542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.231847540 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 74889344 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:17 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231847540 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.231847540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_err.239243095 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 46366148 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:18 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239243095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 17.edn_err.239243095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_intr.212506254 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 37550597 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212506254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.212506254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_smoke.681875349 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 46222913 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:16 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681875349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.edn_smoke.681875349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_stress_all.1337727052 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 309734285 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:15:21 PM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337727052 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1337727052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.2959959693 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3678719709 ps |
| CPU time | 49.14 seconds |
| Started | Oct 12 02:15:14 PM UTC 24 |
| Finished | Oct 12 02:16:04 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959959693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all _with_rand_reset.2959959693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/170.edn_genbits.356006137 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 65150591 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356006137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 170.edn_genbits.356006137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/170.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/171.edn_alert.4076116818 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 24115252 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076116818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 171.edn_alert.4076116818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/171.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/171.edn_genbits.370121524 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 81351264 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:17:43 PM UTC 24 |
| Finished | Oct 12 02:17:46 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370121524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 171.edn_genbits.370121524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/171.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/172.edn_genbits.593686981 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 40199987 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:45 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593686981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 172.edn_genbits.593686981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/172.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/173.edn_alert.2260005789 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 86649219 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260005789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 173.edn_alert.2260005789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/173.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/173.edn_genbits.3604961369 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 23621568 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604961369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3604961369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/173.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/174.edn_alert.2408175177 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 29277562 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408175177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 174.edn_alert.2408175177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/174.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/174.edn_genbits.1462469593 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 47840524 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462469593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1462469593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/174.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/175.edn_alert.3279976307 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 204094020 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279976307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 175.edn_alert.3279976307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/175.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/175.edn_genbits.933863443 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 112364069 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933863443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 175.edn_genbits.933863443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/175.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/176.edn_alert.4078798471 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 320684321 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078798471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 176.edn_alert.4078798471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/176.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/177.edn_alert.18737058 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 27598970 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18737058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.18737058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/177.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/177.edn_genbits.972249724 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 95512448 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:49 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972249724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 177.edn_genbits.972249724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/177.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/178.edn_alert.3987834715 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 53979096 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:49 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987834715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 178.edn_alert.3987834715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/178.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/178.edn_genbits.1884812323 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 100401044 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884812323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1884812323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/178.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/179.edn_alert.1813308837 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 89704665 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:49 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813308837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 179.edn_alert.1813308837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/179.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/179.edn_genbits.3384037761 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 36920982 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:17:46 PM UTC 24 |
| Finished | Oct 12 02:17:48 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384037761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3384037761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/179.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_alert_test.1078497878 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 156730046 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078497878 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1078497878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.296208988 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 105941265 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296208988 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.296208988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_err.123946053 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 24526526 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:15:16 PM UTC 24 |
| Finished | Oct 12 02:15:18 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123946053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 18.edn_err.123946053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_intr.736133772 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 25395453 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:18 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736133772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.736133772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_smoke.2396985370 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 53446107 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:17 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396985370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_smoke.2396985370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/18.edn_stress_all.3627598943 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 411255099 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 02:15:15 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 229040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627598943 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3627598943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/18.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/180.edn_alert.4082781075 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 57661530 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:50 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082781075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 180.edn_alert.4082781075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/180.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/180.edn_genbits.3210189663 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 166957287 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:50 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210189663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3210189663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/180.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/181.edn_alert.120763684 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 25502543 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:50 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120763684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 181.edn_alert.120763684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/181.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/181.edn_genbits.543921294 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 93253523 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:50 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543921294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 181.edn_genbits.543921294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/181.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/182.edn_alert.3725882350 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 108195333 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725882350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 182.edn_alert.3725882350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/182.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/182.edn_genbits.1830827535 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 180760112 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 02:17:47 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 233080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830827535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1830827535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/182.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/183.edn_alert.278991302 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 28121410 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:17:48 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278991302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 183.edn_alert.278991302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/183.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/183.edn_genbits.961451133 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 54175308 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:17:48 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961451133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 183.edn_genbits.961451133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/183.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/184.edn_alert.3523195941 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 25401228 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:17:48 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523195941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 184.edn_alert.3523195941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/184.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/184.edn_genbits.259010958 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 31085297 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:17:48 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259010958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 184.edn_genbits.259010958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/184.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/185.edn_alert.3521576760 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 113135000 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521576760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 185.edn_alert.3521576760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/185.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/185.edn_genbits.3135503902 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 44044101 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:17:48 PM UTC 24 |
| Finished | Oct 12 02:17:50 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135503902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3135503902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/185.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/186.edn_alert.653433264 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 230933110 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653433264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 186.edn_alert.653433264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/186.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/186.edn_genbits.3129365511 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 61288122 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129365511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3129365511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/186.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/187.edn_alert.2690735699 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 93711365 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690735699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 187.edn_alert.2690735699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/187.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/187.edn_genbits.3978633590 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 74025248 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 233140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978633590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3978633590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/187.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/188.edn_alert.2840669020 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 89275167 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840669020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 188.edn_alert.2840669020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/188.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/188.edn_genbits.192448497 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 38138106 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192448497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 188.edn_genbits.192448497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/188.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/189.edn_alert.805359917 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 24819732 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805359917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 189.edn_alert.805359917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/189.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/189.edn_genbits.1550826682 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 51893363 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550826682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1550826682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/189.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_alert.1539253303 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 50126928 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:21 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539253303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_alert.1539253303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_alert_test.3965846731 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 22694594 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:20 PM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965846731 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3965846731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_disable.2589585816 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 23220455 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:20 PM UTC 24 |
| Peak memory | 227972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589585816 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2589585816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_err.4253342982 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 26463061 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:21 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253342982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 19.edn_err.4253342982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_genbits.3828188773 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 71262383 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:20 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828188773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3828188773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_intr.195718654 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 22380445 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195718654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.195718654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_smoke.2080083256 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 30289360 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:19 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080083256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_smoke.2080083256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/19.edn_stress_all.2020414731 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 316378094 ps |
| CPU time | 7.59 seconds |
| Started | Oct 12 02:15:17 PM UTC 24 |
| Finished | Oct 12 02:15:26 PM UTC 24 |
| Peak memory | 229052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020414731 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2020414731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/19.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/190.edn_alert.416219910 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 24671532 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416219910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 190.edn_alert.416219910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/190.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/190.edn_genbits.2820215094 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 76050464 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820215094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2820215094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/190.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/191.edn_alert.2258650098 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 44144394 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258650098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 191.edn_alert.2258650098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/191.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/191.edn_genbits.3580617517 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 76979944 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580617517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3580617517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/191.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/192.edn_alert.2294761087 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 23088872 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294761087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 192.edn_alert.2294761087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/192.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/192.edn_genbits.3081862661 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 38603076 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:17:49 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081862661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3081862661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/192.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/193.edn_alert.98388803 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 78745839 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:17:50 PM UTC 24 |
| Finished | Oct 12 02:17:53 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98388803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.98388803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/193.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/193.edn_genbits.4035554783 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 31579421 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:17:50 PM UTC 24 |
| Finished | Oct 12 02:17:56 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035554783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.4035554783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/193.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/194.edn_alert.3130904738 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 63807792 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:17:51 PM UTC 24 |
| Finished | Oct 12 02:17:56 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130904738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 194.edn_alert.3130904738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/194.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/194.edn_genbits.1017168368 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 44814916 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:51 PM UTC 24 |
| Finished | Oct 12 02:17:53 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017168368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1017168368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/194.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/195.edn_alert.1795257367 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 86100476 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:17:51 PM UTC 24 |
| Finished | Oct 12 02:17:56 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795257367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 195.edn_alert.1795257367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/195.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/195.edn_genbits.3551111968 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 78143804 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:17:51 PM UTC 24 |
| Finished | Oct 12 02:17:56 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551111968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3551111968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/195.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/196.edn_alert.3029168791 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 117627781 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:07 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029168791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 196.edn_alert.3029168791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/196.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/196.edn_genbits.3593128939 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 27920803 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:17:51 PM UTC 24 |
| Finished | Oct 12 02:17:56 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593128939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3593128939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/196.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/197.edn_alert.2822764700 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 121101032 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:07 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822764700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 197.edn_alert.2822764700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/197.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/197.edn_genbits.1405353908 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 109662517 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405353908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1405353908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/197.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/198.edn_alert.1998742207 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 86693448 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998742207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 198.edn_alert.1998742207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/198.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/198.edn_genbits.2880252350 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 39590827 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880252350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2880252350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/198.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/199.edn_alert.4063213728 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 136781863 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063213728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 199.edn_alert.4063213728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/199.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_alert.3996238516 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 22708865 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996238516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_alert.3996238516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_disable.3341280757 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13191674 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341280757 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3341280757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_err.430749881 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 24082874 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430749881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.edn_err.430749881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_intr.1683450457 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 25579125 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683450457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1683450457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_regwen.1368222626 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 33431046 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:14:42 PM UTC 24 |
| Finished | Oct 12 02:14:45 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368222626 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.edn_regwen.1368222626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_sec_cm.4213677114 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2116623021 ps |
| CPU time | 9.02 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:54 PM UTC 24 |
| Peak memory | 261812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213677114 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.4213677114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_smoke.3991709694 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 107451649 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:14:42 PM UTC 24 |
| Finished | Oct 12 02:14:44 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991709694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_smoke.3991709694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/2.edn_stress_all.329144625 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 195275992 ps |
| CPU time | 4.4 seconds |
| Started | Oct 12 02:14:42 PM UTC 24 |
| Finished | Oct 12 02:14:48 PM UTC 24 |
| Peak memory | 229040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329144625 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.329144625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_alert.3419120165 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 68021306 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419120165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_alert.3419120165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_alert_test.1338519303 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 11859166 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338519303 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1338519303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_disable.3479018017 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 36816414 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479018017 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3479018017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.553170003 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 39931185 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:23 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553170003 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.553170003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_err.2902811904 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 31735388 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902811904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 20.edn_err.2902811904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_genbits.1515194281 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 55221025 ps |
| CPU time | 2.29 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515194281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1515194281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_intr.786941911 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 22270857 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786941911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.786941911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_smoke.266512870 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 75738261 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:21 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266512870 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 20.edn_smoke.266512870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_stress_all.2826789136 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1090161068 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 02:15:18 PM UTC 24 |
| Finished | Oct 12 02:15:24 PM UTC 24 |
| Peak memory | 229056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826789136 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2826789136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.2049788659 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 6024051929 ps |
| CPU time | 67.26 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:16:29 PM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049788659 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all _with_rand_reset.2049788659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/200.edn_genbits.187469471 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 36766748 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187469471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 200.edn_genbits.187469471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/200.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/201.edn_genbits.1429423567 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 35446820 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 227996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429423567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1429423567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/201.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/202.edn_genbits.2012688924 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 59149739 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012688924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2012688924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/202.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/203.edn_genbits.2886599400 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 32656433 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:52 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886599400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2886599400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/203.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/204.edn_genbits.3341668903 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 72959283 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341668903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3341668903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/204.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/205.edn_genbits.3173696872 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 63338080 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173696872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3173696872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/205.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/206.edn_genbits.3582958512 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 40980202 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582958512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3582958512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/206.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/207.edn_genbits.480409223 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 66626636 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480409223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 207.edn_genbits.480409223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/207.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/208.edn_genbits.3850000834 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 32159542 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850000834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3850000834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/208.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/209.edn_genbits.3893730196 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 60357901 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:58 PM UTC 24 |
| Peak memory | 233068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893730196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3893730196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/209.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_alert.541358600 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 32070759 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 02:15:21 PM UTC 24 |
| Finished | Oct 12 02:15:24 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541358600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 21.edn_alert.541358600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_alert_test.3344603539 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 14842963 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:15:23 PM UTC 24 |
| Finished | Oct 12 02:15:25 PM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344603539 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3344603539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_disable.801506076 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 15210925 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:15:21 PM UTC 24 |
| Finished | Oct 12 02:15:24 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801506076 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.801506076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.2914703419 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 138108366 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:15:21 PM UTC 24 |
| Finished | Oct 12 02:15:24 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914703419 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.2914703419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_err.3761449297 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 44513449 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:15:21 PM UTC 24 |
| Finished | Oct 12 02:15:24 PM UTC 24 |
| Peak memory | 244136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761449297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 21.edn_err.3761449297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_genbits.2233611387 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 118281457 ps |
| CPU time | 3.77 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:25 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233611387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2233611387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_intr.1997489319 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 69949747 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:15:21 PM UTC 24 |
| Finished | Oct 12 02:15:23 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997489319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1997489319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_smoke.1177671764 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 121254874 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:22 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177671764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.edn_smoke.1177671764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_stress_all.3014678695 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 321572992 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 02:15:20 PM UTC 24 |
| Finished | Oct 12 02:15:24 PM UTC 24 |
| Peak memory | 229056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014678695 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3014678695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3186955566 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 32099120534 ps |
| CPU time | 90.1 seconds |
| Started | Oct 12 02:15:21 PM UTC 24 |
| Finished | Oct 12 02:16:53 PM UTC 24 |
| Peak memory | 231408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186955566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all _with_rand_reset.3186955566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/210.edn_genbits.336617671 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 83615323 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:53 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336617671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.336617671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/210.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/211.edn_genbits.435509107 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 33320408 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435509107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 211.edn_genbits.435509107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/211.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/212.edn_genbits.2862363781 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 287199794 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:17:58 PM UTC 24 |
| Peak memory | 233080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862363781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2862363781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/212.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/213.edn_genbits.568457166 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 49291436 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568457166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 213.edn_genbits.568457166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/213.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/214.edn_genbits.1741673351 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 60197201 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:17:57 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741673351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1741673351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/214.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/215.edn_genbits.1366307950 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 81316036 ps |
| CPU time | 2.73 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:17:58 PM UTC 24 |
| Peak memory | 231420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366307950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1366307950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/215.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/216.edn_genbits.887272756 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 43697178 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:18:07 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887272756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 216.edn_genbits.887272756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/216.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/217.edn_genbits.2420884005 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 123034713 ps |
| CPU time | 2.87 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:18:09 PM UTC 24 |
| Peak memory | 233192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420884005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2420884005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/217.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/218.edn_genbits.3997356493 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 78718465 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:17:54 PM UTC 24 |
| Finished | Oct 12 02:18:07 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997356493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3997356493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/218.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/219.edn_genbits.3662840886 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 70491263 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:17:57 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662840886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3662840886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/219.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_alert.3215686565 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 46391700 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:15:23 PM UTC 24 |
| Finished | Oct 12 02:15:25 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215686565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.edn_alert.3215686565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_alert_test.210700278 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 47514544 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:15:24 PM UTC 24 |
| Finished | Oct 12 02:15:26 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210700278 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.210700278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_disable.3582678617 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 18639360 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:15:24 PM UTC 24 |
| Finished | Oct 12 02:15:26 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582678617 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3582678617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.297648396 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 44013101 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 02:15:24 PM UTC 24 |
| Finished | Oct 12 02:15:27 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297648396 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.297648396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_err.27815843 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 22125051 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:24 PM UTC 24 |
| Finished | Oct 12 02:15:26 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27815843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 22.edn_err.27815843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_genbits.4077258468 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 43465546 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:15:23 PM UTC 24 |
| Finished | Oct 12 02:15:25 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077258468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4077258468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_intr.1100750901 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 33936837 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:15:23 PM UTC 24 |
| Finished | Oct 12 02:15:25 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100750901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1100750901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_smoke.619030029 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 28443979 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:15:23 PM UTC 24 |
| Finished | Oct 12 02:15:25 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619030029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 22.edn_smoke.619030029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/22.edn_stress_all.3143651275 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 110686820 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 02:15:23 PM UTC 24 |
| Finished | Oct 12 02:15:26 PM UTC 24 |
| Peak memory | 231096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143651275 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3143651275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/22.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/220.edn_genbits.2192249529 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 79252674 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:17:57 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192249529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2192249529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/220.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/221.edn_genbits.1943913859 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 32689816 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:17:57 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943913859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1943913859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/221.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/222.edn_genbits.3669883652 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 39959070 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:17:57 PM UTC 24 |
| Finished | Oct 12 02:18:06 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669883652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3669883652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/222.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/223.edn_genbits.2102276035 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 24832133 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:17:57 PM UTC 24 |
| Finished | Oct 12 02:18:06 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102276035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2102276035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/223.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/224.edn_genbits.311130325 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 23178514 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:01 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311130325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 224.edn_genbits.311130325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/224.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/225.edn_genbits.3627654542 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 39024151 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627654542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3627654542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/225.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/226.edn_genbits.2846203561 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 34218288 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 232564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846203561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2846203561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/226.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/227.edn_genbits.865733579 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 46078183 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865733579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 227.edn_genbits.865733579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/227.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/228.edn_genbits.957593653 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 57438547 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957593653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 228.edn_genbits.957593653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/228.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/229.edn_genbits.4276709162 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 63292597 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 228752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276709162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4276709162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/229.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_alert.3465111975 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 51915055 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:15:26 PM UTC 24 |
| Finished | Oct 12 02:15:28 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465111975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.edn_alert.3465111975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_alert_test.2611830143 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 40511658 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 02:15:27 PM UTC 24 |
| Finished | Oct 12 02:15:29 PM UTC 24 |
| Peak memory | 228380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611830143 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2611830143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_disable.96387930 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 85337350 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:26 PM UTC 24 |
| Finished | Oct 12 02:15:28 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96387930 -assert nopostproc +UVM_TESTNAME=edn_disab le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.96387930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.1303411694 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 63138230 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:15:26 PM UTC 24 |
| Finished | Oct 12 02:15:29 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303411694 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.1303411694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_err.1002762473 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 36601979 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:15:26 PM UTC 24 |
| Finished | Oct 12 02:15:28 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002762473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 23.edn_err.1002762473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_genbits.2007966841 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 45094374 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 02:15:25 PM UTC 24 |
| Finished | Oct 12 02:15:28 PM UTC 24 |
| Peak memory | 231084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007966841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2007966841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_intr.844153872 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 42977906 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:15:25 PM UTC 24 |
| Finished | Oct 12 02:15:28 PM UTC 24 |
| Peak memory | 238500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844153872 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.844153872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_smoke.2049384526 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 18122227 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:15:24 PM UTC 24 |
| Finished | Oct 12 02:15:27 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049384526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.edn_smoke.2049384526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/23.edn_stress_all.2462812950 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 48286357 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:15:25 PM UTC 24 |
| Finished | Oct 12 02:15:28 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462812950 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2462812950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/23.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/230.edn_genbits.3105328405 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 53301236 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105328405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3105328405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/230.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/231.edn_genbits.1472285773 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 49881519 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472285773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1472285773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/231.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/232.edn_genbits.3094556884 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 193152918 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:01 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094556884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3094556884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/232.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/233.edn_genbits.3084036460 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 33124355 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:58 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084036460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3084036460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/233.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/234.edn_genbits.1966923377 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 267017403 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:17:59 PM UTC 24 |
| Finished | Oct 12 02:18:02 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966923377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1966923377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/234.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/235.edn_genbits.608158640 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 56835441 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:17:59 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608158640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 235.edn_genbits.608158640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/235.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/236.edn_genbits.1551601214 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 66639559 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:18:02 PM UTC 24 |
| Finished | Oct 12 02:18:08 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551601214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1551601214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/236.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/237.edn_genbits.909409676 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 38474407 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:18:02 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909409676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 237.edn_genbits.909409676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/237.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/238.edn_genbits.2500049112 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 151551070 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500049112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2500049112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/238.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/239.edn_genbits.2188108249 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 49482804 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188108249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2188108249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/239.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_alert.1954188654 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 54317072 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:15:27 PM UTC 24 |
| Finished | Oct 12 02:15:29 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954188654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.edn_alert.1954188654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_alert_test.3965066516 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 18486072 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:15:28 PM UTC 24 |
| Finished | Oct 12 02:15:30 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965066516 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3965066516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2002888874 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 93213551 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:15:28 PM UTC 24 |
| Finished | Oct 12 02:15:31 PM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002888874 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.2002888874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_err.109713042 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 21045887 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:15:28 PM UTC 24 |
| Finished | Oct 12 02:15:31 PM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109713042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 24.edn_err.109713042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_genbits.2368154077 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 147582691 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:15:27 PM UTC 24 |
| Finished | Oct 12 02:15:29 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368154077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2368154077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_intr.162733536 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 21247322 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:15:27 PM UTC 24 |
| Finished | Oct 12 02:15:30 PM UTC 24 |
| Peak memory | 238500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162733536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.162733536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_smoke.3500327603 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 40982047 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:15:27 PM UTC 24 |
| Finished | Oct 12 02:15:29 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500327603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.edn_smoke.3500327603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/24.edn_stress_all.1862062736 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 492573613 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 02:15:27 PM UTC 24 |
| Finished | Oct 12 02:15:34 PM UTC 24 |
| Peak memory | 231088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862062736 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1862062736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/24.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/240.edn_genbits.3406263709 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 151851643 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:11 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406263709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3406263709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/240.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/241.edn_genbits.3022124022 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 37721244 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:11 PM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022124022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3022124022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/241.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/242.edn_genbits.1413076751 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 46607157 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:11 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413076751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1413076751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/242.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/243.edn_genbits.3993577306 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 53479432 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993577306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3993577306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/243.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/244.edn_genbits.2209892470 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 28572090 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209892470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2209892470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/244.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/245.edn_genbits.1627700813 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 38652520 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627700813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1627700813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/245.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/246.edn_genbits.3082421912 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 264001692 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082421912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3082421912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/246.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/247.edn_genbits.471839903 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 45432678 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471839903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 247.edn_genbits.471839903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/247.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/248.edn_genbits.2153961198 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 36429161 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:18:03 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153961198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2153961198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/248.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/249.edn_genbits.3731392806 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 21277682 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:18:07 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731392806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3731392806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/249.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_alert.4054195470 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 199822116 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 02:15:30 PM UTC 24 |
| Finished | Oct 12 02:15:33 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054195470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.edn_alert.4054195470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_alert_test.1487447170 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 80951391 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:15:31 PM UTC 24 |
| Finished | Oct 12 02:15:34 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487447170 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1487447170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_disable.2950091063 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 39814784 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:30 PM UTC 24 |
| Finished | Oct 12 02:15:32 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950091063 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2950091063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.2464055604 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 32579753 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:15:30 PM UTC 24 |
| Finished | Oct 12 02:15:33 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464055604 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2464055604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_err.2924288040 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 21151445 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:15:30 PM UTC 24 |
| Finished | Oct 12 02:15:32 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924288040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 25.edn_err.2924288040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_genbits.3833062605 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 21694905 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:15:29 PM UTC 24 |
| Finished | Oct 12 02:15:32 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833062605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3833062605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_smoke.211124708 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 30495943 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:15:29 PM UTC 24 |
| Finished | Oct 12 02:15:32 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211124708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 25.edn_smoke.211124708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/25.edn_stress_all.349755031 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1487742319 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 02:15:29 PM UTC 24 |
| Finished | Oct 12 02:15:35 PM UTC 24 |
| Peak memory | 229048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349755031 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.349755031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/25.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/250.edn_genbits.3691708000 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 40523750 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:18:07 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691708000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3691708000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/250.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/251.edn_genbits.3517227942 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 22990953 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:18:07 PM UTC 24 |
| Finished | Oct 12 02:18:16 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517227942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3517227942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/251.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/252.edn_genbits.1400603262 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 39410981 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:18:08 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400603262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1400603262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/252.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/253.edn_genbits.813574924 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 107181523 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:18:08 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813574924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 253.edn_genbits.813574924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/253.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/254.edn_genbits.1447599366 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 49071646 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:18:08 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447599366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1447599366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/254.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/255.edn_genbits.1943565918 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 42810550 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 02:18:08 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943565918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1943565918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/255.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/256.edn_genbits.931057317 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 97718447 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:18:08 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931057317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 256.edn_genbits.931057317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/256.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/258.edn_genbits.37300344 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 82531078 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:18:09 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37300344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 258.edn_genbits.37300344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/258.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/259.edn_genbits.251487617 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 77376054 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:18:09 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251487617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 259.edn_genbits.251487617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/259.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_alert.1246815047 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 22216398 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:33 PM UTC 24 |
| Finished | Oct 12 02:15:35 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246815047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.edn_alert.1246815047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_alert_test.2836766635 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 31836636 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:15:33 PM UTC 24 |
| Finished | Oct 12 02:15:35 PM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836766635 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2836766635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_disable.2927194768 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 37162223 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:33 PM UTC 24 |
| Finished | Oct 12 02:15:35 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927194768 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2927194768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.2512470097 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 38925824 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:15:33 PM UTC 24 |
| Finished | Oct 12 02:15:36 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512470097 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.2512470097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_genbits.3619427574 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 42343712 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:15:31 PM UTC 24 |
| Finished | Oct 12 02:15:34 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619427574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3619427574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_intr.1901535584 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 21129216 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:15:31 PM UTC 24 |
| Finished | Oct 12 02:15:34 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901535584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1901535584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_smoke.2545443109 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 16161092 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:15:31 PM UTC 24 |
| Finished | Oct 12 02:15:34 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545443109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.edn_smoke.2545443109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/26.edn_stress_all.3674696048 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 317486382 ps |
| CPU time | 6.16 seconds |
| Started | Oct 12 02:15:31 PM UTC 24 |
| Finished | Oct 12 02:15:39 PM UTC 24 |
| Peak memory | 231072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674696048 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3674696048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/26.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/260.edn_genbits.161138889 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 132670615 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:18:09 PM UTC 24 |
| Finished | Oct 12 02:18:12 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161138889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 260.edn_genbits.161138889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/260.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/261.edn_genbits.1139546207 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 62797573 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:18:10 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139546207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1139546207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/261.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/262.edn_genbits.1215397861 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 33790981 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:18:10 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215397861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1215397861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/262.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/263.edn_genbits.605045767 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 131367103 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:18:10 PM UTC 24 |
| Finished | Oct 12 02:18:13 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605045767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 263.edn_genbits.605045767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/263.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/264.edn_genbits.1786071174 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 113773037 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:18:11 PM UTC 24 |
| Finished | Oct 12 02:18:26 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786071174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1786071174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/264.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/265.edn_genbits.908463193 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 42165679 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:18:12 PM UTC 24 |
| Finished | Oct 12 02:18:22 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908463193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 265.edn_genbits.908463193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/265.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/266.edn_genbits.3040899961 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 75405539 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:18:12 PM UTC 24 |
| Finished | Oct 12 02:18:21 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040899961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3040899961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/266.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/267.edn_genbits.41526256 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 34611823 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:18:12 PM UTC 24 |
| Finished | Oct 12 02:18:21 PM UTC 24 |
| Peak memory | 232112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41526256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 267.edn_genbits.41526256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/267.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/268.edn_genbits.2446698406 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 38595680 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:18:12 PM UTC 24 |
| Finished | Oct 12 02:18:22 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446698406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2446698406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/268.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_alert.3569307945 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 113418658 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569307945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.edn_alert.3569307945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_alert_test.2425645845 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 22601308 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425645845 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2425645845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_disable.4272541261 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 11265792 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:38 PM UTC 24 |
| Peak memory | 228040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272541261 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4272541261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1295328350 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 63776874 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295328350 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1295328350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_err.3545286697 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 26003046 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545286697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 27.edn_err.3545286697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_genbits.2584259694 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 49511488 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:34 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584259694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2584259694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_intr.433025395 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 19505343 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433025395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.433025395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_smoke.556164089 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 21527004 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 02:15:33 PM UTC 24 |
| Finished | Oct 12 02:15:36 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556164089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 27.edn_smoke.556164089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_stress_all.4216876090 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1047361656 ps |
| CPU time | 6.42 seconds |
| Started | Oct 12 02:15:34 PM UTC 24 |
| Finished | Oct 12 02:15:42 PM UTC 24 |
| Peak memory | 229080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216876090 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4216876090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.923610391 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 10111837873 ps |
| CPU time | 65.86 seconds |
| Started | Oct 12 02:15:34 PM UTC 24 |
| Finished | Oct 12 02:16:42 PM UTC 24 |
| Peak memory | 231424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923610391 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_ with_rand_reset.923610391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/278.edn_genbits.3042412428 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 30944114 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:18:13 PM UTC 24 |
| Finished | Oct 12 02:18:44 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042412428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3042412428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/278.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/279.edn_genbits.1662164941 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 48575629 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:18:13 PM UTC 24 |
| Finished | Oct 12 02:18:44 PM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662164941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1662164941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/279.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_alert.1902974645 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 123700489 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:15:36 PM UTC 24 |
| Finished | Oct 12 02:15:39 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902974645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.edn_alert.1902974645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_alert_test.2746337002 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 34667731 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:15:37 PM UTC 24 |
| Finished | Oct 12 02:15:40 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746337002 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2746337002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_disable.484427260 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 33948470 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:37 PM UTC 24 |
| Finished | Oct 12 02:15:40 PM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484427260 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.484427260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.2791052554 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 248487541 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:15:37 PM UTC 24 |
| Finished | Oct 12 02:15:40 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791052554 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2791052554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_err.2238617233 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 30228582 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 02:15:36 PM UTC 24 |
| Finished | Oct 12 02:15:39 PM UTC 24 |
| Peak memory | 244144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238617233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 28.edn_err.2238617233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_genbits.1774995025 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 38102052 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:15:36 PM UTC 24 |
| Finished | Oct 12 02:15:39 PM UTC 24 |
| Peak memory | 231284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774995025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1774995025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_smoke.475909946 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 18681924 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:15:35 PM UTC 24 |
| Finished | Oct 12 02:15:37 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475909946 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 28.edn_smoke.475909946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_stress_all.2147260825 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 339642035 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 02:15:36 PM UTC 24 |
| Finished | Oct 12 02:15:40 PM UTC 24 |
| Peak memory | 229040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147260825 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2147260825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.1523652242 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 12578903578 ps |
| CPU time | 84.15 seconds |
| Started | Oct 12 02:15:36 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523652242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all _with_rand_reset.1523652242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/280.edn_genbits.4275958372 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 82175621 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:44 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275958372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4275958372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/280.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/281.edn_genbits.709379816 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 79294521 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:44 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709379816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 281.edn_genbits.709379816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/281.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/282.edn_genbits.3440928098 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 66587919 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:32 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440928098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3440928098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/282.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/283.edn_genbits.889189932 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 27653820 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:44 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889189932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 283.edn_genbits.889189932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/283.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/284.edn_genbits.1515704350 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 47139260 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:36 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515704350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1515704350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/284.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/286.edn_genbits.2549618274 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 38391069 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:36 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549618274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2549618274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/286.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/287.edn_genbits.1234113336 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 28913043 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:36 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234113336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1234113336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/287.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/288.edn_genbits.3718462540 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 40617805 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:36 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718462540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3718462540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/288.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/289.edn_genbits.496993856 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 156687948 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:36 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496993856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 289.edn_genbits.496993856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/289.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_alert.314692418 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 83101678 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:15:39 PM UTC 24 |
| Finished | Oct 12 02:15:41 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314692418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 29.edn_alert.314692418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_alert_test.2426553073 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 30010046 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426553073 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2426553073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_disable.4113056293 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 15594493 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113056293 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4113056293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.3330540047 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 39046989 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330540047 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.3330540047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_genbits.2698252221 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 69246728 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 02:15:39 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 233072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698252221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2698252221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_smoke.755101407 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 17091052 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:15:38 PM UTC 24 |
| Finished | Oct 12 02:15:41 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755101407 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 29.edn_smoke.755101407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/29.edn_stress_all.3472494764 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 344971357 ps |
| CPU time | 6.6 seconds |
| Started | Oct 12 02:15:39 PM UTC 24 |
| Finished | Oct 12 02:15:46 PM UTC 24 |
| Peak memory | 229316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472494764 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3472494764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/29.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/290.edn_genbits.1387139003 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 223605996 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:37 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387139003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1387139003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/290.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/291.edn_genbits.1431377077 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 257651560 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:39 PM UTC 24 |
| Peak memory | 233148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431377077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1431377077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/291.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/292.edn_genbits.48418021 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 78505227 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:43 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48418021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 292.edn_genbits.48418021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/292.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/293.edn_genbits.3585816734 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 58671227 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:43 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585816734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3585816734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/293.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/294.edn_genbits.3321975040 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 45777717 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:18:14 PM UTC 24 |
| Finished | Oct 12 02:18:26 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321975040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3321975040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/294.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/295.edn_genbits.1012701877 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 183697650 ps |
| CPU time | 5 seconds |
| Started | Oct 12 02:18:15 PM UTC 24 |
| Finished | Oct 12 02:18:55 PM UTC 24 |
| Peak memory | 233132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012701877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1012701877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/295.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/296.edn_genbits.4088854625 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 67227535 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:18:17 PM UTC 24 |
| Finished | Oct 12 02:18:32 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088854625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4088854625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/296.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/297.edn_genbits.1510068040 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 39851041 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:18:20 PM UTC 24 |
| Finished | Oct 12 02:18:32 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510068040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1510068040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/297.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/298.edn_genbits.2673490812 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 45853831 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:18:22 PM UTC 24 |
| Finished | Oct 12 02:18:32 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673490812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2673490812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/298.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/299.edn_genbits.3545087675 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 38909930 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:18:22 PM UTC 24 |
| Finished | Oct 12 02:18:32 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545087675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3545087675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/299.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_alert.3270104322 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 31420903 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:14:45 PM UTC 24 |
| Finished | Oct 12 02:14:48 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270104322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_alert.3270104322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_alert_test.1314663221 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 141672879 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:49 PM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314663221 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1314663221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_disable.1758493965 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28070419 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:14:46 PM UTC 24 |
| Finished | Oct 12 02:14:48 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758493965 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1758493965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.819711105 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 21675601 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:14:46 PM UTC 24 |
| Finished | Oct 12 02:14:48 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819711105 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.819711105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_err.1274669894 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 41367136 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:14:46 PM UTC 24 |
| Finished | Oct 12 02:14:48 PM UTC 24 |
| Peak memory | 230272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274669894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.edn_err.1274669894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_intr.3187573320 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 22566654 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:14:45 PM UTC 24 |
| Finished | Oct 12 02:14:48 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187573320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3187573320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_regwen.509758716 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 65222242 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509758716 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_regwen.509758716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_smoke.2286239283 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 170827891 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 02:14:44 PM UTC 24 |
| Finished | Oct 12 02:14:46 PM UTC 24 |
| Peak memory | 227724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286239283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_smoke.2286239283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_stress_all.2040187186 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 128731258 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 02:14:45 PM UTC 24 |
| Finished | Oct 12 02:14:49 PM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040187186 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2040187186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.3139937335 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1808469294 ps |
| CPU time | 46.24 seconds |
| Started | Oct 12 02:14:45 PM UTC 24 |
| Finished | Oct 12 02:15:33 PM UTC 24 |
| Peak memory | 233392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139937335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_ with_rand_reset.3139937335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_alert.2373158180 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 30502084 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:15:41 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 227964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373158180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.edn_alert.2373158180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_alert_test.3199051770 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 17946786 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 02:15:42 PM UTC 24 |
| Finished | Oct 12 02:15:44 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199051770 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3199051770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_disable.2528720121 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 33031684 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:42 PM UTC 24 |
| Finished | Oct 12 02:15:44 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528720121 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2528720121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.3046913264 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 272220749 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:15:42 PM UTC 24 |
| Finished | Oct 12 02:15:45 PM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046913264 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.3046913264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_err.791588596 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 31985928 ps |
| CPU time | 1 seconds |
| Started | Oct 12 02:15:41 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791588596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 30.edn_err.791588596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_genbits.4187586442 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 61231154 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187586442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4187586442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_intr.3422023711 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 21029763 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:15:41 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422023711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3422023711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_smoke.2065573568 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 46731824 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065573568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.edn_smoke.2065573568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_stress_all.263275456 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 684724603 ps |
| CPU time | 4.02 seconds |
| Started | Oct 12 02:15:40 PM UTC 24 |
| Finished | Oct 12 02:15:45 PM UTC 24 |
| Peak memory | 229036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263275456 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.263275456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.3759313591 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3389463028 ps |
| CPU time | 82.19 seconds |
| Started | Oct 12 02:15:41 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759313591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all _with_rand_reset.3759313591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_alert.3477681891 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 86379346 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477681891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_alert.3477681891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_alert_test.3279183975 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 17342189 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279183975 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3279183975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_disable.2476654536 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 13772513 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476654536 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2476654536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.496420856 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 168575494 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496420856 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.496420856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_err.338055682 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 28339497 ps |
| CPU time | 1.81 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:48 PM UTC 24 |
| Peak memory | 231920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338055682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 31.edn_err.338055682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_genbits.2328621391 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 36396713 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 02:15:43 PM UTC 24 |
| Finished | Oct 12 02:15:46 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328621391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2328621391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_intr.1740121677 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 36055367 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:43 PM UTC 24 |
| Finished | Oct 12 02:15:46 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740121677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1740121677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_smoke.3896658948 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 28025889 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:15:43 PM UTC 24 |
| Finished | Oct 12 02:15:45 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896658948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_smoke.3896658948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_stress_all.802519317 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 190038301 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:15:43 PM UTC 24 |
| Finished | Oct 12 02:15:46 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802519317 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.802519317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.1113082052 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 169914444 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 02:15:43 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 229100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113082052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all _with_rand_reset.1113082052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_alert.1261133701 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 46911378 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:15:46 PM UTC 24 |
| Finished | Oct 12 02:15:49 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261133701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_alert.1261133701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_alert_test.2849255760 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 31182837 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 02:15:46 PM UTC 24 |
| Finished | Oct 12 02:15:49 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849255760 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2849255760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_disable.619104555 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 43855823 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:15:46 PM UTC 24 |
| Finished | Oct 12 02:15:49 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619104555 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.619104555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.147097595 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 75216945 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:15:46 PM UTC 24 |
| Finished | Oct 12 02:15:49 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147097595 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.147097595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_err.1162341855 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 29709921 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:15:46 PM UTC 24 |
| Finished | Oct 12 02:15:49 PM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162341855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 32.edn_err.1162341855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_genbits.193252759 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 18386125 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193252759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.edn_genbits.193252759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_intr.3985987542 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 24801251 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:48 PM UTC 24 |
| Peak memory | 238508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985987542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3985987542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_smoke.1617796857 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 20803971 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:47 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617796857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_smoke.1617796857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_stress_all.411720503 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 59697681 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:15:48 PM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411720503 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.411720503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.409349648 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 42430080269 ps |
| CPU time | 106.61 seconds |
| Started | Oct 12 02:15:45 PM UTC 24 |
| Finished | Oct 12 02:17:34 PM UTC 24 |
| Peak memory | 231404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409349648 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_ with_rand_reset.409349648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_alert.3193252808 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 103257219 ps |
| CPU time | 1.8 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:52 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193252808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_alert.3193252808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_alert_test.4103858629 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 26005121 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:51 PM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103858629 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4103858629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_disable.2428212564 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 15568560 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:51 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428212564 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2428212564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.3448460664 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 110208329 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:51 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448460664 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.3448460664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_err.2910719340 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 20185504 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:51 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910719340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 33.edn_err.2910719340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_genbits.1844979815 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 82175798 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:15:48 PM UTC 24 |
| Finished | Oct 12 02:15:50 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844979815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1844979815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_intr.1123570488 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 27000093 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:15:48 PM UTC 24 |
| Finished | Oct 12 02:15:50 PM UTC 24 |
| Peak memory | 238688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123570488 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1123570488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_smoke.2406825442 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 58941578 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:15:48 PM UTC 24 |
| Finished | Oct 12 02:15:50 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406825442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_smoke.2406825442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_stress_all.2937655793 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 671162290 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 02:15:48 PM UTC 24 |
| Finished | Oct 12 02:15:51 PM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937655793 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2937655793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.1471522234 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1975324612 ps |
| CPU time | 51.86 seconds |
| Started | Oct 12 02:15:48 PM UTC 24 |
| Finished | Oct 12 02:16:41 PM UTC 24 |
| Peak memory | 231192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471522234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all _with_rand_reset.1471522234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_alert.231777457 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 97835429 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:15:50 PM UTC 24 |
| Finished | Oct 12 02:15:53 PM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231777457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 34.edn_alert.231777457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_alert_test.1787059322 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 13806020 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:15:51 PM UTC 24 |
| Finished | Oct 12 02:15:53 PM UTC 24 |
| Peak memory | 218300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787059322 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1787059322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_disable.2901722675 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 37756212 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:15:50 PM UTC 24 |
| Finished | Oct 12 02:15:53 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901722675 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2901722675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.2232070658 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 57121748 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:15:51 PM UTC 24 |
| Finished | Oct 12 02:15:53 PM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232070658 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.2232070658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_err.1775261403 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 20563767 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:50 PM UTC 24 |
| Finished | Oct 12 02:15:53 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775261403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 34.edn_err.1775261403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_genbits.1212709887 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 129437613 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:52 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212709887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1212709887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_intr.1755379007 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 26955799 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:15:50 PM UTC 24 |
| Finished | Oct 12 02:15:53 PM UTC 24 |
| Peak memory | 238688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755379007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1755379007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_smoke.2383973515 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 17321752 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:15:49 PM UTC 24 |
| Finished | Oct 12 02:15:51 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383973515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_smoke.2383973515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/34.edn_stress_all.1368152378 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 134104343 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 02:15:50 PM UTC 24 |
| Finished | Oct 12 02:15:55 PM UTC 24 |
| Peak memory | 231204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368152378 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1368152378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/34.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_alert_test.3932541218 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 12014802 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:15:53 PM UTC 24 |
| Finished | Oct 12 02:15:55 PM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932541218 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3932541218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.629795964 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 62154155 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:15:53 PM UTC 24 |
| Finished | Oct 12 02:15:56 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629795964 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.629795964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_err.2558484480 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 42822683 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:15:53 PM UTC 24 |
| Finished | Oct 12 02:15:55 PM UTC 24 |
| Peak memory | 238248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558484480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 35.edn_err.2558484480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_genbits.2835394675 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 220430657 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:15:52 PM UTC 24 |
| Finished | Oct 12 02:15:54 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835394675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2835394675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_intr.4122824370 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 20517679 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:15:52 PM UTC 24 |
| Finished | Oct 12 02:15:54 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122824370 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4122824370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_smoke.3477321129 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 15895599 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:15:52 PM UTC 24 |
| Finished | Oct 12 02:15:54 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477321129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.edn_smoke.3477321129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_stress_all.1751319442 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 179725004 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 02:15:52 PM UTC 24 |
| Finished | Oct 12 02:15:58 PM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751319442 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1751319442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.61347423 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3052551553 ps |
| CPU time | 68.15 seconds |
| Started | Oct 12 02:15:52 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 233596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61347423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_w ith_rand_reset.61347423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_alert.2818981170 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 44873109 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:15:55 PM UTC 24 |
| Finished | Oct 12 02:15:57 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818981170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.edn_alert.2818981170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_alert_test.2952459326 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 51485338 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:15:56 PM UTC 24 |
| Finished | Oct 12 02:15:58 PM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952459326 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2952459326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_disable.2157945482 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 21074558 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:15:56 PM UTC 24 |
| Finished | Oct 12 02:15:58 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157945482 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2157945482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.222199237 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 29488812 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 02:15:56 PM UTC 24 |
| Finished | Oct 12 02:15:58 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222199237 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.222199237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_err.2252611408 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 28431971 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:15:56 PM UTC 24 |
| Finished | Oct 12 02:15:58 PM UTC 24 |
| Peak memory | 245568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252611408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 36.edn_err.2252611408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_genbits.1039193878 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 142019988 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:15:54 PM UTC 24 |
| Finished | Oct 12 02:15:57 PM UTC 24 |
| Peak memory | 233128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039193878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1039193878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_intr.2730028412 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 70344022 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:15:55 PM UTC 24 |
| Finished | Oct 12 02:15:57 PM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730028412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2730028412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_smoke.4032642703 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 24027431 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:15:53 PM UTC 24 |
| Finished | Oct 12 02:15:56 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032642703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.edn_smoke.4032642703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/36.edn_stress_all.390842158 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 753980166 ps |
| CPU time | 4.99 seconds |
| Started | Oct 12 02:15:54 PM UTC 24 |
| Finished | Oct 12 02:16:00 PM UTC 24 |
| Peak memory | 229036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390842158 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.390842158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/36.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_alert_test.636593341 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 19957193 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:15:58 PM UTC 24 |
| Finished | Oct 12 02:16:01 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636593341 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.636593341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_disable.2863064199 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 16563057 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:15:58 PM UTC 24 |
| Finished | Oct 12 02:16:00 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863064199 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2863064199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.3962368817 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 31759315 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:15:58 PM UTC 24 |
| Finished | Oct 12 02:16:01 PM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962368817 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.3962368817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_err.4277846904 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 91817073 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:15:58 PM UTC 24 |
| Finished | Oct 12 02:16:00 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277846904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 37.edn_err.4277846904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_intr.1081720027 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 28760910 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:15:57 PM UTC 24 |
| Finished | Oct 12 02:16:00 PM UTC 24 |
| Peak memory | 238688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081720027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1081720027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_smoke.348620654 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 16334959 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:15:56 PM UTC 24 |
| Finished | Oct 12 02:15:58 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348620654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 37.edn_smoke.348620654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_stress_all.648463673 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 249190402 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 02:15:57 PM UTC 24 |
| Finished | Oct 12 02:16:01 PM UTC 24 |
| Peak memory | 229408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648463673 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.648463673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.2519893492 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1647124771 ps |
| CPU time | 43.34 seconds |
| Started | Oct 12 02:15:57 PM UTC 24 |
| Finished | Oct 12 02:16:42 PM UTC 24 |
| Peak memory | 233312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519893492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all _with_rand_reset.2519893492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_alert.2938936335 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 105144801 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:16:01 PM UTC 24 |
| Finished | Oct 12 02:16:03 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938936335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_alert.2938936335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_alert_test.1704927697 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 14467010 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:16:02 PM UTC 24 |
| Finished | Oct 12 02:16:05 PM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704927697 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1704927697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_disable.4278108370 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 12512949 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:16:01 PM UTC 24 |
| Finished | Oct 12 02:16:03 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278108370 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4278108370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.2055700756 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 65263983 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:16:01 PM UTC 24 |
| Finished | Oct 12 02:16:04 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055700756 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.2055700756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_err.1279178508 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 32672339 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:16:01 PM UTC 24 |
| Finished | Oct 12 02:16:03 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279178508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 38.edn_err.1279178508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_genbits.4067597939 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 101918309 ps |
| CPU time | 3.2 seconds |
| Started | Oct 12 02:16:00 PM UTC 24 |
| Finished | Oct 12 02:16:04 PM UTC 24 |
| Peak memory | 231080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067597939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4067597939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_intr.2553810381 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 48972615 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:16:01 PM UTC 24 |
| Finished | Oct 12 02:16:03 PM UTC 24 |
| Peak memory | 238312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553810381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2553810381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_smoke.2750941147 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 28271511 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:00 PM UTC 24 |
| Finished | Oct 12 02:16:02 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750941147 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_smoke.2750941147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_stress_all.3214554333 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 349584948 ps |
| CPU time | 4.77 seconds |
| Started | Oct 12 02:16:00 PM UTC 24 |
| Finished | Oct 12 02:16:06 PM UTC 24 |
| Peak memory | 231056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214554333 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3214554333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.2988742287 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 27677430015 ps |
| CPU time | 109.43 seconds |
| Started | Oct 12 02:16:00 PM UTC 24 |
| Finished | Oct 12 02:17:51 PM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988742287 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all _with_rand_reset.2988742287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_alert.1131662061 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 107674862 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 02:16:05 PM UTC 24 |
| Finished | Oct 12 02:16:07 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131662061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_alert.1131662061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_alert_test.3344395170 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 33492239 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:16:05 PM UTC 24 |
| Finished | Oct 12 02:16:07 PM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344395170 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3344395170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_disable.1793544474 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 18247799 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:16:05 PM UTC 24 |
| Finished | Oct 12 02:16:07 PM UTC 24 |
| Peak memory | 228096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793544474 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1793544474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.774590278 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 91902286 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 02:16:05 PM UTC 24 |
| Finished | Oct 12 02:16:07 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774590278 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.774590278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_err.1277893218 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 69843939 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:16:05 PM UTC 24 |
| Finished | Oct 12 02:16:07 PM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277893218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 39.edn_err.1277893218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_genbits.1710373381 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 78273513 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:16:02 PM UTC 24 |
| Finished | Oct 12 02:16:05 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710373381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1710373381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_intr.1482865212 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 22535245 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:16:03 PM UTC 24 |
| Finished | Oct 12 02:16:06 PM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482865212 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1482865212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_smoke.3560340249 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 32133611 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:16:02 PM UTC 24 |
| Finished | Oct 12 02:16:05 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560340249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_smoke.3560340249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_stress_all.2652537815 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1238769249 ps |
| CPU time | 4.71 seconds |
| Started | Oct 12 02:16:02 PM UTC 24 |
| Finished | Oct 12 02:16:08 PM UTC 24 |
| Peak memory | 229052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652537815 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2652537815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.4076321521 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 8235159064 ps |
| CPU time | 102.57 seconds |
| Started | Oct 12 02:16:02 PM UTC 24 |
| Finished | Oct 12 02:17:47 PM UTC 24 |
| Peak memory | 233376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076321521 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all _with_rand_reset.4076321521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_alert.1334730125 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 50871363 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:50 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334730125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_alert.1334730125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_alert_test.1509302490 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 19992340 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:14:49 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509302490 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1509302490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_disable.2005274066 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11392468 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:14:49 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005274066 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2005274066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.3995230854 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 39506124 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:14:49 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995230854 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.3995230854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_err.3044179959 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 84676067 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:50 PM UTC 24 |
| Peak memory | 245948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044179959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.edn_err.3044179959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_genbits.3671744954 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 77245162 ps |
| CPU time | 2.15 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:50 PM UTC 24 |
| Peak memory | 231096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671744954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3671744954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_intr.3285373680 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 60303845 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:50 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285373680 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3285373680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_regwen.298114563 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 26691321 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:50 PM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298114563 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_regwen.298114563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_sec_cm.2772009450 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4760480401 ps |
| CPU time | 7.07 seconds |
| Started | Oct 12 02:14:49 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 261804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772009450 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2772009450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_smoke.2546002691 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 43709819 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:50 PM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546002691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_smoke.2546002691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_stress_all.3151515297 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 141863704 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 233076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151515297 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3151515297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.3525845040 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4544376233 ps |
| CPU time | 54 seconds |
| Started | Oct 12 02:14:47 PM UTC 24 |
| Finished | Oct 12 02:15:43 PM UTC 24 |
| Peak memory | 233716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525845040 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_ with_rand_reset.3525845040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_alert.9222220 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 44890324 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:16:06 PM UTC 24 |
| Finished | Oct 12 02:16:09 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9222220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.9222220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_alert_test.3004898300 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 15818796 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:16:09 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004898300 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3004898300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_disable.643193284 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 12249018 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:16:07 PM UTC 24 |
| Finished | Oct 12 02:16:09 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643193284 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.643193284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.1367985903 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 42084151 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:16:07 PM UTC 24 |
| Finished | Oct 12 02:16:10 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367985903 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.1367985903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_err.4231191315 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 44348383 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:16:07 PM UTC 24 |
| Finished | Oct 12 02:16:10 PM UTC 24 |
| Peak memory | 244220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231191315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 40.edn_err.4231191315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_genbits.1917466606 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 92208565 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 02:16:06 PM UTC 24 |
| Finished | Oct 12 02:16:09 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917466606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1917466606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_intr.84847568 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 27602113 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:16:06 PM UTC 24 |
| Finished | Oct 12 02:16:09 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84847568 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 40.edn_intr.84847568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_smoke.2001379936 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 18592677 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:16:05 PM UTC 24 |
| Finished | Oct 12 02:16:07 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001379936 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.edn_smoke.2001379936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_stress_all.4074771355 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 928804067 ps |
| CPU time | 4.91 seconds |
| Started | Oct 12 02:16:06 PM UTC 24 |
| Finished | Oct 12 02:16:12 PM UTC 24 |
| Peak memory | 229316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074771355 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4074771355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.1363209724 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 21057956818 ps |
| CPU time | 103.56 seconds |
| Started | Oct 12 02:16:06 PM UTC 24 |
| Finished | Oct 12 02:17:52 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363209724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all _with_rand_reset.1363209724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_alert.766060435 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 26165274 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:16:10 PM UTC 24 |
| Finished | Oct 12 02:16:13 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766060435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 41.edn_alert.766060435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_alert_test.3821553833 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 15454805 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:16:11 PM UTC 24 |
| Finished | Oct 12 02:16:13 PM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821553833 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3821553833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.1912619697 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 62692001 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:16:10 PM UTC 24 |
| Finished | Oct 12 02:16:13 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912619697 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.1912619697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_err.894635783 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 30157146 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:16:10 PM UTC 24 |
| Finished | Oct 12 02:16:13 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894635783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 41.edn_err.894635783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_genbits.2583507501 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 130532577 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 02:16:09 PM UTC 24 |
| Finished | Oct 12 02:16:12 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583507501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2583507501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_intr.4022897374 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 32285757 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:16:09 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022897374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4022897374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_smoke.417088218 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 60711760 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:16:09 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417088218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 41.edn_smoke.417088218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/41.edn_stress_all.1698116732 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 429205844 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:16:09 PM UTC 24 |
| Finished | Oct 12 02:16:11 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698116732 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1698116732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/41.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_alert.2446546046 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 55969813 ps |
| CPU time | 2 seconds |
| Started | Oct 12 02:16:12 PM UTC 24 |
| Finished | Oct 12 02:16:23 PM UTC 24 |
| Peak memory | 234128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446546046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_alert.2446546046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_alert_test.1624564898 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 26258051 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:17 PM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624564898 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1624564898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_disable.1448279900 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 26753913 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:17 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448279900 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1448279900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.3847534542 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 382510137 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:17 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847534542 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.3847534542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_err.2865974790 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 102333589 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:16:12 PM UTC 24 |
| Finished | Oct 12 02:16:22 PM UTC 24 |
| Peak memory | 248012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865974790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 42.edn_err.2865974790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_genbits.3235981808 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 39520309 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 02:16:12 PM UTC 24 |
| Finished | Oct 12 02:16:22 PM UTC 24 |
| Peak memory | 233576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235981808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3235981808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_intr.3120122855 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 22532684 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:12 PM UTC 24 |
| Finished | Oct 12 02:16:22 PM UTC 24 |
| Peak memory | 230036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120122855 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3120122855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_smoke.2048381804 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 22581988 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:16:11 PM UTC 24 |
| Finished | Oct 12 02:16:13 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048381804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_smoke.2048381804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_stress_all.1753867265 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 239733300 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 02:16:12 PM UTC 24 |
| Finished | Oct 12 02:16:24 PM UTC 24 |
| Peak memory | 229056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753867265 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1753867265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.3529333545 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1095211254 ps |
| CPU time | 8.16 seconds |
| Started | Oct 12 02:16:12 PM UTC 24 |
| Finished | Oct 12 02:16:29 PM UTC 24 |
| Peak memory | 231160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529333545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all _with_rand_reset.3529333545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_alert.3603207313 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 71836320 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:16:14 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603207313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.edn_alert.3603207313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_alert_test.3989154079 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 16935883 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:16:18 PM UTC 24 |
| Finished | Oct 12 02:16:22 PM UTC 24 |
| Peak memory | 217808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989154079 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3989154079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_disable.3317665444 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 12468339 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:16:17 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317665444 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3317665444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.4124552548 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 64555532 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:16:18 PM UTC 24 |
| Finished | Oct 12 02:16:22 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124552548 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.4124552548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_err.1981709423 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 34482459 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:16:14 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981709423 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 43.edn_err.1981709423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_genbits.3844486675 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 56985766 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:18 PM UTC 24 |
| Peak memory | 231024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844486675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3844486675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_intr.3684076006 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 27934226 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:17 PM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684076006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3684076006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_smoke.959194357 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 43558342 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:17 PM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959194357 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 43.edn_smoke.959194357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/43.edn_stress_all.1012776924 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 632762406 ps |
| CPU time | 3.32 seconds |
| Started | Oct 12 02:16:13 PM UTC 24 |
| Finished | Oct 12 02:16:29 PM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012776924 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1012776924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/43.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_alert.3326871479 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 24940704 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 02:16:22 PM UTC 24 |
| Finished | Oct 12 02:16:40 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326871479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.edn_alert.3326871479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_alert_test.8732616 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 36881406 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:16:24 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8732616 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.8732616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_disable.1773295672 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 26373804 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:16:24 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773295672 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1773295672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.1801841900 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 75676062 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 02:16:24 PM UTC 24 |
| Finished | Oct 12 02:16:28 PM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801841900 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.1801841900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_err.2295792444 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 22993240 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:16:24 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295792444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 44.edn_err.2295792444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_genbits.3030838374 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 89287221 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:16:18 PM UTC 24 |
| Finished | Oct 12 02:16:39 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030838374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3030838374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_intr.1536630646 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 26522929 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:16:22 PM UTC 24 |
| Finished | Oct 12 02:16:32 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536630646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1536630646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_smoke.4149036403 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 53866552 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:16:18 PM UTC 24 |
| Finished | Oct 12 02:16:22 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149036403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.edn_smoke.4149036403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/44.edn_stress_all.1041687815 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 853433508 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 02:16:18 PM UTC 24 |
| Finished | Oct 12 02:16:23 PM UTC 24 |
| Peak memory | 233136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041687815 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1041687815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/44.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_alert.1737740723 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 82685342 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:32 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737740723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.edn_alert.1737740723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_alert_test.1523585898 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 57055087 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:39 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523585898 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1523585898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_disable.3100424449 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 89268891 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:32 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100424449 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3100424449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.2558802813 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 164903644 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:32 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558802813 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.2558802813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_err.339980279 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 23901482 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:32 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339980279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 45.edn_err.339980279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_genbits.11064086 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 34971013 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:16:25 PM UTC 24 |
| Finished | Oct 12 02:16:28 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11064086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 45.edn_genbits.11064086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_intr.153349669 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 39825654 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:31 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153349669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.153349669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_smoke.2182773612 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 27914674 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:16:24 PM UTC 24 |
| Finished | Oct 12 02:16:27 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182773612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.edn_smoke.2182773612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_stress_all.2360747643 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 316779788 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 02:16:25 PM UTC 24 |
| Finished | Oct 12 02:16:29 PM UTC 24 |
| Peak memory | 228960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360747643 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2360747643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.1974575136 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1552228516 ps |
| CPU time | 17.35 seconds |
| Started | Oct 12 02:16:28 PM UTC 24 |
| Finished | Oct 12 02:16:48 PM UTC 24 |
| Peak memory | 231240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974575136 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all _with_rand_reset.1974575136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_alert_test.2196371275 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 39953583 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 02:16:32 PM UTC 24 |
| Finished | Oct 12 02:16:38 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196371275 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2196371275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_disable.3791294304 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 32221523 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:16:32 PM UTC 24 |
| Finished | Oct 12 02:16:38 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791294304 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3791294304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.1935867538 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 56334335 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 02:16:32 PM UTC 24 |
| Finished | Oct 12 02:16:39 PM UTC 24 |
| Peak memory | 231360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935867538 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.1935867538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_err.2064380470 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 18376412 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:31 PM UTC 24 |
| Finished | Oct 12 02:16:37 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064380470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 46.edn_err.2064380470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_intr.2369255084 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 35474860 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:16:30 PM UTC 24 |
| Finished | Oct 12 02:16:39 PM UTC 24 |
| Peak memory | 227928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369255084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2369255084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_smoke.2768443781 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 16198146 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:16:30 PM UTC 24 |
| Finished | Oct 12 02:16:39 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768443781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_smoke.2768443781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/46.edn_stress_all.2274702663 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 359985120 ps |
| CPU time | 3.18 seconds |
| Started | Oct 12 02:16:30 PM UTC 24 |
| Finished | Oct 12 02:16:41 PM UTC 24 |
| Peak memory | 231088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274702663 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2274702663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/46.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_alert.2993405666 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 201515659 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:16:40 PM UTC 24 |
| Finished | Oct 12 02:16:43 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993405666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_alert.2993405666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_alert_test.3953685226 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 17823253 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:16:41 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 228552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953685226 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3953685226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_disable.4210563386 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 12310431 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:16:41 PM UTC 24 |
| Finished | Oct 12 02:16:43 PM UTC 24 |
| Peak memory | 227976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210563386 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4210563386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.3949846006 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 97199416 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:16:41 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949846006 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.3949846006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_err.1377867856 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 23191986 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:16:41 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377867856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 47.edn_err.1377867856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_genbits.1902912738 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 52662317 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:16:33 PM UTC 24 |
| Finished | Oct 12 02:16:37 PM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902912738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1902912738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_intr.240740263 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 28748392 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:16:40 PM UTC 24 |
| Finished | Oct 12 02:16:42 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240740263 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.240740263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_smoke.3139908255 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 47576258 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:16:33 PM UTC 24 |
| Finished | Oct 12 02:16:37 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139908255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_smoke.3139908255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/47.edn_stress_all.89172515 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 165327054 ps |
| CPU time | 4.86 seconds |
| Started | Oct 12 02:16:34 PM UTC 24 |
| Finished | Oct 12 02:16:41 PM UTC 24 |
| Peak memory | 229004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89172515 -assert nopostproc +UVM_TESTNAME=edn_s tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.89172515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/47.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_alert.3566728364 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 28540644 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:45 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566728364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.edn_alert.3566728364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_alert_test.72091359 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 18199884 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72091359 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.72091359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_disable.3667879887 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 13427931 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 227920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667879887 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3667879887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.158754188 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 221346660 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158754188 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.158754188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_err.3027858384 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 47232230 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027858384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 48.edn_err.3027858384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_genbits.2019967899 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 68985496 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:45 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019967899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2019967899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_intr.3796843391 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 43258398 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796843391 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3796843391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_smoke.3490156167 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 18585417 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:44 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490156167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.edn_smoke.3490156167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_stress_all.2720841323 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 667643088 ps |
| CPU time | 5.26 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:16:48 PM UTC 24 |
| Peak memory | 229060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720841323 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2720841323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.279395811 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 16606753324 ps |
| CPU time | 85.97 seconds |
| Started | Oct 12 02:16:42 PM UTC 24 |
| Finished | Oct 12 02:18:09 PM UTC 24 |
| Peak memory | 231228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279395811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_ with_rand_reset.279395811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_alert.3005407559 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 25738841 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:47 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005407559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_alert.3005407559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_alert_test.3104981854 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 77315218 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:49 PM UTC 24 |
| Peak memory | 217852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104981854 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3104981854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_disable.730496330 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 39402612 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:47 PM UTC 24 |
| Peak memory | 227916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730496330 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.730496330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.2741318087 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 27904853 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:49 PM UTC 24 |
| Peak memory | 230208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741318087 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.2741318087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_err.4079147406 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 37772789 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:47 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079147406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 49.edn_err.4079147406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_genbits.4176138522 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 192897187 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:47 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176138522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4176138522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_intr.2321640097 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 20882483 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:47 PM UTC 24 |
| Peak memory | 227988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321640097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2321640097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_smoke.299888087 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 76514513 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:46 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299888087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 49.edn_smoke.299888087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/49.edn_stress_all.1385403993 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 86663989 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:16:44 PM UTC 24 |
| Finished | Oct 12 02:16:47 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385403993 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1385403993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/49.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_alert.3449027515 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 47889939 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:53 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449027515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_alert.3449027515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_alert_test.4028463758 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 39140095 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:53 PM UTC 24 |
| Peak memory | 217856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028463758 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4028463758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_disable.1113164329 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 58463825 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:53 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113164329 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1113164329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_err.1329198783 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 24796485 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:52 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329198783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 5.edn_err.1329198783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_genbits.3559858452 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 54493390 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:53 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559858452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3559858452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_intr.935928553 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 24548108 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:53 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935928553 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.935928553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_regwen.1839282101 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 20851564 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:14:49 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839282101 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 5.edn_regwen.1839282101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_smoke.878890216 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 16849347 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:14:49 PM UTC 24 |
| Finished | Oct 12 02:14:51 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878890216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.edn_smoke.878890216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/5.edn_stress_all.3163991027 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 450108582 ps |
| CPU time | 8.36 seconds |
| Started | Oct 12 02:14:50 PM UTC 24 |
| Finished | Oct 12 02:14:59 PM UTC 24 |
| Peak memory | 229352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163991027 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3163991027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/5.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/50.edn_alert.3113845080 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 37612452 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:50 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113845080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 50.edn_alert.3113845080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/50.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/50.edn_err.3260388051 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 19494337 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:50 PM UTC 24 |
| Peak memory | 238564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260388051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 50.edn_err.3260388051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/50.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/50.edn_genbits.228647502 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 71896063 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:49 PM UTC 24 |
| Peak memory | 227848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228647502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 50.edn_genbits.228647502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/50.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/51.edn_alert.2563641585 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 46684542 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:50 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563641585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 51.edn_alert.2563641585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/51.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/51.edn_err.1154998061 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 21632607 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:50 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154998061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 51.edn_err.1154998061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/51.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/51.edn_genbits.413817693 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 64865692 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:49 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413817693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 51.edn_genbits.413817693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/51.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/52.edn_alert.3557878590 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 87679538 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:50 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557878590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 52.edn_alert.3557878590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/52.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/52.edn_err.1518545064 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 36445885 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:16:49 PM UTC 24 |
| Finished | Oct 12 02:16:52 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518545064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 52.edn_err.1518545064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/52.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/52.edn_genbits.1686503384 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 35212573 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:16:47 PM UTC 24 |
| Finished | Oct 12 02:16:50 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686503384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1686503384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/52.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/53.edn_alert.1255973467 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 36838974 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:52 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255973467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 53.edn_alert.1255973467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/53.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/53.edn_err.3156555173 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 33849573 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:52 PM UTC 24 |
| Peak memory | 238248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156555173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 53.edn_err.3156555173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/53.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/53.edn_genbits.4095021336 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 59741866 ps |
| CPU time | 2.38 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:53 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095021336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4095021336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/53.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/54.edn_alert.269679343 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 38421176 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:52 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269679343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 54.edn_alert.269679343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/54.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/54.edn_err.2350682092 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 32821740 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:52 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350682092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 54.edn_err.2350682092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/54.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/54.edn_genbits.3528837699 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 170923476 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:53 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528837699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3528837699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/54.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/55.edn_alert.838404117 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 26451261 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:53 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838404117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 55.edn_alert.838404117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/55.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/55.edn_err.1918023237 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 35494483 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:53 PM UTC 24 |
| Peak memory | 246264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918023237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 55.edn_err.1918023237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/55.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/55.edn_genbits.3856644778 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 44032237 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 02:16:50 PM UTC 24 |
| Finished | Oct 12 02:16:53 PM UTC 24 |
| Peak memory | 233180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856644778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3856644778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/55.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/56.edn_alert.3129538630 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 41406004 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129538630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 56.edn_alert.3129538630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/56.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/56.edn_err.2551371453 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 57809643 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:54 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551371453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 56.edn_err.2551371453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/56.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/56.edn_genbits.965647783 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 51377939 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:54 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965647783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 56.edn_genbits.965647783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/56.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/57.edn_alert.2676511983 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 47450023 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676511983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 57.edn_alert.2676511983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/57.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/57.edn_err.3492688265 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 72143261 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492688265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 57.edn_err.3492688265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/57.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/57.edn_genbits.753872776 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 32735304 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753872776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 57.edn_genbits.753872776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/57.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/58.edn_alert.460314259 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 29007774 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460314259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 58.edn_alert.460314259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/58.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/58.edn_err.3243174870 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 27452378 ps |
| CPU time | 1 seconds |
| Started | Oct 12 02:16:53 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243174870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 58.edn_err.3243174870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/58.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/58.edn_genbits.1097948732 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 33308947 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:16:52 PM UTC 24 |
| Finished | Oct 12 02:16:55 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097948732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1097948732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/58.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/59.edn_alert.62861544 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 34342713 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62861544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.62861544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/59.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/59.edn_err.1534631109 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 18236680 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534631109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 59.edn_err.1534631109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/59.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/59.edn_genbits.3975823494 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 77903966 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:58 PM UTC 24 |
| Peak memory | 231472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975823494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3975823494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/59.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_alert.1878429999 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 74380565 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:14:55 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878429999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_alert.1878429999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_alert_test.3406873170 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 31335251 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:14:53 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406873170 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3406873170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_disable.1359502631 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 22897764 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:14:53 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359502631 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1359502631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_err.2962121980 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 22995813 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 02:14:53 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 247848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962121980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 6.edn_err.2962121980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_intr.105314722 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 32586901 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:14:54 PM UTC 24 |
| Peak memory | 228044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105314722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.105314722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_regwen.2545943302 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 16904372 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:14:54 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545943302 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 6.edn_regwen.2545943302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/6.edn_smoke.661960182 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 21236315 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:14:52 PM UTC 24 |
| Finished | Oct 12 02:14:54 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661960182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.edn_smoke.661960182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/6.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/60.edn_alert.1069491543 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 24151955 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069491543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 60.edn_alert.1069491543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/60.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/60.edn_err.3745634724 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 28530905 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 238428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745634724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 60.edn_err.3745634724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/60.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/60.edn_genbits.3889558356 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 94170023 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 228076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889558356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3889558356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/60.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/61.edn_alert.3835000513 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 25193119 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835000513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 61.edn_alert.3835000513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/61.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/61.edn_err.1887143902 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 29714967 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887143902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 61.edn_err.1887143902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/61.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/61.edn_genbits.2567118822 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 44554352 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:58 PM UTC 24 |
| Peak memory | 233404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567118822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2567118822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/61.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/62.edn_alert.2986967936 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 37947183 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986967936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 62.edn_alert.2986967936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/62.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/62.edn_err.815373840 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 38531808 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815373840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 62.edn_err.815373840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/62.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/62.edn_genbits.419868116 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 76079872 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:16:55 PM UTC 24 |
| Finished | Oct 12 02:16:57 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419868116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 62.edn_genbits.419868116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/62.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/63.edn_alert.4116061216 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 46234400 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:16:57 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116061216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 63.edn_alert.4116061216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/63.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/63.edn_err.2538855823 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 100103759 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:16:57 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538855823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 63.edn_err.2538855823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/63.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/63.edn_genbits.3784583675 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 93944242 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:16:57 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784583675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3784583675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/63.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/64.edn_alert.3904920118 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 26028201 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:16:57 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904920118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 64.edn_alert.3904920118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/64.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/64.edn_err.2840981165 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 43945492 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:16:58 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840981165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 64.edn_err.2840981165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/64.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/64.edn_genbits.3797010909 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 35003097 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:16:57 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797010909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3797010909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/64.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/65.edn_alert.3986094841 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 42898227 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 02:16:58 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986094841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 65.edn_alert.3986094841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/65.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/65.edn_err.1251001919 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 19184476 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:16:58 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 238444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251001919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 65.edn_err.1251001919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/65.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/65.edn_genbits.1478844238 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 39485473 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 02:16:58 PM UTC 24 |
| Finished | Oct 12 02:17:00 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478844238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1478844238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/65.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/66.edn_alert.4099865247 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 64058117 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099865247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 66.edn_alert.4099865247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/66.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/66.edn_err.2976104760 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 19220710 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976104760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 66.edn_err.2976104760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/66.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/66.edn_genbits.4260453382 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 96131637 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260453382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4260453382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/66.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/67.edn_alert.1471738668 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 93193551 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:03 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471738668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 67.edn_alert.1471738668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/67.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/67.edn_err.180069831 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 48854054 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 248220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180069831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 67.edn_err.180069831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/67.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/67.edn_genbits.4145448851 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 44878690 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:03 PM UTC 24 |
| Peak memory | 231104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145448851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4145448851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/67.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/68.edn_alert.2047907139 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 32039442 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047907139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 68.edn_alert.2047907139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/68.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/68.edn_err.2147311048 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 73319987 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147311048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 68.edn_err.2147311048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/68.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/68.edn_genbits.3152425100 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 40866781 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:03 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152425100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3152425100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/68.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/69.edn_alert.584636787 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 77980891 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:02 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584636787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 69.edn_alert.584636787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/69.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/69.edn_err.3531264205 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 26545090 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 248228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531264205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 69.edn_err.3531264205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/69.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/69.edn_genbits.1401854176 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 53413412 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:17:00 PM UTC 24 |
| Finished | Oct 12 02:17:03 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401854176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1401854176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/69.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_alert.726964589 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 92693600 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 02:14:55 PM UTC 24 |
| Finished | Oct 12 02:14:58 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726964589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.edn_alert.726964589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_alert_test.125008418 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 31784140 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:14:55 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125008418 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.125008418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_disable.2697308283 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 18507148 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:14:55 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697308283 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2697308283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.3913172030 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 25917341 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:14:55 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913172030 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.3913172030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_err.2864013581 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 22569301 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:14:55 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864013581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 7.edn_err.2864013581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_genbits.4257959481 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 62064231 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 02:14:54 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257959481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4257959481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_regwen.332932908 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 36981155 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 02:14:54 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332932908 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_regwen.332932908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_smoke.2108063440 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 39588244 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:14:53 PM UTC 24 |
| Finished | Oct 12 02:14:56 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108063440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_smoke.2108063440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/7.edn_stress_all.2023317153 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 500322351 ps |
| CPU time | 2.87 seconds |
| Started | Oct 12 02:14:54 PM UTC 24 |
| Finished | Oct 12 02:14:58 PM UTC 24 |
| Peak memory | 231456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023317153 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2023317153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/7.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/70.edn_alert.3587626459 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 52058655 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587626459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 70.edn_alert.3587626459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/70.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/70.edn_err.644937445 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 44666917 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644937445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 70.edn_err.644937445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/70.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/70.edn_genbits.2990931578 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 42277972 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:06 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990931578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2990931578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/70.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/71.edn_alert.1288493135 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 197019888 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:06 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288493135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 71.edn_alert.1288493135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/71.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/71.edn_err.3777138181 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 29856529 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777138181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 71.edn_err.3777138181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/71.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/71.edn_genbits.3098778985 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 42271595 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098778985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3098778985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/71.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/72.edn_alert.1351011491 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 23412570 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:06 PM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351011491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 72.edn_alert.1351011491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/72.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/72.edn_err.4223967574 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 46549021 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223967574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 72.edn_err.4223967574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/72.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/72.edn_genbits.1443344825 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 36633854 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:06 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443344825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1443344825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/72.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/73.edn_alert.1742898621 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 78919766 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:06 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742898621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 73.edn_alert.1742898621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/73.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/73.edn_err.2318768405 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 60554320 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:06 PM UTC 24 |
| Peak memory | 244140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318768405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 73.edn_err.2318768405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/73.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/73.edn_genbits.1101102964 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 100799849 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101102964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1101102964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/73.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/74.edn_alert.2531331718 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 26433745 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:05 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531331718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 74.edn_alert.2531331718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/74.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/74.edn_err.2331230018 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 18874299 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 02:17:05 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331230018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 74.edn_err.2331230018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/74.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/74.edn_genbits.2065907125 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 112982303 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 02:17:03 PM UTC 24 |
| Finished | Oct 12 02:17:07 PM UTC 24 |
| Peak memory | 233152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065907125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2065907125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/74.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/75.edn_alert.1975696857 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 23610492 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975696857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 75.edn_alert.1975696857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/75.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/75.edn_err.514357028 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 25632693 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 238440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514357028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 75.edn_err.514357028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/75.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/75.edn_genbits.560733374 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 51320417 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 02:17:05 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560733374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 75.edn_genbits.560733374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/75.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/76.edn_alert.3756067884 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 27270613 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756067884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 76.edn_alert.3756067884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/76.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/76.edn_err.1148376037 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 30687498 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148376037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 76.edn_err.1148376037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/76.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/76.edn_genbits.942542533 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 110380828 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942542533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 76.edn_genbits.942542533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/76.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/77.edn_alert.992150592 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 40076480 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992150592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 77.edn_alert.992150592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/77.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/77.edn_err.513143578 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 33982297 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513143578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 77.edn_err.513143578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/77.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/77.edn_genbits.1781458404 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 89368387 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:08 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781458404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1781458404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/77.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/78.edn_alert.808600857 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 27618782 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:10 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808600857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 78.edn_alert.808600857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/78.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/78.edn_err.1547933386 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 20545350 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:10 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547933386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 78.edn_err.1547933386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/78.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/78.edn_genbits.1341987602 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 44570426 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 02:17:06 PM UTC 24 |
| Finished | Oct 12 02:17:09 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341987602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1341987602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/78.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/79.edn_alert.3442469788 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 23959077 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:10 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442469788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 79.edn_alert.3442469788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/79.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/79.edn_err.3840519457 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 18932321 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:10 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840519457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 79.edn_err.3840519457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/79.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/79.edn_genbits.1848747761 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 39671033 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848747761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1848747761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/79.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_alert_test.2140833461 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 80554590 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 228580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140833461 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2140833461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_disable.503232583 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 72123879 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 228036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503232583 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.503232583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.2512346313 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 51374631 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512346313 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.2512346313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_err.3045957142 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 24606432 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 238428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045957142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 8.edn_err.3045957142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_genbits.2775125506 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 108339301 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 02:14:57 PM UTC 24 |
| Finished | Oct 12 02:14:59 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775125506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2775125506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_intr.788455513 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 20580716 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:14:57 PM UTC 24 |
| Finished | Oct 12 02:14:59 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788455513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.788455513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_regwen.3868107624 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 15279589 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:14:56 PM UTC 24 |
| Finished | Oct 12 02:14:59 PM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868107624 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 8.edn_regwen.3868107624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/8.edn_smoke.2600792481 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 17790325 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 02:14:55 PM UTC 24 |
| Finished | Oct 12 02:14:57 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600792481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.edn_smoke.2600792481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/8.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/80.edn_alert.2952530673 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 49762481 ps |
| CPU time | 1.65 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952530673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 80.edn_alert.2952530673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/80.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/80.edn_err.2399541908 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 36119777 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:10 PM UTC 24 |
| Peak memory | 238248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399541908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 80.edn_err.2399541908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/80.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/80.edn_genbits.3025307723 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 40212574 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:10 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025307723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3025307723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/80.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/81.edn_alert.2010082016 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 27957573 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010082016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 81.edn_alert.2010082016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/81.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/81.edn_err.2452458400 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 18300076 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:17:09 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452458400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 81.edn_err.2452458400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/81.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/81.edn_genbits.1089999520 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 71168360 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 02:17:08 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089999520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1089999520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/81.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/82.edn_alert.4122719377 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 24385777 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:17:09 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122719377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 82.edn_alert.4122719377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/82.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/82.edn_err.614864885 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 32192375 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 02:17:09 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614864885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 82.edn_err.614864885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/82.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/82.edn_genbits.243433657 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 105584993 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 02:17:09 PM UTC 24 |
| Finished | Oct 12 02:17:11 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243433657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 82.edn_genbits.243433657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/82.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/83.edn_alert.57085539 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 44306059 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:13 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57085539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.57085539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/83.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/83.edn_err.306295900 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 74252612 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:13 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306295900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 83.edn_err.306295900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/83.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/83.edn_genbits.4153110429 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 118923930 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:13 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153110429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4153110429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/83.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/84.edn_alert.3839098030 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 80660268 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839098030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 84.edn_alert.3839098030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/84.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/84.edn_err.141556617 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 26696737 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:13 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141556617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 84.edn_err.141556617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/84.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/84.edn_genbits.3031963281 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 97841496 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:13 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031963281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3031963281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/84.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/85.edn_alert.3203389661 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 196694082 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203389661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 85.edn_alert.3203389661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/85.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/85.edn_err.2363088212 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 23643722 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363088212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 85.edn_err.2363088212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/85.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/85.edn_genbits.714217253 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 106545241 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714217253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 85.edn_genbits.714217253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/85.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/86.edn_alert.2720200451 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 22661512 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720200451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 86.edn_alert.2720200451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/86.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/86.edn_err.2512281936 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 32968218 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512281936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 86.edn_err.2512281936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/86.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/86.edn_genbits.2332352089 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 52667061 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:11 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332352089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2332352089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/86.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/87.edn_alert.4085387302 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 35641067 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085387302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 87.edn_alert.4085387302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/87.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/87.edn_err.3573084075 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 31958546 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573084075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 87.edn_err.3573084075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/87.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/87.edn_genbits.1222631059 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 45761599 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222631059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1222631059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/87.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/88.edn_alert.3671222790 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 74408274 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671222790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 88.edn_alert.3671222790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/88.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/88.edn_err.3474653538 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 19210886 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 248176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474653538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 88.edn_err.3474653538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/88.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/88.edn_genbits.1129865941 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 185853150 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:16 PM UTC 24 |
| Peak memory | 233212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129865941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1129865941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/88.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/89.edn_alert.2489524814 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 22969682 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:16 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489524814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 89.edn_alert.2489524814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/89.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/89.edn_err.1051569436 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 22859069 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:16 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051569436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 89.edn_err.1051569436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/89.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/89.edn_genbits.761248228 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 48878930 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:12 PM UTC 24 |
| Finished | Oct 12 02:17:14 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761248228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 89.edn_genbits.761248228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/89.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_alert.408441874 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 38253449 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 02:15:00 PM UTC 24 |
| Finished | Oct 12 02:15:02 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408441874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.edn_alert.408441874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_alert_test.726561398 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 48571939 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:15:00 PM UTC 24 |
| Finished | Oct 12 02:15:02 PM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726561398 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.726561398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_disable.1489794342 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 13920203 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:15:00 PM UTC 24 |
| Finished | Oct 12 02:15:02 PM UTC 24 |
| Peak memory | 227984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489794342 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1489794342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.2865235203 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 53370254 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:15:00 PM UTC 24 |
| Finished | Oct 12 02:15:02 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865235203 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.2865235203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_err.2285559592 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 24169015 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 02:15:00 PM UTC 24 |
| Finished | Oct 12 02:15:02 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285559592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 9.edn_err.2285559592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_intr.2252317461 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 21125236 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252317461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2252317461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_regwen.1868333678 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 57602615 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:01 PM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868333678 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 9.edn_regwen.1868333678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_smoke.2191907355 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 60873890 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:00 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191907355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.edn_smoke.2191907355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/9.edn_stress_all.1061127030 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 506989690 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 02:14:58 PM UTC 24 |
| Finished | Oct 12 02:15:05 PM UTC 24 |
| Peak memory | 228920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061127030 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1061127030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/9.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/90.edn_alert.3666817114 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 29876385 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:16 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666817114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 90.edn_alert.3666817114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/90.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/90.edn_err.1630336823 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 26325308 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 248232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630336823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 90.edn_err.1630336823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/90.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/90.edn_genbits.3448837453 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 85462947 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:16 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448837453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3448837453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/90.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/91.edn_alert.947797622 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 83677973 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 232048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947797622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 91.edn_alert.947797622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/91.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/91.edn_err.1032617639 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 44023189 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032617639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 91.edn_err.1032617639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/91.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/91.edn_genbits.1630568970 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 54666662 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630568970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1630568970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/91.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/92.edn_alert.4227531296 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 40412807 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:16 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227531296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 92.edn_alert.4227531296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/92.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/92.edn_err.4286131503 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 130970586 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 244124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286131503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 92.edn_err.4286131503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/92.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/92.edn_genbits.4293512463 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 115751891 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293512463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.4293512463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/92.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/93.edn_alert.3408800830 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 94515645 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408800830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 93.edn_alert.3408800830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/93.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/93.edn_err.3004805723 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 24400979 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 02:17:15 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004805723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 93.edn_err.3004805723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/93.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/93.edn_genbits.1941665976 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 74022472 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:14 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941665976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1941665976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/93.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/94.edn_alert.3148410015 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 23038202 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148410015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 94.edn_alert.3148410015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/94.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/94.edn_err.166502495 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 36003545 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166502495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 94.edn_err.166502495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/94.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/94.edn_genbits.2894478103 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 54298469 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 02:17:15 PM UTC 24 |
| Finished | Oct 12 02:17:17 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894478103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2894478103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/94.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/95.edn_alert.1923295571 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 51491396 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923295571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 95.edn_alert.1923295571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/95.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/95.edn_err.2761026189 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 31938268 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761026189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 95.edn_err.2761026189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/95.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/95.edn_genbits.2667386797 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 63296221 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667386797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2667386797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/95.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/96.edn_alert.3681470697 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 25558496 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681470697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 96.edn_alert.3681470697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/96.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/96.edn_err.539159303 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 24786357 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 246124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539159303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 96.edn_err.539159303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/96.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/96.edn_genbits.3192999958 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 21339119 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192999958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3192999958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/96.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/97.edn_alert.1588714636 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 27687248 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588714636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 97.edn_alert.1588714636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/97.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/97.edn_err.1553149667 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 30624927 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553149667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 97.edn_err.1553149667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/97.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/97.edn_genbits.3451881947 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 183171336 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451881947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3451881947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/97.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/98.edn_alert.3604673486 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 108774573 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:20 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604673486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 98.edn_alert.3604673486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/98.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/98.edn_err.2114805174 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 100570925 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:19 PM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114805174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 98.edn_err.2114805174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/98.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/98.edn_genbits.1849243489 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 146333622 ps |
| CPU time | 3.37 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 233084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849243489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1849243489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/98.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/99.edn_alert.3180332941 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 30785923 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 02:17:19 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180332941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 99.edn_alert.3180332941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/99.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/99.edn_err.1409112126 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 57731312 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 02:17:19 PM UTC 24 |
| Finished | Oct 12 02:17:22 PM UTC 24 |
| Peak memory | 238444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409112126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 99.edn_err.1409112126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/99.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/default/99.edn_genbits.3797146244 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 273800252 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 02:17:17 PM UTC 24 |
| Finished | Oct 12 02:17:20 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797146244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3797146244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/99.edn_genbits/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |