Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 7233 1 T4 14 T56 22 T57 18
all_values[1] 7233 1 T4 14 T56 22 T57 18


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 7520 1 T4 16 T56 22 T57 27
auto[1] 6946 1 T4 12 T56 22 T57 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 5767 1 T4 12 T56 10 T57 19
auto[1] 8699 1 T4 16 T56 34 T57 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 8550 1 T4 19 T56 23 T57 21
auto[1] 5916 1 T4 9 T56 21 T57 15


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intr   cp_intr_test   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] auto[0] 1524 1 T4 3 T56 3 T57 7
all_values[0] auto[0] auto[0] auto[1] 723 1 T4 2 T56 4 T57 1
all_values[0] auto[0] auto[1] auto[0] 1327 1 T4 3 T56 1 T57 2
all_values[0] auto[0] auto[1] auto[1] 713 1 T4 2 T56 3 T212 1
all_values[0] auto[1] auto[0] auto[1] 1506 1 T4 3 T56 5 T57 6
all_values[0] auto[1] auto[1] auto[1] 1440 1 T4 1 T56 6 T57 2
all_values[1] auto[0] auto[0] auto[0] 1593 1 T4 4 T56 3 T57 7
all_values[1] auto[0] auto[0] auto[1] 633 1 T56 1 T90 1 T322 1
all_values[1] auto[0] auto[1] auto[0] 1323 1 T4 2 T56 3 T57 3
all_values[1] auto[0] auto[1] auto[1] 714 1 T4 3 T56 5 T57 1
all_values[1] auto[1] auto[0] auto[1] 1541 1 T4 4 T56 6 T57 6
all_values[1] auto[1] auto[1] auto[1] 1429 1 T4 1 T56 4 T57 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal